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[wip] channels added

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bartool
2023-07-31 14:04:45 +02:00
parent d7e25af8bf
commit a690f3a209
11 changed files with 247 additions and 180 deletions
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89
firmware/shared_libs/controllers/ctrl_generator.c
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@@ -9,12 +9,19 @@
typedef struct FG_handle_s FG_handle_t;
typedef struct
{
GPIO_TypeDef *port;
uint16_t pin;
} GEN_led_t;
struct FG_handle_s
{
ad9833_handle_t hdds;
ltc2631_handle_t hoffs;
mcp41x_handle_t hampl;
FG_handle_t *link[2];
GEN_led_t hled;
};
typedef uint8_t timer_handle_t;
@@ -23,6 +30,7 @@ typedef struct
timer_handle_t hpwm;
ltc2631_handle_t hoffs;
mcp41x_handle_t hampl;
GEN_led_t hled;
} PWM_handle_t;
typedef enum
@@ -61,12 +69,29 @@ uint8_t ch_to_gen_ch[CHANNEL_MAX] = {FG_CHAN1, FG_CHAN2, FG_CHAN3, PWM_CHAN1, PW
// #define AMP1_CS_PIN GPIO_PIN_0
// #define AMP2_CS_PIN GPIO_PIN_0
// #define AMP3_CS_PIN GPIO_PIN_0
void led_init(GEN_led_t *hled, GPIO_TypeDef *port, uint16_t pin)
{
hled->port = port;
hled->pin = pin;
HAL_GPIO_WritePin(port, pin, GPIO_PIN_SET);
}
void led_on(GEN_led_t *hled)
{
HAL_GPIO_WritePin(hled->port, hled->pin, GPIO_PIN_RESET);
}
void led_off(GEN_led_t *hled)
{
HAL_GPIO_WritePin(hled->port, hled->pin, GPIO_PIN_SET);
}
void gen_init()
{
ad9833_init(&dds_gen[FG_CHAN1].hdds, &hspi2, DDS1_CS_GPIO_Port, DDS1_CS_Pin);
ad9833_setMode(&dds_gen[FG_CHAN1].hdds, MODE_OFF);
// ad9833_init(&dds_gen[FG_CHAN2].hdds, &hspi2, DDS2_CS_PORT, DDS2_CS_PIN);
ad9833_init(&dds_gen[FG_CHAN2].hdds, &hspi2, DDS2_CS_GPIO_Port, DDS2_CS_Pin);
// ad9833_init(&dds_gen[FG_CHAN3].hdds, &hspi2, DDS3_CS_PORT, DDS3_CS_PIN);
// ltc2631_init(&dds_gen[FG_CHAN1].hoffs, &hi2c1, 0x00, LTC2631_8BIT, LTC_REF_2V5);
@@ -75,8 +100,10 @@ void gen_init()
mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP1_CS_GPIO_Port, AMP1_CS_Pin, MCP41X_10K);
mcp41x_setValue(&dds_gen[FG_CHAN1].hampl, 0);
// mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP2_CS_PORT, AMP2_CS_PIN, MCP41X_10K);
mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP2_CS_GPIO_Port, AMP2_CS_Pin, MCP41X_10K);
// mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP3_CS_PORT, AMP3_CS_PIN, MCP41X_10K);
led_init(&dds_gen[FG_CHAN1].hled, LED_CH1_GPIO_Port, LED_CH1_Pin);
}
static void _setAmpliude(mcp41x_handle_t *hampl, uint16_t ampl_x100)
@@ -126,16 +153,18 @@ static void _setWaveDdsGen(ad9833_handle_t *hdds, GEN_wave_t wave)
}
}
static void _setEnabledDdsGen(ad9833_handle_t *hdds, GEN_fg_t *gen)
static void _setEnabledDdsGen(FG_handle_t *hfg, GEN_fg_t *gen)
{
ULOG_DEBUG("(%d:_setAmplitude) phase: %d", __LINE__, gen->enabled);
switch (gen->enabled)
{
case FALSE:
ad9833_setMode(hdds, MODE_OFF);
ad9833_setMode(&hfg->hdds, MODE_OFF);
led_off(&hfg->hled);
break;
case TRUE:
_setWaveDdsGen(hdds, gen->wave);
_setWaveDdsGen(&hfg->hdds, gen->wave);
led_on(&hfg->hled);
break;
default:
@@ -156,13 +185,13 @@ static void _setDutyPwmGen(timer_handle_t *hpwm, uint8_t duty)
{
}
static void _setEnabledPwmGen(timer_handle_t *hpwm, bool_t en)
static void _setEnabledPwmGen(PWM_handle_t *hpwm, bool_t en)
{
}
void setFreq(GENERATOR_t *gen, GEN_channel_t channel)
void setFreq(GEN_sig_t *gen, GEN_channel_t channel)
{
switch (gen->gen_type)
switch (gen->type)
{
case GEN_FG_TYPE:
_setFreqDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->frequency);
@@ -172,14 +201,14 @@ void setFreq(GENERATOR_t *gen, GEN_channel_t channel)
break;
default:
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type);
break;
}
}
void setAmplitude(GENERATOR_t *gen, GEN_channel_t channel)
void setAmplitude(GEN_sig_t *gen, GEN_channel_t channel)
{
switch (gen->gen_type)
switch (gen->type)
{
case GEN_FG_TYPE:
_setAmpliude(&dds_gen[ch_to_gen_ch[channel]].hampl, ((GEN_fg_t *)gen->gen)->amplitude);
@@ -189,14 +218,14 @@ void setAmplitude(GENERATOR_t *gen, GEN_channel_t channel)
break;
default:
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type);
break;
}
}
void setOfsset(GENERATOR_t *gen, GEN_channel_t channel)
void setOfsset(GEN_sig_t *gen, GEN_channel_t channel)
{
switch (gen->gen_type)
switch (gen->type)
{
case GEN_FG_TYPE:
_setOffset(&dds_gen[ch_to_gen_ch[channel]].hoffs, ((GEN_fg_t *)gen->gen)->offset);
@@ -206,14 +235,14 @@ void setOfsset(GENERATOR_t *gen, GEN_channel_t channel)
break;
default:
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type);
break;
}
}
void setPhase(GENERATOR_t *gen, GEN_channel_t channel)
void setPhase(GEN_sig_t *gen, GEN_channel_t channel)
{
switch (gen->gen_type)
switch (gen->type)
{
case GEN_FG_TYPE:
_setPhaseDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->phase);
@@ -223,56 +252,56 @@ void setPhase(GENERATOR_t *gen, GEN_channel_t channel)
break;
default:
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type);
break;
}
}
void setWave(GENERATOR_t *gen, GEN_channel_t channel)
void setWave(GEN_sig_t *gen, GEN_channel_t channel)
{
switch (gen->gen_type)
switch (gen->type)
{
case GEN_FG_TYPE:
_setWaveDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->wave);
break;
default:
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type);
break;
}
}
void setDuty(GENERATOR_t *gen, GEN_channel_t channel)
void setDuty(GEN_sig_t *gen, GEN_channel_t channel)
{
switch (gen->gen_type)
switch (gen->type)
{
case GEN_PWM_TYPE:
_setDutyPwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->duty);
break;
default:
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type);
break;
}
}
void setEnabled(GENERATOR_t *gen, GEN_channel_t channel)
void setEnabled(GEN_sig_t *gen, GEN_channel_t channel)
{
switch (gen->gen_type)
switch (gen->type)
{
case GEN_FG_TYPE:
_setEnabledDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen));
_setEnabledDdsGen(&dds_gen[ch_to_gen_ch[channel]], ((GEN_fg_t *)gen->gen));
break;
case GEN_PWM_TYPE:
_setEnabledPwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->enabled);
_setEnabledPwmGen(&pwm_gen[ch_to_gen_ch[channel]], ((GEN_pwm_t *)gen->gen)->enabled);
break;
default:
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type);
break;
}
}
void setLink(GENERATOR_t *source_gen, GEN_channel_t source_ch, GENERATOR_t *dest_gen, GEN_channel_t dest_ch)
void setLink(GEN_sig_t *source_gen, GEN_channel_t source_ch, GEN_sig_t *dest_gen, GEN_channel_t dest_ch)
{
}