59064 lines
2.4 MiB
59064 lines
2.4 MiB
<?xml version="1.0" encoding="UTF-8"?>
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<!--
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Copyright (c) 2020 STMicroelectronics.
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SPDX-License-Identifier: Apache-2.0
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
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<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
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<name>STM32G474xx</name>
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<version>1.6</version>
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<description>STM32G474xx</description>
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<cpu>
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<name>CM4</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>true</mpuPresent>
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<fpuPresent>true</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<!--Bus Interface Properties-->
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<!--Cortex-M3 is byte addressable-->
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<addressUnitBits>8</addressUnitBits>
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<!--the maximum data bit width accessible within a single transfer-->
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<width>32</width>
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<!--Register Default Properties-->
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<size>0x20</size>
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<resetValue>0x0</resetValue>
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<resetMask>0xFFFFFFFF</resetMask>
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<peripherals>
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<peripheral>
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<name>CRC</name>
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<description>Cyclic redundancy check calculation unit</description>
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<groupName>CRC</groupName>
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<baseAddress>0x40023000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>DR</name>
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<displayName>DR</displayName>
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<description>Data register</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0xFFFFFFFF</resetValue>
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<fields>
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<field>
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<name>DR</name>
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<description>Data register bits</description>
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<bitOffset>0</bitOffset>
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<bitWidth>32</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>IDR</name>
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<displayName>IDR</displayName>
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<description>Independent data register</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>IDR</name>
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<description>General-purpose 8-bit data register bits</description>
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<bitOffset>0</bitOffset>
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<bitWidth>32</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CR</name>
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<displayName>CR</displayName>
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<description>Control register</description>
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<addressOffset>0x8</addressOffset>
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<size>0x20</size>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>REV_OUT</name>
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<description>Reverse output data</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>REV_IN</name>
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<description>Reverse input data</description>
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<bitOffset>5</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>POLYSIZE</name>
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<description>Polynomial size</description>
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<bitOffset>3</bitOffset>
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<bitWidth>2</bitWidth>
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<access>read-write</access>
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</field>
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<field>
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<name>RESET</name>
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<description>RESET bit</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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<access>write-only</access>
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</field>
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</fields>
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</register>
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<register>
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<name>INIT</name>
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<displayName>INIT</displayName>
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<description>Initial CRC value</description>
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<addressOffset>0x10</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0xFFFFFFFF</resetValue>
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<fields>
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<field>
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<name>CRC_INIT</name>
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<description>Programmable initial CRC value</description>
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<bitOffset>0</bitOffset>
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<bitWidth>32</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>POL</name>
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<displayName>POL</displayName>
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<description>polynomial</description>
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<addressOffset>0x14</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x04C11DB7</resetValue>
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<fields>
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<field>
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<name>POL</name>
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<description>Programmable polynomial</description>
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<bitOffset>0</bitOffset>
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<bitWidth>32</bitWidth>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>IWDG</name>
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<description>WinWATCHDOG</description>
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<groupName>IWDG</groupName>
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<baseAddress>0x40003000</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>KR</name>
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<displayName>KR</displayName>
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<description>Key register</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>write-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>KEY</name>
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<description>Key value (write only, read 0x0000)</description>
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<bitOffset>0</bitOffset>
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<bitWidth>16</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>PR</name>
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<displayName>PR</displayName>
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<description>Prescaler register</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>PR</name>
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<description>Prescaler divider</description>
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<bitOffset>0</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>RLR</name>
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<displayName>RLR</displayName>
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<description>Reload register</description>
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<addressOffset>0x8</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000FFF</resetValue>
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<fields>
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<field>
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<name>RL</name>
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<description>Watchdog counter reload value</description>
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<bitOffset>0</bitOffset>
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<bitWidth>12</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>SR</name>
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<displayName>SR</displayName>
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<description>Status register</description>
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<addressOffset>0xC</addressOffset>
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<size>0x20</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>WVU</name>
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<description>Watchdog counter window value update</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>RVU</name>
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<description>Watchdog counter reload value update</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>PVU</name>
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<description>Watchdog prescaler value update</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>WINR</name>
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<displayName>WINR</displayName>
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<description>Window register</description>
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<addressOffset>0x10</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000FFF</resetValue>
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<fields>
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<field>
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<name>WIN</name>
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<description>Watchdog counter window value</description>
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<bitOffset>0</bitOffset>
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<bitWidth>12</bitWidth>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>WWDG</name>
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<description>System window watchdog</description>
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<groupName>WWDG</groupName>
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<baseAddress>0x40002C00</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<registers>
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<register>
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<name>CR</name>
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<displayName>CR</displayName>
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<description>Control register</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x0000007F</resetValue>
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<fields>
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<field>
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<name>WDGA</name>
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<description>Activation bit</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>T</name>
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<description>7-bit counter (MSB to LSB)</description>
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<bitOffset>0</bitOffset>
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<bitWidth>7</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CFR</name>
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<displayName>CFR</displayName>
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<description>Configuration register</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x0000007F</resetValue>
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<fields>
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<field>
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<name>WDGTB</name>
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<description>Timer base</description>
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<bitOffset>11</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>EWI</name>
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<description>Early wakeup interrupt</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>W</name>
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<description>7-bit window value</description>
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<bitOffset>0</bitOffset>
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<bitWidth>7</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>SR</name>
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<displayName>SR</displayName>
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<description>Status register</description>
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<addressOffset>0x8</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>EWIF</name>
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<description>Early wakeup interrupt flag</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>I2C1</name>
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<description>Inter-integrated circuit</description>
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<groupName>I2C</groupName>
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<baseAddress>0x40005400</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>I2C1_EV</name>
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<description>I2C1_EV</description>
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<value>31</value>
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</interrupt>
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<interrupt>
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<name>I2C1_ER</name>
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<description>I2C1_ER</description>
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<value>32</value>
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</interrupt>
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<registers>
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<register>
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<name>CR1</name>
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<displayName>CR1</displayName>
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<description>Control register 1</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>PE</name>
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<description>Peripheral enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>TXIE</name>
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<description>TX Interrupt enable</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>RXIE</name>
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<description>RX Interrupt enable</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ADDRIE</name>
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<description>Address match interrupt enable (slave only)</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>NACKIE</name>
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<description>Not acknowledge received interrupt enable</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>STOPIE</name>
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<description>STOP detection Interrupt enable</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>TCIE</name>
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<description>Transfer Complete interrupt enable</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ERRIE</name>
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<description>Error interrupts enable</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>DNF</name>
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<description>Digital noise filter</description>
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<bitOffset>8</bitOffset>
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<bitWidth>4</bitWidth>
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</field>
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<field>
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<name>ANFOFF</name>
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<description>Analog noise filter OFF</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>TXDMAEN</name>
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<description>DMA transmission requests enable</description>
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<bitOffset>14</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>RXDMAEN</name>
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<description>DMA reception requests enable</description>
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<bitOffset>15</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>SBC</name>
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<description>Slave byte control</description>
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<bitOffset>16</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>NOSTRETCH</name>
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<description>Clock stretching disable</description>
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<bitOffset>17</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WUPEN</name>
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<description>Wakeup from STOP enable</description>
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<bitOffset>18</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>GCEN</name>
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<description>General call enable</description>
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<bitOffset>19</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>SMBHEN</name>
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<description>SMBus Host address enable</description>
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<bitOffset>20</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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|
<name>SMBDEN</name>
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<description>SMBus Device Default address enable</description>
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<bitOffset>21</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ALERTEN</name>
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<description>SMBUS alert enable</description>
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<bitOffset>22</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>PECEN</name>
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<description>PEC enable</description>
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<bitOffset>23</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
|
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<name>CR2</name>
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<displayName>CR2</displayName>
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<description>Control register 2</description>
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<addressOffset>0x4</addressOffset>
|
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
|
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<name>PECBYTE</name>
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<description>Packet error checking byte</description>
|
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<bitOffset>26</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
|
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<field>
|
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<name>AUTOEND</name>
|
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<description>Automatic end mode (master mode)</description>
|
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<bitOffset>25</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>NBYTES reload mode</description>
|
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<bitOffset>24</bitOffset>
|
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<bitWidth>1</bitWidth>
|
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</field>
|
|
<field>
|
|
<name>NBYTES</name>
|
|
<description>Number of bytes</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>NACK generation (slave mode)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop generation (master mode)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start generation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HEAD10R</name>
|
|
<description>10-bit address header only read direction (master receiver mode)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADD10</name>
|
|
<description>10-bit addressing mode (master mode)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RD_WRN</name>
|
|
<description>Transfer direction (master mode)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SADD</name>
|
|
<description>Slave address bit (master mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OAR1</name>
|
|
<displayName>OAR1</displayName>
|
|
<description>Own address register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OA1</name>
|
|
<description>Interface address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA1MODE</name>
|
|
<description>Own Address 1 10-bit mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA1EN</name>
|
|
<description>Own Address 1 enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OAR2</name>
|
|
<displayName>OAR2</displayName>
|
|
<description>Own address register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OA2</name>
|
|
<description>Interface address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA2MSK</name>
|
|
<description>Own Address 2 masks</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OA2EN</name>
|
|
<description>Own Address 2 enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMINGR</name>
|
|
<displayName>TIMINGR</displayName>
|
|
<description>Timing register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SCLL</name>
|
|
<description>SCL low period (master mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLH</name>
|
|
<description>SCL high period (master mode)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDADEL</name>
|
|
<description>Data hold time</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCLDEL</name>
|
|
<description>Data setup time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Timing prescaler</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMEOUTR</name>
|
|
<displayName>TIMEOUTR</displayName>
|
|
<description>Status register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEOUTA</name>
|
|
<description>Bus timeout A</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIDLE</name>
|
|
<description>Idle clock timeout detection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMOUTEN</name>
|
|
<description>Clock timeout enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUTB</name>
|
|
<description>Bus timeout B</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEXTEN</name>
|
|
<description>Extended clock timeout enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt and Status register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDCODE</name>
|
|
<description>Address match code (Slave mode)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Transfer direction (Slave mode)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALERT</name>
|
|
<description>SMBus alert</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout or t_low detection flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PECERR</name>
|
|
<description>PEC Error in reception</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Overrun/Underrun (slave mode)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ARLO</name>
|
|
<description>Arbitration lost</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>Bus error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCR</name>
|
|
<description>Transfer Complete Reload</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transfer Complete (master mode)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>Stop detection flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NACKF</name>
|
|
<description>Not acknowledge received flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address matched (slave mode)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>Receive data register not empty (receivers)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXIS</name>
|
|
<description>Transmit interrupt status (transmitters)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmit data register empty (transmitters)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt clear register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALERTCF</name>
|
|
<description>Alert flag clear</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMOUTCF</name>
|
|
<description>Timeout detection flag clear</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECCF</name>
|
|
<description>PEC Error flag clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRCF</name>
|
|
<description>Overrun/Underrun flag clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARLOCF</name>
|
|
<description>Arbitration lost flag clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BERRCF</name>
|
|
<description>Bus error flag clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOPCF</name>
|
|
<description>Stop detection flag clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NACKCF</name>
|
|
<description>Not Acknowledge flag clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDRCF</name>
|
|
<description>Address Matched flag clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PECR</name>
|
|
<displayName>PECR</displayName>
|
|
<description>PEC register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Packet error checking register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDR</name>
|
|
<displayName>RXDR</displayName>
|
|
<description>Receive data register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>8-bit receive data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDR</name>
|
|
<displayName>TXDR</displayName>
|
|
<description>Transmit data register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>8-bit transmit data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C1">
|
|
<name>I2C2</name>
|
|
<baseAddress>0x40005800</baseAddress>
|
|
<interrupt>
|
|
<name>WWDG</name>
|
|
<description>Window Watchdog interrupt</description>
|
|
<value>0</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_EV</name>
|
|
<description>I2C2_EV</description>
|
|
<value>33</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C2_ER</name>
|
|
<description>I2C2_ER</description>
|
|
<value>34</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C1">
|
|
<name>I2C3</name>
|
|
<baseAddress>0x40007800</baseAddress>
|
|
<interrupt>
|
|
<name>I2C3_EV</name>
|
|
<description>I2C3_EV</description>
|
|
<value>92</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C3_ER</name>
|
|
<description>I2C3_ER</description>
|
|
<value>93</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C1">
|
|
<name>I2C4</name>
|
|
<baseAddress>0x40008400</baseAddress>
|
|
<interrupt>
|
|
<name>I2C4_EV</name>
|
|
<description>I2C4_EV</description>
|
|
<value>82</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>I2C4_ER</name>
|
|
<description>I2C4_ER</description>
|
|
<value>83</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASH</name>
|
|
<description>Flash</description>
|
|
<groupName>Flash</groupName>
|
|
<baseAddress>0x40022000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLASH</name>
|
|
<description>FLASH</description>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ACR</name>
|
|
<displayName>ACR</displayName>
|
|
<description>Access control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000600</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LATENCY</name>
|
|
<description>Latency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRFTEN</name>
|
|
<description>Prefetch enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICEN</name>
|
|
<description>Instruction cache enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCEN</name>
|
|
<description>Data cache enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICRST</name>
|
|
<description>Instruction cache reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCRST</name>
|
|
<description>Data cache reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RUN_PD</name>
|
|
<description>Flash Power-down mode during Low-power run mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLEEP_PD</name>
|
|
<description>Flash Power-down mode during Low-power sleep mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_SWEN</name>
|
|
<description>Debug software enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDKEYR</name>
|
|
<displayName>PDKEYR</displayName>
|
|
<description>Power down key register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PDKEYR</name>
|
|
<description>RUN_PD in FLASH_ACR key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYR</name>
|
|
<displayName>KEYR</displayName>
|
|
<description>Flash key register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEYR</name>
|
|
<description>KEYR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPTKEYR</name>
|
|
<displayName>OPTKEYR</displayName>
|
|
<description>Option byte key register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPTKEYR</name>
|
|
<description>Option byte key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EOP</name>
|
|
<description>End of operation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPERR</name>
|
|
<description>Operation error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PROGERR</name>
|
|
<description>Programming error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRPERR</name>
|
|
<description>Write protected error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PGAERR</name>
|
|
<description>Programming alignment error</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SIZERR</name>
|
|
<description>Size error</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PGSERR</name>
|
|
<description>Programming sequence error</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MISERR</name>
|
|
<description>Fast programming data miss error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FASTERR</name>
|
|
<description>Fast programming error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RDERR</name>
|
|
<description>PCROP read error</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPTVERR</name>
|
|
<description>Option validity error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Flash control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PG</name>
|
|
<description>Programming</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Page erase</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MER1</name>
|
|
<description>Bank 1 Mass erase</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PNB</name>
|
|
<description>Page number</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STRT</name>
|
|
<description>Start</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTSTRT</name>
|
|
<description>Options modification start</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSTPG</name>
|
|
<description>Fast programming</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOPIE</name>
|
|
<description>End of operation interrupt enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDERRIE</name>
|
|
<description>PCROP read error interrupt enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OBL_LAUNCH</name>
|
|
<description>Force the option byte loading</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEC_PROT1</name>
|
|
<description>SEC_PROT1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTLOCK</name>
|
|
<description>Options Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>FLASH_CR Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCR</name>
|
|
<displayName>ECCR</displayName>
|
|
<description>Flash ECC register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDR_ECC</name>
|
|
<description>ECC fail address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BK_ECC</name>
|
|
<description>BK_ECC</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SYSF_ECC</name>
|
|
<description>SYSF_ECC</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ECCIE</name>
|
|
<description>ECCIE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECCC2</name>
|
|
<description>ECC correction</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECCD2</name>
|
|
<description>ECC2 detection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECCC</name>
|
|
<description>ECC correction</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECCD</name>
|
|
<description>ECC detection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPTR</name>
|
|
<displayName>OPTR</displayName>
|
|
<description>Flash option register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xF0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDP</name>
|
|
<description>Read protection level</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOR_LEV</name>
|
|
<description>BOR reset Level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nRST_STOP</name>
|
|
<description>nRST_STOP</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nRST_STDBY</name>
|
|
<description>nRST_STDBY</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nRST_SHDW</name>
|
|
<description>nRST_SHDW</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDWG_SW</name>
|
|
<description>Independent watchdog selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IWDG_STOP</name>
|
|
<description>Independent watchdog counter freeze in Stop mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IWDG_STDBY</name>
|
|
<description>Independent watchdog counter freeze in Standby mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDG_SW</name>
|
|
<description>Window watchdog selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nBOOT1</name>
|
|
<description>Boot configuration</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM2_PE</name>
|
|
<description>SRAM2 parity check enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM2_RST</name>
|
|
<description>SRAM2 Erase when system reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nSWBOOT0</name>
|
|
<description>nSWBOOT0</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>nBOOT0</name>
|
|
<description>nBOOT0</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRST_MODE</name>
|
|
<description>NRST_MODE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IRHEN</name>
|
|
<description>IRHEN</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCROP1SR</name>
|
|
<displayName>PCROP1SR</displayName>
|
|
<description>Flash Bank 1 PCROP Start address register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCROP1_STRT</name>
|
|
<description>Bank 1 PCROP area start offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCROP1ER</name>
|
|
<displayName>PCROP1ER</displayName>
|
|
<description>Flash Bank 1 PCROP End address register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PCROP1_END</name>
|
|
<description>Bank 1 PCROP area end offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCROP_RDP</name>
|
|
<description>PCROP area preserved when RDP level decreased</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRP1AR</name>
|
|
<displayName>WRP1AR</displayName>
|
|
<description>Flash Bank 1 WRP area A address register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRP1A_STRT</name>
|
|
<description>Bank 1 WRP first area start offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRP1A_END</name>
|
|
<description>Bank 1 WRP first area A end offset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRP1BR</name>
|
|
<displayName>WRP1BR</displayName>
|
|
<description>Flash Bank 1 WRP area B address register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRP1B_STRT</name>
|
|
<description>Bank 1 WRP second area B end offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRP1B_END</name>
|
|
<description>Bank 1 WRP second area B start offset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SEC1R</name>
|
|
<displayName>SEC1R</displayName>
|
|
<description>securable area bank1 register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF00FF00</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOOT_LOCK</name>
|
|
<description>BOOT_LOCK</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEC_SIZE1</name>
|
|
<description>SEC_SIZE1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DBGMCU</name>
|
|
<description>Debug support</description>
|
|
<groupName>DBGMCU</groupName>
|
|
<baseAddress>0xE0042000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>IDCODE</name>
|
|
<displayName>IDCODE</displayName>
|
|
<description>MCU Device ID Code Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEV_ID</name>
|
|
<description>Device Identifier</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REV_ID</name>
|
|
<description>Revision Identifier</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Debug MCU Configuration Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_SLEEP</name>
|
|
<description>Debug Sleep Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_STOP</name>
|
|
<description>Debug Stop Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_STANDBY</name>
|
|
<description>Debug Standby Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRACE_IOEN</name>
|
|
<description>Trace pin assignment control</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRACE_MODE</name>
|
|
<description>Trace pin assignment control</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1L_FZ</name>
|
|
<displayName>APB1L_FZ</displayName>
|
|
<description>APB Low Freeze Register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_TIMER2_STOP</name>
|
|
<description>Debug Timer 2 stopped when Core is halted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM3_STOP</name>
|
|
<description>TIM3 counter stopped when core is halted</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM4_STOP</name>
|
|
<description>TIM4 counter stopped when core is halted</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM5_STOP</name>
|
|
<description>TIM5 counter stopped when core is halted</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER6_STOP</name>
|
|
<description>Debug Timer 6 stopped when Core is halted</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM7_STOP</name>
|
|
<description>TIM7 counter stopped when core is halted</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_RTC_STOP</name>
|
|
<description>Debug RTC stopped when Core is halted</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_WWDG_STOP</name>
|
|
<description>Debug Window Wachdog stopped when Core is halted</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_IWDG_STOP</name>
|
|
<description>Debug Independent Wachdog stopped when Core is halted</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_I2C1_STOP</name>
|
|
<description>I2C1 SMBUS timeout mode stopped when core is halted</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_I2C2_STOP</name>
|
|
<description>I2C2 SMBUS timeout mode stopped when core is halted</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_I2C3_STOP</name>
|
|
<description>I2C3 SMBUS timeout mode stopped when core is halted</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_LPTIMER_STOP</name>
|
|
<description>LPTIM1 counter stopped when core is halted</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1H_FZ</name>
|
|
<displayName>APB1H_FZ</displayName>
|
|
<description>APB Low Freeze Register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_I2C4_STOP</name>
|
|
<description>DBG_I2C4_STOP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB2_FZ</name>
|
|
<displayName>APB2_FZ</displayName>
|
|
<description>APB High Freeze Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_TIM1_STOP</name>
|
|
<description>TIM1 counter stopped when core is halted</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM8_STOP</name>
|
|
<description>TIM8 counter stopped when core is halted</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM15_STOP</name>
|
|
<description>TIM15 counter stopped when core is halted</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM16_STOP</name>
|
|
<description>TIM16 counter stopped when core is halted</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM17_STOP</name>
|
|
<description>TIM17 counter stopped when core is halted</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIM20_STOP</name>
|
|
<description>TIM20counter stopped when core is halted</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_HRTIM0_STOP</name>
|
|
<description>DBG_HRTIM0_STOP</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_HRTIM1_STOP</name>
|
|
<description>DBG_HRTIM0_STOP</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_HRTIM2_STOP</name>
|
|
<description>DBG_HRTIM0_STOP</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_HRTIM3_STOP</name>
|
|
<description>DBG_HRTIM0_STOP</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RCC</name>
|
|
<description>Reset and clock control</description>
|
|
<groupName>RCC</groupName>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RCC</name>
|
|
<description>RCC</description>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Clock control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000063</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSYSRDY</name>
|
|
<description>Main PLL clock ready flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSON</name>
|
|
<description>Main PLL enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSECSSON</name>
|
|
<description>Clock security system enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HSEBYP</name>
|
|
<description>HSE crystal oscillator bypass</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSERDY</name>
|
|
<description>HSE clock ready flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HSEON</name>
|
|
<description>HSE clock enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDY</name>
|
|
<description>HSI clock ready flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HSIKERON</name>
|
|
<description>HSI always enable for peripheral kernels</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSION</name>
|
|
<description>HSI clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSCR</name>
|
|
<displayName>ICSCR</displayName>
|
|
<description>Internal clock sources calibration register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x40000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSICAL0</name>
|
|
<description>Internal High Speed clock Calibration</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HSITRIM</name>
|
|
<description>Internal High Speed clock trimming</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>Clock configuration register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000005</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCOPRE</name>
|
|
<description>Microcontroller clock output prescaler</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MCOSEL</name>
|
|
<description>Microcontroller clock output</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PPRE2</name>
|
|
<description>APB high-speed prescaler (APB2)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PPRE1</name>
|
|
<description>PB low-speed prescaler (APB1)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPRE</name>
|
|
<description>AHB prescaler</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWS</name>
|
|
<description>System clock switch status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>System clock switch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLSYSCFGR</name>
|
|
<displayName>PLLSYSCFGR</displayName>
|
|
<description>PLL configuration register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00001000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSYSPDIV</name>
|
|
<description>Main PLL division factor for PLLSAI2CLK</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSR</name>
|
|
<description>Main PLL division factor for PLLCLK (system clock)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSREN</name>
|
|
<description>Main PLL PLLCLK output enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSQ</name>
|
|
<description>Main PLL division factor for PLLUSB1CLK(48 MHz clock)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSQEN</name>
|
|
<description>Main PLL PLLUSB1CLK output enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSP</name>
|
|
<description>Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLPEN</name>
|
|
<description>Main PLL PLLSAI3CLK output enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSN</name>
|
|
<description>Main PLL multiplication factor for VCO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSM</name>
|
|
<description>Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSRC</name>
|
|
<description>Main PLL, PLLSAI1 and PLLSAI2 entry clock source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIER</name>
|
|
<displayName>CIER</displayName>
|
|
<description>Clock interrupt enable register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSIRDYIE</name>
|
|
<description>LSI ready interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYIE</name>
|
|
<description>LSE ready interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYIE</name>
|
|
<description>HSI ready interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSERDYIE</name>
|
|
<description>HSE ready interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSRDYIE</name>
|
|
<description>PLL ready interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSIE</name>
|
|
<description>LSE clock security system interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RC48RDYIE</name>
|
|
<description>HSI48 ready interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIFR</name>
|
|
<displayName>CIFR</displayName>
|
|
<description>Clock interrupt flag register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSIRDYF</name>
|
|
<description>LSI ready interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYF</name>
|
|
<description>LSE ready interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYF</name>
|
|
<description>HSI ready interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSERDYF</name>
|
|
<description>HSE ready interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSRDYF</name>
|
|
<description>PLL ready interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSECSSF</name>
|
|
<description>Clock security system interrupt flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSF</name>
|
|
<description>LSE Clock security system interrupt flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RC48RDYF</name>
|
|
<description>HSI48 ready interrupt flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CICR</name>
|
|
<displayName>CICR</displayName>
|
|
<description>Clock interrupt clear register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSIRDYC</name>
|
|
<description>LSI ready interrupt clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYC</name>
|
|
<description>LSE ready interrupt clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYC</name>
|
|
<description>HSI ready interrupt clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSERDYC</name>
|
|
<description>HSE ready interrupt clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLSYSRDYC</name>
|
|
<description>PLL ready interrupt clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSECSSC</name>
|
|
<description>Clock security system interrupt clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSC</name>
|
|
<description>LSE Clock security system interrupt clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RC48RDYC</name>
|
|
<description>HSI48 oscillator ready interrupt clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB1RSTR</name>
|
|
<displayName>AHB1RSTR</displayName>
|
|
<description>AHB1 peripheral reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMA1RST</name>
|
|
<description>DMA1 reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA2RST</name>
|
|
<description>DMA2 reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUX1RST</name>
|
|
<description>DMAMUXRST</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CORDICRST</name>
|
|
<description>CORDIC reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MATRIXRST</name>
|
|
<description>MATRIX reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLITFRST_</name>
|
|
<description>FLITF reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCRST</name>
|
|
<description>CRC reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB2RSTR</name>
|
|
<displayName>AHB2RSTR</displayName>
|
|
<description>AHB2 peripheral reset register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GPIOARST</name>
|
|
<description>IO port A reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOBRST</name>
|
|
<description>IO port B reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOCRST</name>
|
|
<description>IO port C reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIODRST</name>
|
|
<description>IO port D reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOERST</name>
|
|
<description>IO port E reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOFRST</name>
|
|
<description>IO port F reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOGRST</name>
|
|
<description>IO port G reset</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC12RST</name>
|
|
<description>ADC reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC345RST_</name>
|
|
<description>SAR ADC345 interface reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC1RST_</name>
|
|
<description>DAC1 interface reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC2RST</name>
|
|
<description>DAC2 interface reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC3RST</name>
|
|
<description>DAC3 interface reset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC4RST</name>
|
|
<description>DAC4 interface reset</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRYPTRST</name>
|
|
<description>Cryptography module reset</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RNGRST</name>
|
|
<description>Random Number Generator module reset</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB3RSTR</name>
|
|
<displayName>AHB3RSTR</displayName>
|
|
<description>AHB3 peripheral reset register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FMCRST</name>
|
|
<description>Flexible memory controller reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QUADSPI1RST</name>
|
|
<description>Quad SPI 1 module reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1RSTR1</name>
|
|
<displayName>APB1RSTR1</displayName>
|
|
<description>APB1 peripheral reset register 1</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIM1RST</name>
|
|
<description>Low Power Timer 1 reset</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C3</name>
|
|
<description>I2C3 interface reset</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRRST</name>
|
|
<description>Power interface reset</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FDCANRST</name>
|
|
<description>FDCAN reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBDRST</name>
|
|
<description>USBD reset</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2RST</name>
|
|
<description>I2C2 reset</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1RST</name>
|
|
<description>I2C1 reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART5RST</name>
|
|
<description>UART5 reset</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART4RST</name>
|
|
<description>UART4 reset</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART3RST</name>
|
|
<description>USART3 reset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2RST</name>
|
|
<description>USART2 reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI3RST</name>
|
|
<description>SPI3 reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2RST</name>
|
|
<description>SPI2 reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRSRST</name>
|
|
<description>Clock recovery system reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM7RST</name>
|
|
<description>TIM7 timer reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM6RST</name>
|
|
<description>TIM6 timer reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM5RST</name>
|
|
<description>TIM5 timer reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM4RST</name>
|
|
<description>TIM3 timer reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM3RST</name>
|
|
<description>TIM3 timer reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM2RST</name>
|
|
<description>TIM2 timer reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1RSTR2</name>
|
|
<displayName>APB1RSTR2</displayName>
|
|
<description>APB1 peripheral reset register 2</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPUART1RST</name>
|
|
<description>Low-power UART 1 reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C4RST</name>
|
|
<description>I2C4 reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBPDRST</name>
|
|
<description>USBPD reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB2RSTR</name>
|
|
<displayName>APB2RSTR</displayName>
|
|
<description>APB2 peripheral reset register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCFGRST</name>
|
|
<description>System configuration (SYSCFG) reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM1RST</name>
|
|
<description>TIM1 timer reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1RST</name>
|
|
<description>SPI1 reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM8RST</name>
|
|
<description>TIM8 timer reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1RST</name>
|
|
<description>USART1 reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI4RST</name>
|
|
<description>SPI 4 reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM15RST</name>
|
|
<description>TIM15 timer reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM16RST</name>
|
|
<description>TIM16 timer reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM17RST</name>
|
|
<description>TIM17 timer reset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM20RST</name>
|
|
<description>Timer 20 reset</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAI1RST</name>
|
|
<description>Serial audio interface 1 (SAI1) reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRTIM1RST</name>
|
|
<description>HRTIMER reset</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB1ENR</name>
|
|
<displayName>AHB1ENR</displayName>
|
|
<description>AHB1 peripheral clock enable register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMA1EN</name>
|
|
<description>DMA1 clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA2EN</name>
|
|
<description>DMA2 clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUXEN</name>
|
|
<description>DMAMUX clock enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CORDICEN</name>
|
|
<description>CORDIC clock enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMACEN</name>
|
|
<description>FMAC clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLITFEN</name>
|
|
<description>FLITF clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB2ENR</name>
|
|
<displayName>AHB2ENR</displayName>
|
|
<description>AHB2 peripheral clock enable register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GPIOAEN</name>
|
|
<description>IO port A clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOBEN</name>
|
|
<description>IO port B clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOCEN</name>
|
|
<description>IO port C clock enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIODEN</name>
|
|
<description>IO port D clock enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOEEN</name>
|
|
<description>IO port E clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOFEN</name>
|
|
<description>IO port F clock enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOGEN</name>
|
|
<description>IO port G clock enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC12EN</name>
|
|
<description>ADC clock enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC345EN</name>
|
|
<description>DCMI clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC1</name>
|
|
<description>AES accelerator clock enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC2</name>
|
|
<description>HASH clock enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC3</name>
|
|
<description>Random Number Generator clock enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC4</name>
|
|
<description>DAC4 clock enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRYPTEN</name>
|
|
<description>Cryptography clock enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RNGEN</name>
|
|
<description>Random Number Generator clock enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB3ENR</name>
|
|
<displayName>AHB3ENR</displayName>
|
|
<description>AHB3 peripheral clock enable register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FMCEN</name>
|
|
<description>Flexible memory controller clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QUADSPI1EN</name>
|
|
<description>Quad SPI 1 module clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1ENR1</name>
|
|
<displayName>APB1ENR1</displayName>
|
|
<description>APB1ENR1</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIM2EN</name>
|
|
<description>TIM2 timer clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM3EN</name>
|
|
<description>TIM3 timer clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM4EN</name>
|
|
<description>TIM4 timer clock enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM5EN</name>
|
|
<description>TIM5 timer clock enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM6EN</name>
|
|
<description>TIM6 timer clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM7EN</name>
|
|
<description>TIM7 timer clock enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRSEN</name>
|
|
<description>CRSclock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCAPBEN</name>
|
|
<description>RTC APB clock enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGEN</name>
|
|
<description>Window watchdog clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2EN</name>
|
|
<description>SPI2 clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SP3EN</name>
|
|
<description>SPI3 clock enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2EN</name>
|
|
<description>USART2 clock enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART3EN</name>
|
|
<description>USART3 clock enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART4EN</name>
|
|
<description>UART4 clock enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART5EN</name>
|
|
<description>UART5 clock enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1EN</name>
|
|
<description>I2C1 clock enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2EN</name>
|
|
<description>I2C2 clock enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBDEN</name>
|
|
<description>USBDclock enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FDCANEN</name>
|
|
<description>FDCAN clock enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWREN</name>
|
|
<description>Power interface clock enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C3</name>
|
|
<description>OPAMP interface clock enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPTIM1EN</name>
|
|
<description>Low power timer 1 clock enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1ENR2</name>
|
|
<displayName>APB1ENR2</displayName>
|
|
<description>APB1 peripheral clock enable register 2</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPUART1EN</name>
|
|
<description>Low power UART 1 clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C4EN</name>
|
|
<description>I2C4 clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBPDEN</name>
|
|
<description>USBPD clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB2ENR</name>
|
|
<displayName>APB2ENR</displayName>
|
|
<description>APB2ENR</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCFGEN</name>
|
|
<description>SYSCFG clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM1EN</name>
|
|
<description>TIM1 timer clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1EN</name>
|
|
<description>SPI1 clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM8EN</name>
|
|
<description>TIM8 timer clock enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1EN</name>
|
|
<description>USART1clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI4EN</name>
|
|
<description>SPI 4 clock enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM15EN</name>
|
|
<description>TIM15 timer clock enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM16EN</name>
|
|
<description>TIM16 timer clock enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM17EN</name>
|
|
<description>TIM17 timer clock enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM20EN</name>
|
|
<description>Timer 20 clock enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAI1EN</name>
|
|
<description>SAI1 clock enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRTIMEREN</name>
|
|
<description>HRTIMER clock enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB1SMENR</name>
|
|
<displayName>AHB1SMENR</displayName>
|
|
<description>AHB1 peripheral clocks enable in Sleep and Stop modes register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000130F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMA1SMEN</name>
|
|
<description>DMA1 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMA2SMEN</name>
|
|
<description>DMA2 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAMUX1SMEN</name>
|
|
<description>DMAMUX clock enable during Sleep and Stop modes</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CORDICSMEN</name>
|
|
<description>CORDIC clock enable during sleep mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLASHSMEN</name>
|
|
<description>Flash memory interface clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM1SMEN</name>
|
|
<description>SRAM1 interface clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCSMEN</name>
|
|
<description>CRCSMEN</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMACSMEN</name>
|
|
<description>FMACSM clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB2SMENR</name>
|
|
<displayName>AHB2SMENR</displayName>
|
|
<description>AHB2 peripheral clocks enable in Sleep and Stop modes register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x050F667F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GPIOASMEN</name>
|
|
<description>IO port A clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOBSMEN</name>
|
|
<description>IO port B clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOCSMEN</name>
|
|
<description>IO port C clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIODSMEN</name>
|
|
<description>IO port D clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOESMEN</name>
|
|
<description>IO port E clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOFSMEN</name>
|
|
<description>IO port F clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOGSMEN</name>
|
|
<description>IO port G clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM2SMEN</name>
|
|
<description>SRAM2 interface clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM3SMEN</name>
|
|
<description>SRAM2 interface clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD12CSMEN</name>
|
|
<description>ADC clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC345SMEN</name>
|
|
<description>DCMI clock enable during Sleep and Stop modes</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC1SMEN</name>
|
|
<description>AES accelerator clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC2SMEN</name>
|
|
<description>HASH clock enable during Sleep and Stop modes</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC3SMEN</name>
|
|
<description>DAC3 clock enable during sleep mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DAC4SMEN</name>
|
|
<description>DAC4 clock enable during sleep mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRYPTSMEN</name>
|
|
<description>Cryptography clock enable during sleep mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RNGSMEN</name>
|
|
<description>Random Number Generator clock enable during sleep mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHB3SMENR</name>
|
|
<displayName>AHB3SMENR</displayName>
|
|
<description>AHB3 peripheral clocks enable in Sleep and Stop modes register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000101</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FMCSMEN</name>
|
|
<description>Flexible memory controller clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QUADSPI1SMEN</name>
|
|
<description>QUAD SPI 1 module clock enable during sleep mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1SMENR1</name>
|
|
<displayName>APB1SMENR1</displayName>
|
|
<description>APB1SMENR1</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xD2FECD3F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIM2SMEN</name>
|
|
<description>TIM2 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM3SMEN</name>
|
|
<description>TIM3 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM4SMEN</name>
|
|
<description>TIM4 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM5SMEN</name>
|
|
<description>TIM5 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM6SMEN</name>
|
|
<description>TIM6 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM7SMEN</name>
|
|
<description>TIM7 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRSSMEN</name>
|
|
<description>CRS clock enable during sleep mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCAPBSMEN</name>
|
|
<description>RTC APB clock enable during Sleep and Stop modes</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGSMEN</name>
|
|
<description>Window watchdog clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2SMEN</name>
|
|
<description>SPI2 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SP3SMEN</name>
|
|
<description>SPI3 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2SMEN</name>
|
|
<description>USART2 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART3SMEN</name>
|
|
<description>USART3 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART4SMEN</name>
|
|
<description>UART4 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART5SMEN</name>
|
|
<description>UART5 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1SMEN</name>
|
|
<description>I2C1 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2SMEN</name>
|
|
<description>I2C2 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C3SMEN</name>
|
|
<description>I2C3 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FDCANSMEN</name>
|
|
<description>FDCAN clock enable during sleep mode</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRSMEN</name>
|
|
<description>Power interface clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C3SMEN_3</name>
|
|
<description>I2C 3 interface clock enable during sleep mode</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPTIM1SMEN</name>
|
|
<description>Low Power Timer1 clock enable during sleep mode</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB1SMENR2</name>
|
|
<displayName>APB1SMENR2</displayName>
|
|
<description>APB1 peripheral clocks enable in Sleep and Stop modes register 2</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000103</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPUART1SMEN</name>
|
|
<description>Low power UART 1 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C4SMEN</name>
|
|
<description>I2C4 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBPDSMEN</name>
|
|
<description>USB PD clock enable during sleep mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB2SMENR</name>
|
|
<displayName>APB2SMENR</displayName>
|
|
<description>APB2SMENR</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0437F801</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCFGSMEN</name>
|
|
<description>SYSCFG clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM1SMEN</name>
|
|
<description>TIM1 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1SMEN</name>
|
|
<description>SPI1 clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM8SMEN</name>
|
|
<description>TIM8 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1SMEN</name>
|
|
<description>USART1clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI4SMEN</name>
|
|
<description>SPI4 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM15SMEN</name>
|
|
<description>TIM15 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM16SMEN</name>
|
|
<description>TIM16 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM17SMEN</name>
|
|
<description>TIM17 timer clocks enable during Sleep and Stop modes</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM20SMEN</name>
|
|
<description>Timer 20clock enable during sleep mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAI1SMEN</name>
|
|
<description>SAI1 clock enable during sleep mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRTIMERSMEN</name>
|
|
<description>HRTIMER clock enable during sleep mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCIPR1</name>
|
|
<displayName>CCIPR1</displayName>
|
|
<description>CCIPR</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADC345SEL</name>
|
|
<description>ADC3/4/5 clock source selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADCSEL</name>
|
|
<description>ADCs clock source selection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLK48SEL</name>
|
|
<description>48 MHz clock source selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FDCANSEL</name>
|
|
<description>SAI2 clock source selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPISEL_</name>
|
|
<description>SAI1 clock source selection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAISEL</name>
|
|
<description>Low power timer 2 clock source selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPTIM1SEL</name>
|
|
<description>Low power timer 1 clock source selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C3SEL</name>
|
|
<description>I2C3 clock source selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2SEL</name>
|
|
<description>I2C2 clock source selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1SEL</name>
|
|
<description>I2C1 clock source selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPUART1SEL</name>
|
|
<description>LPUART1 clock source selection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART5SEL</name>
|
|
<description>UART5 clock source selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UART4SEL</name>
|
|
<description>UART4 clock source selection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART3SEL</name>
|
|
<description>USART3 clock source selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2SEL</name>
|
|
<description>USART2 clock source selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1SEL</name>
|
|
<description>USART1 clock source selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDCR</name>
|
|
<displayName>BDCR</displayName>
|
|
<description>BDCR</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSCOSEL</name>
|
|
<description>Low speed clock output selection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSCCOEN</name>
|
|
<description>Low speed clock output enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VSWRST</name>
|
|
<description>Vswitch domain software reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCEN</name>
|
|
<description>RTC clock enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTCSEL</name>
|
|
<description>RTC clock source selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSD</name>
|
|
<description>LSECSSD</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSON</name>
|
|
<description>LSECSSON</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSEDRV</name>
|
|
<description>SE oscillator drive capability</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSEBYP</name>
|
|
<description>LSE oscillator bypass</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSERDY</name>
|
|
<description>LSE oscillator ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LSEON</name>
|
|
<description>LSE oscillator enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>CSR</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0C000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPWRSTF</name>
|
|
<description>Low-power reset flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WWDGRSTF</name>
|
|
<description>Window watchdog reset flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WDGRSTF</name>
|
|
<description>Independent window watchdog reset flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SFTRSTF</name>
|
|
<description>Software reset flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BORRSTF</name>
|
|
<description>BOR flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PADRSTF</name>
|
|
<description>Pad reset flag</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OBLRSTF</name>
|
|
<description>Option byte loader reset flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RMVF</name>
|
|
<description>Remove reset flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDY</name>
|
|
<description>LSI oscillator ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LSION</name>
|
|
<description>LSI oscillator enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRRCR</name>
|
|
<displayName>CRRCR</displayName>
|
|
<description>Clock recovery RC register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RC48ON</name>
|
|
<description>HSI48 clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RC48RDY</name>
|
|
<description>HSI48 clock ready flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RC48CAL</name>
|
|
<description>HSI48 clock calibration</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCIPR2</name>
|
|
<displayName>CCIPR2</displayName>
|
|
<description>Peripherals independent clock configuration register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2C4SEL</name>
|
|
<description>I2C4 clock source selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>QUADSPISEL</name>
|
|
<description>Octospi clock source selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWR</name>
|
|
<description>Power control</description>
|
|
<groupName>PWR</groupName>
|
|
<baseAddress>0x40007000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Power control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000200</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPR</name>
|
|
<description>Low-power run</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VOS</name>
|
|
<description>Voltage scaling range selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBP</name>
|
|
<description>Disable backup domain write protection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPMS</name>
|
|
<description>Low-power mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Power control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PVMEN1</name>
|
|
<description>Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLS</name>
|
|
<description>Power voltage detector level selection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVDE</name>
|
|
<description>Power voltage detector enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVMEN2</name>
|
|
<description>Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVMEN3</name>
|
|
<description>Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVMEN4</name>
|
|
<description>Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR3</name>
|
|
<displayName>CR3</displayName>
|
|
<description>Power control register 3</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00008000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EWUP1</name>
|
|
<description>Enable Wakeup pin WKUP1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EWUP2</name>
|
|
<description>Enable Wakeup pin WKUP2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EWUP3</name>
|
|
<description>Enable Wakeup pin WKUP3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EWUP4</name>
|
|
<description>Enable Wakeup pin WKUP4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EWUP5</name>
|
|
<description>Enable Wakeup pin WKUP5</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RRS</name>
|
|
<description>SRAM2 retention in Standby mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>APC</name>
|
|
<description>Apply pull-up and pull-down configuration</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UCPD1_STDBY</name>
|
|
<description>STDBY</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UCPD1_DBDIS</name>
|
|
<description>DBDIS</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIWUL</name>
|
|
<description>Enable external WakeUp line</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR4</name>
|
|
<displayName>CR4</displayName>
|
|
<description>Power control register 4</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VBRS</name>
|
|
<description>VBAT battery charging resistor selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBE</name>
|
|
<description>VBAT battery charging enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP5</name>
|
|
<description>Wakeup pin WKUP5 polarity</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP4</name>
|
|
<description>Wakeup pin WKUP4 polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP3</name>
|
|
<description>Wakeup pin WKUP3 polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP2</name>
|
|
<description>Wakeup pin WKUP2 polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WP1</name>
|
|
<description>Wakeup pin WKUP1 polarity</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR1</name>
|
|
<displayName>SR1</displayName>
|
|
<description>Power status register 1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WUFI</name>
|
|
<description>Wakeup flag internal</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBF</name>
|
|
<description>Standby flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF5</name>
|
|
<description>Wakeup flag 5</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF4</name>
|
|
<description>Wakeup flag 4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF3</name>
|
|
<description>Wakeup flag 3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF2</name>
|
|
<description>Wakeup flag 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF1</name>
|
|
<description>Wakeup flag 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR2</name>
|
|
<displayName>SR2</displayName>
|
|
<description>Power status register 2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PVMO4</name>
|
|
<description>Peripheral voltage monitoring output: VDDA vs. 2.2 V</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVMO3</name>
|
|
<description>Peripheral voltage monitoring output: VDDA vs. 1.62 V</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVMO2</name>
|
|
<description>Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVMO1</name>
|
|
<description>Peripheral voltage monitoring output: VDDUSB vs. 1.2 V</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVDO</name>
|
|
<description>Power voltage detector output</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VOSF</name>
|
|
<description>Voltage scaling flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REGLPF</name>
|
|
<description>Low-power regulator flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REGLPS</name>
|
|
<description>Low-power regulator started</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<displayName>SCR</displayName>
|
|
<description>Power status clear register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSBF</name>
|
|
<description>Clear standby flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWUF5</name>
|
|
<description>Clear wakeup flag 5</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWUF4</name>
|
|
<description>Clear wakeup flag 4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWUF3</name>
|
|
<description>Clear wakeup flag 3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWUF2</name>
|
|
<description>Clear wakeup flag 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWUF1</name>
|
|
<description>Clear wakeup flag 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUCRA</name>
|
|
<displayName>PUCRA</displayName>
|
|
<description>Power Port A pull-up control register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PU15</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU13</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU12</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU11</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU10</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU9</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU8</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU7</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU6</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU5</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU4</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU3</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU2</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU1</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU0</name>
|
|
<description>Port A pull-up bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDCRA</name>
|
|
<displayName>PDCRA</displayName>
|
|
<description>Power Port A pull-down control register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD14</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD12</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD11</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD4</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Port A pull-down bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUCRB</name>
|
|
<displayName>PUCRB</displayName>
|
|
<description>Power Port B pull-up control register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PU15</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU14</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU13</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU12</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU11</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU10</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU9</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU8</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU7</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU6</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU5</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU4</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU3</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU2</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU1</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU0</name>
|
|
<description>Port B pull-up bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDCRB</name>
|
|
<displayName>PDCRB</displayName>
|
|
<description>Power Port B pull-down control register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD15</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD14</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD13</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD12</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD11</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Port B pull-down bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUCRC</name>
|
|
<displayName>PUCRC</displayName>
|
|
<description>Power Port C pull-up control register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PU15</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU14</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU13</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU12</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU11</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU10</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU9</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU8</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU7</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU6</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU5</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU4</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU3</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU2</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU1</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU0</name>
|
|
<description>Port C pull-up bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDCRC</name>
|
|
<displayName>PDCRC</displayName>
|
|
<description>Power Port C pull-down control register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD15</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD14</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD13</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD12</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD11</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD4</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Port C pull-down bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUCRD</name>
|
|
<displayName>PUCRD</displayName>
|
|
<description>Power Port D pull-up control register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PU15</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU14</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU13</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU12</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU11</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU10</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU9</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU8</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU7</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU6</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU5</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU4</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU3</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU2</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU1</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU0</name>
|
|
<description>Port D pull-up bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDCRD</name>
|
|
<displayName>PDCRD</displayName>
|
|
<description>Power Port D pull-down control register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD15</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD14</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD13</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD12</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD11</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD4</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Port D pull-down bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUCRE</name>
|
|
<displayName>PUCRE</displayName>
|
|
<description>Power Port E pull-up control register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PU15</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU14</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU13</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU12</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU11</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU10</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU9</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU8</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU7</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU6</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU5</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU4</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU3</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU2</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU1</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU0</name>
|
|
<description>Port E pull-up bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDCRE</name>
|
|
<displayName>PDCRE</displayName>
|
|
<description>Power Port E pull-down control register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD15</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD14</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD13</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD12</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD11</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD4</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Port E pull-down bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUCRF</name>
|
|
<displayName>PUCRF</displayName>
|
|
<description>Power Port F pull-up control register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PU15</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU14</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU13</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU12</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU11</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU10</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU9</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU8</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU7</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU6</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU5</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU4</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU3</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU2</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU1</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU0</name>
|
|
<description>Port F pull-up bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDCRF</name>
|
|
<displayName>PDCRF</displayName>
|
|
<description>Power Port F pull-down control register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD15</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD14</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD13</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD12</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD11</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD4</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Port F pull-down bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUCRG</name>
|
|
<displayName>PUCRG</displayName>
|
|
<description>Power Port G pull-up control register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PU10</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU9</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU8</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU7</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU6</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU5</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU4</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU3</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU2</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU1</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PU0</name>
|
|
<description>Port G pull-up bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDCRG</name>
|
|
<displayName>PDCRG</displayName>
|
|
<description>Power Port G pull-down control register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PD10</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD9</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD8</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD7</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD6</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD5</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD4</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD3</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD2</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD1</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PD0</name>
|
|
<description>Port G pull-down bit y (y=0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR5</name>
|
|
<displayName>CR5</displayName>
|
|
<description>Power control register 5</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>R1MODE</name>
|
|
<description>Main regular range 1 mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RNG</name>
|
|
<description>Random number generator</description>
|
|
<groupName>RNG</groupName>
|
|
<baseAddress>0x50060800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RNG</name>
|
|
<description>RNG</description>
|
|
<value>90</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CED</name>
|
|
<description>Clock error detection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RNGEN</name>
|
|
<description>Random number generator enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEIS</name>
|
|
<description>Seed error interrupt status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CEIS</name>
|
|
<description>Clock error interrupt status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SECS</name>
|
|
<description>Seed error current status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CECS</name>
|
|
<description>Clock error current status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DRDY</name>
|
|
<description>Data ready</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>data register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RNDATA</name>
|
|
<description>Random data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x48000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODER</name>
|
|
<displayName>MODER</displayName>
|
|
<description>GPIO port mode register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xABFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODER15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTYPER</name>
|
|
<displayName>OTYPER</displayName>
|
|
<description>GPIO port output type register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OT15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPEEDR</name>
|
|
<displayName>OSPEEDR</displayName>
|
|
<description>GPIO port output speed register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0C000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPEEDR15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUPDR</name>
|
|
<displayName>PUPDR</displayName>
|
|
<description>GPIO port pull-up/pull-down register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x64000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUPDR15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>GPIO port input data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDR15</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR14</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR13</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR12</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR11</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR10</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR9</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR8</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR7</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR6</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR5</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR4</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR3</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR2</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR1</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR0</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<displayName>ODR</displayName>
|
|
<description>GPIO port output data register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ODR15</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR14</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR13</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR12</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR11</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR10</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR9</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR8</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR7</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR6</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR5</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR4</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR3</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR2</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR1</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR0</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSRR</name>
|
|
<displayName>BSRR</displayName>
|
|
<description>GPIO port bit set/reset register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS15</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS14</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS13</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS12</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS11</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS10</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS9</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS8</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS7</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS6</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS5</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS4</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS3</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS0</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKR</name>
|
|
<displayName>LCKR</displayName>
|
|
<description>GPIO port configuration lock register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCKK</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK15</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK14</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK13</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK12</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK11</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK10</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK9</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK8</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK7</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK6</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK5</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK4</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK3</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK2</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK1</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK0</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRL</name>
|
|
<displayName>AFRL</displayName>
|
|
<description>GPIO alternate function low register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFRL7</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL6</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL5</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL4</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL3</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL2</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL1</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL0</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRH</name>
|
|
<displayName>AFRH</displayName>
|
|
<description>GPIO alternate function high register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFRH15</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH14</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH13</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH12</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH11</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH10</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH9</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH8</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>GPIO port bit reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOB</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x48000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODER</name>
|
|
<displayName>MODER</displayName>
|
|
<description>GPIO port mode register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFEBF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODER15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTYPER</name>
|
|
<displayName>OTYPER</displayName>
|
|
<description>GPIO port output type register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OT15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPEEDR</name>
|
|
<displayName>OSPEEDR</displayName>
|
|
<description>GPIO port output speed register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPEEDR15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUPDR</name>
|
|
<displayName>PUPDR</displayName>
|
|
<description>GPIO port pull-up/pull-down register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUPDR15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>GPIO port input data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDR15</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR14</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR13</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR12</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR11</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR10</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR9</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR8</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR7</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR6</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR5</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR4</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR3</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR2</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR1</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR0</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<displayName>ODR</displayName>
|
|
<description>GPIO port output data register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ODR15</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR14</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR13</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR12</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR11</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR10</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR9</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR8</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR7</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR6</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR5</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR4</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR3</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR2</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR1</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR0</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSRR</name>
|
|
<displayName>BSRR</displayName>
|
|
<description>GPIO port bit set/reset register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS15</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS14</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS13</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS12</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS11</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS10</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS9</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS8</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS7</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS6</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS5</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS4</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS3</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS0</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKR</name>
|
|
<displayName>LCKR</displayName>
|
|
<description>GPIO port configuration lock register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCKK</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK15</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK14</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK13</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK12</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK11</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK10</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK9</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK8</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK7</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK6</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK5</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK4</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK3</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK2</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK1</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK0</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRL</name>
|
|
<displayName>AFRL</displayName>
|
|
<description>GPIO alternate function low register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFRL7</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL6</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL5</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL4</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL3</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL2</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL1</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL0</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRH</name>
|
|
<displayName>AFRH</displayName>
|
|
<description>GPIO alternate function high register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFRH15</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH14</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH13</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH12</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH11</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH10</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH9</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH8</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>GPIO port bit reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOC</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x48000800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODER</name>
|
|
<displayName>MODER</displayName>
|
|
<description>GPIO port mode register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODER15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODER0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTYPER</name>
|
|
<displayName>OTYPER</displayName>
|
|
<description>GPIO port output type register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OT15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPEEDR</name>
|
|
<displayName>OSPEEDR</displayName>
|
|
<description>GPIO port output speed register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPEEDR15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEEDR0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUPDR</name>
|
|
<displayName>PUPDR</displayName>
|
|
<description>GPIO port pull-up/pull-down register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUPDR15</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR14</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR13</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR12</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR11</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR10</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR9</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR8</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR7</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR6</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR5</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR4</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR3</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR2</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR1</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPDR0</name>
|
|
<description>Port x configuration bits (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>GPIO port input data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDR15</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR14</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR13</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR12</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR11</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR10</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR9</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR8</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR7</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR6</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR5</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR4</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR3</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR2</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR1</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDR0</name>
|
|
<description>Port input data (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<displayName>ODR</displayName>
|
|
<description>GPIO port output data register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ODR15</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR14</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR13</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR12</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR11</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR10</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR9</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR8</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR7</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR6</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR5</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR4</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR3</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR2</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR1</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODR0</name>
|
|
<description>Port output data (y = 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSRR</name>
|
|
<displayName>BSRR</displayName>
|
|
<description>GPIO port bit set/reset register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port x reset bit y (y = 0..15)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS15</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS14</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS13</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS12</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS11</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS10</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS9</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS8</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS7</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS6</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS5</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS4</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS3</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS0</name>
|
|
<description>Port x set bit y (y= 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKR</name>
|
|
<displayName>LCKR</displayName>
|
|
<description>GPIO port configuration lock register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCKK</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK15</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK14</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK13</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK12</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK11</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK10</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK9</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK8</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK7</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK6</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK5</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK4</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK3</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK2</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK1</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK0</name>
|
|
<description>Port x lock bit y (y= 0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRL</name>
|
|
<displayName>AFRL</displayName>
|
|
<description>GPIO alternate function low register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFRL7</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL6</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL5</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL4</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL3</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL2</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL1</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRL0</name>
|
|
<description>Alternate function selection for port x bit y (y = 0..7)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRH</name>
|
|
<displayName>AFRH</displayName>
|
|
<description>GPIO alternate function high register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFRH15</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH14</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH13</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH12</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH11</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH10</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH9</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFRH8</name>
|
|
<description>Alternate function selection for port x bit y (y = 8..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>GPIO port bit reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOD</name>
|
|
<baseAddress>0x48000C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOE</name>
|
|
<baseAddress>0x48001000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOF</name>
|
|
<baseAddress>0x48001400</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOC">
|
|
<name>GPIOG</name>
|
|
<baseAddress>0x48001800</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM15</name>
|
|
<description>General purpose timers</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>Update request source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>One-pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>Auto-reload preload enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIFREMAP</name>
|
|
<description>UIF status bit remapping</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>Dithering Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OIS2</name>
|
|
<description>Output idle state 2 (OC2 output)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS1N</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS1</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>TI1 selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>Master mode selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>Capture/compare DMA selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCUS</name>
|
|
<description>Capture/compare control update selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCPC</name>
|
|
<description>Capture/compare preloaded control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<displayName>SMCR</displayName>
|
|
<description>slave mode control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS_4_3</name>
|
|
<description>Trigger selection - bit 4:3</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMS_3</name>
|
|
<description>Slave mode selection - bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>Master/Slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>Slave mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<displayName>DIER</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>Trigger DMA request enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMDE</name>
|
|
<description>COM DMA request enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>Capture/Compare 2 DMA request enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>Capture/Compare 1 DMA request enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIE</name>
|
|
<description>Break interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Trigger interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIE</name>
|
|
<description>COM interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>Capture/Compare 2 interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>Capture/Compare 1 interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>Capture/Compare 2 overcapture flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>Capture/Compare 1 overcapture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>Break interrupt flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Trigger interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>COM interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>Capture/compare 2 interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>Capture/compare 1 interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<displayName>EGR</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BG</name>
|
|
<description>Break generation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>Trigger generation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMG</name>
|
|
<description>Capture/Compare control update generation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>Capture/compare 2 generation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/compare 1 generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Output</name>
|
|
<displayName>CCMR1_Output</displayName>
|
|
<description>capture/compare mode register (output mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC2M_3</name>
|
|
<description>Output Compare 2 mode - bit 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1M_3</name>
|
|
<description>Output Compare 1 mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>OC2M</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>OC2PE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>OC2FE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>CC2S</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>OC1CE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>Output Compare 1 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>Output Compare 1 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>Output Compare 1 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Input</name>
|
|
<displayName>CCMR1_Input</displayName>
|
|
<description>capture/compare mode register 1 (input mode)</description>
|
|
<alternateRegister>CCMR1_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>IC2F</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>IC2PSC</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>CC2S</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>Input capture 1 filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>Input capture 1 prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<displayName>CCER</displayName>
|
|
<description>capture/compare enable register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC2NP</name>
|
|
<description>Capture/Compare 2 complementary output polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>Capture/Compare 2 output polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>Capture/Compare 2 output enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1NP</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1NE</name>
|
|
<description>Capture/Compare 1 complementary output enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>Capture/Compare 1 output enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>counter</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UIFCPY</name>
|
|
<description>UIF Copy</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>prescaler</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>auto-reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auto-reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<displayName>RCR</displayName>
|
|
<description>repetition counter register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<displayName>CCR1</displayName>
|
|
<description>capture/compare register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>Capture/Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<displayName>CCR2</displayName>
|
|
<description>capture/compare register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>Capture/Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<displayName>BDTR</displayName>
|
|
<description>break and dead-time register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>Dead-time generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>Off-state selection for Idle mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>Off-state selection for Run mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>Break enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>Break polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>Automatic output enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>Main output enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKF</name>
|
|
<description>Break filter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKDSRM</name>
|
|
<description>BKDSRM</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKBID</name>
|
|
<description>BKBID</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTR2</name>
|
|
<displayName>DTR2</displayName>
|
|
<description>timer Deadtime Register 2</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGF</name>
|
|
<description>Dead-time generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTAE</name>
|
|
<description>Deadtime Asymmetric Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPE</name>
|
|
<description>Deadtime Preload Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TISEL</name>
|
|
<displayName>TISEL</displayName>
|
|
<description>TIM timer input selection register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TI1SEL</name>
|
|
<description>TI1[0] to TI1[15] input selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI2SEL</name>
|
|
<description>TI2[0] to TI2[15] input selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF1</name>
|
|
<displayName>AF1</displayName>
|
|
<description>TIM alternate function option register 1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKCMP4P</name>
|
|
<description>BRK COMP4 input polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3P</name>
|
|
<description>BRK COMP3 input polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2P</name>
|
|
<description>BRK COMP2 input polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1P</name>
|
|
<description>BRK COMP1 input polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINP</name>
|
|
<description>BRK BKIN input polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP7E</name>
|
|
<description>BRK COMP7 enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP6E</name>
|
|
<description>BRK COMP6 enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP5E</name>
|
|
<description>BRK COMP5 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP4E</name>
|
|
<description>BRK COMP4 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3E</name>
|
|
<description>BRK COMP3 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2E</name>
|
|
<description>BRK COMP2 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1E</name>
|
|
<description>BRK COMP1 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINE</name>
|
|
<description>BRK BKIN input enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF2</name>
|
|
<displayName>AF2</displayName>
|
|
<description>TIM alternate function option register 2</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCRSEL</name>
|
|
<description>OCREF_CLR source selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<displayName>DCR</displayName>
|
|
<description>DMA control register</description>
|
|
<addressOffset>0x3DC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>DMA burst length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>DMA base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<displayName>DMAR</displayName>
|
|
<description>DMA address for full transfer</description>
|
|
<addressOffset>0x3E0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>DMA register for burst accesses</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM16</name>
|
|
<description>General purpose timers</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40014400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>Update request source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>One-pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>Auto-reload preload enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIFREMAP</name>
|
|
<description>UIF status bit remapping</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>Dithering Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OIS1N</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS1</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>Capture/compare DMA selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCUS</name>
|
|
<description>Capture/compare control update selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCPC</name>
|
|
<description>Capture/compare preloaded control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<displayName>DIER</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMDE</name>
|
|
<description>COM DMA request enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>Capture/Compare 1 DMA request enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIE</name>
|
|
<description>Break interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIE</name>
|
|
<description>COM interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>Capture/Compare 1 interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>Capture/Compare 1 overcapture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>Break interrupt flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>COM interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>Capture/compare 1 interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<displayName>EGR</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BG</name>
|
|
<description>Break generation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMG</name>
|
|
<description>Capture/Compare control update generation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/compare 1 generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Output</name>
|
|
<displayName>CCMR1_Output</displayName>
|
|
<description>capture/compare mode register (output mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC1M_3</name>
|
|
<description>Output Compare 1 mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>Output Compare 1 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>Output Compare 1 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>Output Compare 1 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Input</name>
|
|
<displayName>CCMR1_Input</displayName>
|
|
<description>capture/compare mode register 1 (input mode)</description>
|
|
<alternateRegister>CCMR1_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>Input capture 1 filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>Input capture 1 prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<displayName>CCER</displayName>
|
|
<description>capture/compare enable register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC1NP</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1NE</name>
|
|
<description>Capture/Compare 1 complementary output enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>Capture/Compare 1 output enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>counter</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UIFCPY</name>
|
|
<description>UIF Copy</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>prescaler</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>auto-reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auto-reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<displayName>RCR</displayName>
|
|
<description>repetition counter register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<displayName>CCR1</displayName>
|
|
<description>capture/compare register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>Capture/Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<displayName>BDTR</displayName>
|
|
<description>break and dead-time register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>Dead-time generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>Off-state selection for Idle mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>Off-state selection for Run mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>Break enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>Break polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>Automatic output enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>Main output enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKF</name>
|
|
<description>Break filter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKDSRM</name>
|
|
<description>BKDSRM</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKBID</name>
|
|
<description>BKBID</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTR2</name>
|
|
<displayName>DTR2</displayName>
|
|
<description>timer Deadtime Register 2</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTGF</name>
|
|
<description>Dead-time generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTAE</name>
|
|
<description>Deadtime Asymmetric Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPE</name>
|
|
<description>Deadtime Preload Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TISEL</name>
|
|
<displayName>TISEL</displayName>
|
|
<description>TIM timer input selection register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TI1SEL</name>
|
|
<description>TI1[0] to TI1[15] input selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF1</name>
|
|
<displayName>AF1</displayName>
|
|
<description>TIM alternate function option register 1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKCMP4P</name>
|
|
<description>BRK COMP4 input polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3P</name>
|
|
<description>BRK COMP3 input polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2P</name>
|
|
<description>BRK COMP2 input polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1P</name>
|
|
<description>BRK COMP1 input polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINP</name>
|
|
<description>BRK BKIN input polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP7E</name>
|
|
<description>BRK COMP7 enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP6E</name>
|
|
<description>BRK COMP6 enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP5E</name>
|
|
<description>BRK COMP5 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP4E</name>
|
|
<description>BRK COMP4 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3E</name>
|
|
<description>BRK COMP3 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2E</name>
|
|
<description>BRK COMP2 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1E</name>
|
|
<description>BRK COMP1 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINE</name>
|
|
<description>BRK BKIN input enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF2</name>
|
|
<displayName>AF2</displayName>
|
|
<description>TIM alternate function option register 2</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCRSEL</name>
|
|
<description>OCREF_CLR source selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OR1</name>
|
|
<displayName>OR1</displayName>
|
|
<description>TIM option register 1</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSE32EN</name>
|
|
<description>HSE Divided by 32 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<displayName>DCR</displayName>
|
|
<description>DMA control register</description>
|
|
<addressOffset>0x3DC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>DMA burst length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>DMA base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<displayName>DMAR</displayName>
|
|
<description>DMA address for full transfer</description>
|
|
<addressOffset>0x3E0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>DMA register for burst accesses</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM16">
|
|
<name>TIM17</name>
|
|
<baseAddress>0x40014800</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM1</name>
|
|
<description>Advanced-timers</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40012C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM1_BRK_TIM15</name>
|
|
<description>TIM1_BRK_TIM15</description>
|
|
<value>24</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM1_UP_TIM16</name>
|
|
<description>TIM1_UP_TIM16</description>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM1_TRG_COM</name>
|
|
<description>TIM1_TRG_COM/</description>
|
|
<value>26</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM1_CC</name>
|
|
<description>TIM1 capture compare interrupt</description>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM8_CC</name>
|
|
<description>TIM8_CC</description>
|
|
<value>46</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>Dithering Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIFREMAP</name>
|
|
<description>UIF status bit remapping</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>Auto-reload preload enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>Center-aligned mode selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>One-pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>Update request source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MMS_3</name>
|
|
<description>Master mode selection - bit 3</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMS2</name>
|
|
<description>Master mode selection 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS6</name>
|
|
<description>Output Idle state 6 (OC6 output)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS5</name>
|
|
<description>Output Idle state 5 (OC5 output)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS4N</name>
|
|
<description>Output Idle state 4 (OC4N output)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS4</name>
|
|
<description>Output Idle state 4</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS3N</name>
|
|
<description>Output Idle state 3</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS3</name>
|
|
<description>Output Idle state 3</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS2N</name>
|
|
<description>Output Idle state 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS2</name>
|
|
<description>Output Idle state 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS1N</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS1</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>TI1 selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>Master mode selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>Capture/compare DMA selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCUS</name>
|
|
<description>Capture/compare control update selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCPC</name>
|
|
<description>Capture/compare preloaded control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<displayName>SMCR</displayName>
|
|
<description>slave mode control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMSPS</name>
|
|
<description>SMS Preload Source</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMSPE</name>
|
|
<description>SMS Preload Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TS_4_3</name>
|
|
<description>Trigger selection - bit 4:3</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMS_3</name>
|
|
<description>Slave mode selection - bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>External trigger polarity</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECE</name>
|
|
<description>External clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETPS</name>
|
|
<description>External trigger prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETF</name>
|
|
<description>External trigger filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>Master/Slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCCS</name>
|
|
<description>OCREF clear selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>Slave mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<displayName>DIER</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERRIE</name>
|
|
<description>Transition Error interrupt enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IERRIE</name>
|
|
<description>Index Error interrupt enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIRIE</name>
|
|
<description>Direction Change interrupt enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDXIE</name>
|
|
<description>Index interrupt enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>Trigger DMA request enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMDE</name>
|
|
<description>COM DMA request enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>Capture/Compare 4 DMA request enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>Capture/Compare 3 DMA request enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>Capture/Compare 2 DMA request enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>Capture/Compare 1 DMA request enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Trigger interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>Capture/Compare 4 interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>Capture/Compare 3 interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>Capture/Compare 2 interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>Capture/Compare 1 interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIE</name>
|
|
<description>Break interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIE</name>
|
|
<description>COM interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERRF</name>
|
|
<description>Transition Error interrupt flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IERRF</name>
|
|
<description>Index Error interrupt flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIRF</name>
|
|
<description>Direction Change interrupt flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDXF</name>
|
|
<description>Index interrupt flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC6IF</name>
|
|
<description>Compare 6 interrupt flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC5IF</name>
|
|
<description>Compare 5 interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBIF</name>
|
|
<description>System Break interrupt flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>Capture/Compare 4 overcapture flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>Capture/Compare 3 overcapture flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>Capture/compare 2 overcapture flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>Capture/Compare 1 overcapture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B2IF</name>
|
|
<description>Break 2 interrupt flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>Break interrupt flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Trigger interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>COM interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>Capture/Compare 4 interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>Capture/Compare 3 interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>Capture/Compare 2 interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>Capture/compare 1 interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<displayName>EGR</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>B2G</name>
|
|
<description>Break 2 generation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BG</name>
|
|
<description>Break generation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>Trigger generation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMG</name>
|
|
<description>Capture/Compare control update generation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>Capture/compare 4 generation</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>Capture/compare 3 generation</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>Capture/compare 2 generation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/compare 1 generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Output</name>
|
|
<displayName>CCMR1_Output</displayName>
|
|
<description>capture/compare mode register 1 (output mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC2M_3</name>
|
|
<description>Output Compare 2 mode - bit 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1M_3</name>
|
|
<description>Output Compare 1 mode - bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>Output Compare 2 clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>Output Compare 2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>Output Compare 2 preload enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>Output Compare 2 fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>Capture/Compare 2 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>Output Compare 1 clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>Output Compare 1 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>Output Compare 1 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>Output Compare 1 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Input</name>
|
|
<displayName>CCMR1_Input</displayName>
|
|
<description>capture/compare mode register 1 (input mode)</description>
|
|
<alternateRegister>CCMR1_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>Input capture 2 filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>Input capture 2 prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>Capture/Compare 2 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>Input capture 1 filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICPCS</name>
|
|
<description>Input capture 1 prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_Output</name>
|
|
<displayName>CCMR2_Output</displayName>
|
|
<description>capture/compare mode register 2 (output mode)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC4M_3</name>
|
|
<description>Output Compare 4 mode - bit 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3M_3</name>
|
|
<description>Output Compare 3 mode - bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4CE</name>
|
|
<description>Output compare 4 clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4M</name>
|
|
<description>Output compare 4 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4PE</name>
|
|
<description>Output compare 4 preload enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4FE</name>
|
|
<description>Output compare 4 fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>Capture/Compare 4 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3CE</name>
|
|
<description>Output compare 3 clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3M</name>
|
|
<description>Output compare 3 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3PE</name>
|
|
<description>Output compare 3 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3FE</name>
|
|
<description>Output compare 3 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>Capture/Compare 3 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_Input</name>
|
|
<displayName>CCMR2_Input</displayName>
|
|
<description>capture/compare mode register 2 (input mode)</description>
|
|
<alternateRegister>CCMR2_Output</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IC4F</name>
|
|
<description>Input capture 4 filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC4PSC</name>
|
|
<description>Input capture 4 prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>Capture/Compare 4 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC3F</name>
|
|
<description>Input capture 3 filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC3PSC</name>
|
|
<description>Input capture 3 prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>Capture/compare 3 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<displayName>CCER</displayName>
|
|
<description>capture/compare enable register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC6P</name>
|
|
<description>Capture/Compare 6 output polarity</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC6E</name>
|
|
<description>Capture/Compare 6 output enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC5P</name>
|
|
<description>Capture/Compare 5 output polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC5E</name>
|
|
<description>Capture/Compare 5 output enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4NP</name>
|
|
<description>Capture/Compare 4 complementary output polarity</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4NE</name>
|
|
<description>Capture/Compare 4 complementary output enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>Capture/Compare 3 output Polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>Capture/Compare 4 output enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3NP</name>
|
|
<description>Capture/Compare 3 output Polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3NE</name>
|
|
<description>Capture/Compare 3 complementary output enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>Capture/Compare 3 output Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>Capture/Compare 3 output enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2NP</name>
|
|
<description>Capture/Compare 2 output Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2NE</name>
|
|
<description>Capture/Compare 2 complementary output enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>Capture/Compare 2 output Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>Capture/Compare 2 output enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1NP</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1NE</name>
|
|
<description>Capture/Compare 1 complementary output enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>Capture/Compare 1 output enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>counter</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UIFCPY</name>
|
|
<description>UIFCPY</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>prescaler</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>auto-reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auto-reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<displayName>RCR</displayName>
|
|
<description>repetition counter register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<displayName>CCR1</displayName>
|
|
<description>capture/compare register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>Capture/Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<displayName>CCR2</displayName>
|
|
<description>capture/compare register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>Capture/Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<displayName>CCR3</displayName>
|
|
<description>capture/compare register 3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR3</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<displayName>CCR4</displayName>
|
|
<description>capture/compare register 4</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR4</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<displayName>BDTR</displayName>
|
|
<description>break and dead-time register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BK2ID</name>
|
|
<description>BK2ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKBID</name>
|
|
<description>BKBID</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2DSRM</name>
|
|
<description>BK2DSRM</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKDSRM</name>
|
|
<description>BKDSRM</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2P</name>
|
|
<description>Break 2 polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2E</name>
|
|
<description>Break 2 Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2F</name>
|
|
<description>Break 2 filter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKF</name>
|
|
<description>Break filter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>Main output enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>Automatic output enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>Break polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>Break enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>Off-state selection for Run mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>Off-state selection for Idle mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>Dead-time generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR5</name>
|
|
<displayName>CCR5</displayName>
|
|
<description>capture/compare register 4</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR5</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GC5C1</name>
|
|
<description>Group Channel 5 and Channel 1</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GC5C2</name>
|
|
<description>Group Channel 5 and Channel 2</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GC5C3</name>
|
|
<description>Group Channel 5 and Channel 3</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR6</name>
|
|
<displayName>CCR6</displayName>
|
|
<description>capture/compare register 4</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR6</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR3_Output</name>
|
|
<displayName>CCMR3_Output</displayName>
|
|
<description>capture/compare mode register 2 (output mode)</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC6M_bit3</name>
|
|
<description>Output Compare 6 mode bit 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5M_bit3</name>
|
|
<description>Output Compare 5 mode bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6CE</name>
|
|
<description>Output compare 6 clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6M</name>
|
|
<description>Output compare 6 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6PE</name>
|
|
<description>Output compare 6 preload enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6FE</name>
|
|
<description>Output compare 6 fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5CE</name>
|
|
<description>Output compare 5 clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5M</name>
|
|
<description>Output compare 5 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5PE</name>
|
|
<description>Output compare 5 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5FE</name>
|
|
<description>Output compare 5 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTR2</name>
|
|
<displayName>DTR2</displayName>
|
|
<description>timer Deadtime Register 2</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTPE</name>
|
|
<description>Deadtime Preload Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTAE</name>
|
|
<description>Deadtime Asymmetric Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTGF</name>
|
|
<description>Dead-time falling edge generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECR</name>
|
|
<displayName>ECR</displayName>
|
|
<description>DMA control register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Index Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDIR</name>
|
|
<description>Index Direction</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBLK</name>
|
|
<description>Index Blanking</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIDX</name>
|
|
<description>First Index</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPOS</name>
|
|
<description>Index Positioning</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PW</name>
|
|
<description>Pulse width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWPRSC</name>
|
|
<description>Pulse Width prescaler</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TISEL</name>
|
|
<displayName>TISEL</displayName>
|
|
<description>TIM timer input selection register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TI1SEL</name>
|
|
<description>TI1[0] to TI1[15] input selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI2SEL</name>
|
|
<description>TI2[0] to TI2[15] input selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI3SEL</name>
|
|
<description>TI3[0] to TI3[15] input selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI4SEL</name>
|
|
<description>TI4[0] to TI4[15] input selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF1</name>
|
|
<displayName>AF1</displayName>
|
|
<description>TIM alternate function option register 1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETRSEL</name>
|
|
<description>ETR source selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP4P</name>
|
|
<description>BRK COMP4 input polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3P</name>
|
|
<description>BRK COMP3 input polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2P</name>
|
|
<description>BRK COMP2 input polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1P</name>
|
|
<description>BRK COMP1 input polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINP</name>
|
|
<description>BRK BKIN input polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP7E</name>
|
|
<description>BRK COMP7 enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP6E</name>
|
|
<description>BRK COMP6 enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP5E</name>
|
|
<description>BRK COMP5 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP4E</name>
|
|
<description>BRK COMP4 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3E</name>
|
|
<description>BRK COMP3 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2E</name>
|
|
<description>BRK COMP2 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1E</name>
|
|
<description>BRK COMP1 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINE</name>
|
|
<description>BRK BKIN input enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF2</name>
|
|
<displayName>AF2</displayName>
|
|
<description>TIM alternate function option register 2</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCRSEL</name>
|
|
<description>OCREF_CLR source selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP4P</name>
|
|
<description>BRK2 COMP4 input polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP3P</name>
|
|
<description>BRK2 COMP3 input polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP2P</name>
|
|
<description>BRK2 COMP2 input polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP1P</name>
|
|
<description>BRK2 COMP1 input polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2INP</name>
|
|
<description>BRK2 BKIN input polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP7E</name>
|
|
<description>BRK2 COMP7 enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP6E</name>
|
|
<description>BRK2 COMP6 enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP5E</name>
|
|
<description>BRK2 COMP5 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP4E</name>
|
|
<description>BRK2 COMP4 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP3E</name>
|
|
<description>BRK2 COMP3 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP2E</name>
|
|
<description>BRK2 COMP2 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP1E</name>
|
|
<description>BRK2 COMP1 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINE</name>
|
|
<description>BRK BKIN input enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<displayName>DCR</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x3DC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>DMA burst length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>DMA base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<displayName>DMAR</displayName>
|
|
<description>DMA address for full transfer</description>
|
|
<addressOffset>0x3E0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>DMA register for burst accesses</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM1">
|
|
<name>TIM20</name>
|
|
<baseAddress>0x40015000</baseAddress>
|
|
<interrupt>
|
|
<name>TIM20_BRK</name>
|
|
<description>TIM20_BRK</description>
|
|
<value>77</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM20_UP</name>
|
|
<description>TIM20_UP</description>
|
|
<value>78</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM20_TRG_COM</name>
|
|
<description>TIM20_TRG_COM</description>
|
|
<value>79</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM20_CC</name>
|
|
<description>TIM20_CC</description>
|
|
<value>80</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM1">
|
|
<name>TIM8</name>
|
|
<baseAddress>0x40013400</baseAddress>
|
|
<interrupt>
|
|
<name>TIM8_BRK</name>
|
|
<description>TIM8_BRK</description>
|
|
<value>43</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM8_UP</name>
|
|
<description>TIM8_UP</description>
|
|
<value>44</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM8_TRG_COM</name>
|
|
<description>TIM8_TRG_COM</description>
|
|
<value>45</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM2</name>
|
|
<description>Advanced-timers</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM2</name>
|
|
<description>TIM2</description>
|
|
<value>28</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>Dithering Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIFREMAP</name>
|
|
<description>UIF status bit remapping</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>Clock division</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>Auto-reload preload enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>Center-aligned mode selection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Direction</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>One-pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>Update request source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MMS_3</name>
|
|
<description>Master mode selection - bit 3</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMS2</name>
|
|
<description>Master mode selection 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS6</name>
|
|
<description>Output Idle state 6 (OC6 output)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS5</name>
|
|
<description>Output Idle state 5 (OC5 output)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS4N</name>
|
|
<description>Output Idle state 4 (OC4N output)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS4</name>
|
|
<description>Output Idle state 4</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS3N</name>
|
|
<description>Output Idle state 3</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS3</name>
|
|
<description>Output Idle state 3</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS2N</name>
|
|
<description>Output Idle state 2</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS2</name>
|
|
<description>Output Idle state 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS1N</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIS1</name>
|
|
<description>Output Idle state 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>TI1 selection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>Master mode selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>Capture/compare DMA selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCUS</name>
|
|
<description>Capture/compare control update selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCPC</name>
|
|
<description>Capture/compare preloaded control</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<displayName>SMCR</displayName>
|
|
<description>slave mode control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMSPS</name>
|
|
<description>SMS Preload Source</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMSPE</name>
|
|
<description>SMS Preload Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TS_4_3</name>
|
|
<description>Trigger selection - bit 4:3</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMS_3</name>
|
|
<description>Slave mode selection - bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>External trigger polarity</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECE</name>
|
|
<description>External clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETPS</name>
|
|
<description>External trigger prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ETF</name>
|
|
<description>External trigger filter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>Master/Slave mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>Trigger selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OCCS</name>
|
|
<description>OCREF clear selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>Slave mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<displayName>DIER</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERRIE</name>
|
|
<description>Transition Error interrupt enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IERRIE</name>
|
|
<description>Index Error interrupt enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIRIE</name>
|
|
<description>Direction Change interrupt enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDXIE</name>
|
|
<description>Index interrupt enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>Trigger DMA request enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMDE</name>
|
|
<description>COM DMA request enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>Capture/Compare 4 DMA request enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>Capture/Compare 3 DMA request enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>Capture/Compare 2 DMA request enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>Capture/Compare 1 DMA request enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>Trigger interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>Capture/Compare 4 interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>Capture/Compare 3 interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>Capture/Compare 2 interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>Capture/Compare 1 interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIE</name>
|
|
<description>Break interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIE</name>
|
|
<description>COM interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TERRF</name>
|
|
<description>Transition Error interrupt flag</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IERRF</name>
|
|
<description>Index Error interrupt flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIRF</name>
|
|
<description>Direction Change interrupt flag</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDXF</name>
|
|
<description>Index interrupt flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC6IF</name>
|
|
<description>Compare 6 interrupt flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC5IF</name>
|
|
<description>Compare 5 interrupt flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBIF</name>
|
|
<description>System Break interrupt flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>Capture/Compare 4 overcapture flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>Capture/Compare 3 overcapture flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>Capture/compare 2 overcapture flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>Capture/Compare 1 overcapture flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B2IF</name>
|
|
<description>Break 2 interrupt flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>Break interrupt flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>Trigger interrupt flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>COM interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>Capture/Compare 4 interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>Capture/Compare 3 interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>Capture/Compare 2 interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>Capture/compare 1 interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<displayName>EGR</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>B2G</name>
|
|
<description>Break 2 generation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BG</name>
|
|
<description>Break generation</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>Trigger generation</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMG</name>
|
|
<description>Capture/Compare control update generation</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>Capture/compare 4 generation</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>Capture/compare 3 generation</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>Capture/compare 2 generation</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/compare 1 generation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Output</name>
|
|
<displayName>CCMR1_Output</displayName>
|
|
<description>capture/compare mode register 1 (output mode)</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC2M_3</name>
|
|
<description>Output Compare 2 mode - bit 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1M_3</name>
|
|
<description>Output Compare 1 mode - bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>Output Compare 2 clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>Output Compare 2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>Output Compare 2 preload enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>Output Compare 2 fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>Capture/Compare 2 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>Output Compare 1 clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>Output Compare 1 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>Output Compare 1 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>Output Compare 1 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_Input</name>
|
|
<displayName>CCMR1_Input</displayName>
|
|
<description>capture/compare mode register 1 (input mode)</description>
|
|
<alternateRegister>CCMR1_Output</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>Input capture 2 filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>Input capture 2 prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>Capture/Compare 2 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>Input capture 1 filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ICPCS</name>
|
|
<description>Input capture 1 prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>Capture/Compare 1 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_Output</name>
|
|
<displayName>CCMR2_Output</displayName>
|
|
<description>capture/compare mode register 2 (output mode)</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC4M_3</name>
|
|
<description>Output Compare 4 mode - bit 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3M_3</name>
|
|
<description>Output Compare 3 mode - bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4CE</name>
|
|
<description>Output compare 4 clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4M</name>
|
|
<description>Output compare 4 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4PE</name>
|
|
<description>Output compare 4 preload enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC4FE</name>
|
|
<description>Output compare 4 fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>Capture/Compare 4 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3CE</name>
|
|
<description>Output compare 3 clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3M</name>
|
|
<description>Output compare 3 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3PE</name>
|
|
<description>Output compare 3 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC3FE</name>
|
|
<description>Output compare 3 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>Capture/Compare 3 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_Input</name>
|
|
<displayName>CCMR2_Input</displayName>
|
|
<description>capture/compare mode register 2 (input mode)</description>
|
|
<alternateRegister>CCMR2_Output</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IC4F</name>
|
|
<description>Input capture 4 filter</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC4PSC</name>
|
|
<description>Input capture 4 prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>Capture/Compare 4 selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC3F</name>
|
|
<description>Input capture 3 filter</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IC3PSC</name>
|
|
<description>Input capture 3 prescaler</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>Capture/compare 3 selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<displayName>CCER</displayName>
|
|
<description>capture/compare enable register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CC6P</name>
|
|
<description>Capture/Compare 6 output polarity</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC6E</name>
|
|
<description>Capture/Compare 6 output enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC5P</name>
|
|
<description>Capture/Compare 5 output polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC5E</name>
|
|
<description>Capture/Compare 5 output enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4NP</name>
|
|
<description>Capture/Compare 4 complementary output polarity</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4NE</name>
|
|
<description>Capture/Compare 4 complementary output enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>Capture/Compare 3 output Polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>Capture/Compare 4 output enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3NP</name>
|
|
<description>Capture/Compare 3 output Polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3NE</name>
|
|
<description>Capture/Compare 3 complementary output enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>Capture/Compare 3 output Polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>Capture/Compare 3 output enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2NP</name>
|
|
<description>Capture/Compare 2 output Polarity</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2NE</name>
|
|
<description>Capture/Compare 2 complementary output enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>Capture/Compare 2 output Polarity</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>Capture/Compare 2 output enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1NP</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1NE</name>
|
|
<description>Capture/Compare 1 complementary output enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>Capture/Compare 1 output Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>Capture/Compare 1 output enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>counter</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UIFCPY</name>
|
|
<description>UIFCPY</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>prescaler</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>auto-reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auto-reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<displayName>RCR</displayName>
|
|
<description>repetition counter register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<displayName>CCR1</displayName>
|
|
<description>capture/compare register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>Capture/Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<displayName>CCR2</displayName>
|
|
<description>capture/compare register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>Capture/Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<displayName>CCR3</displayName>
|
|
<description>capture/compare register 3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR3</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<displayName>CCR4</displayName>
|
|
<description>capture/compare register 4</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR4</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<displayName>BDTR</displayName>
|
|
<description>break and dead-time register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BK2ID</name>
|
|
<description>BK2ID</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKBID</name>
|
|
<description>BKBID</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2DSRM</name>
|
|
<description>BK2DSRM</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKDSRM</name>
|
|
<description>BKDSRM</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2P</name>
|
|
<description>Break 2 polarity</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2E</name>
|
|
<description>Break 2 Enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2F</name>
|
|
<description>Break 2 filter</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKF</name>
|
|
<description>Break filter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>Main output enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>Automatic output enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>Break polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>Break enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>Off-state selection for Run mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>Off-state selection for Idle mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>Lock configuration</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>Dead-time generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR5</name>
|
|
<displayName>CCR5</displayName>
|
|
<description>capture/compare register 4</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR5</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GC5C1</name>
|
|
<description>Group Channel 5 and Channel 1</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GC5C2</name>
|
|
<description>Group Channel 5 and Channel 2</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GC5C3</name>
|
|
<description>Group Channel 5 and Channel 3</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR6</name>
|
|
<displayName>CCR6</displayName>
|
|
<description>capture/compare register 4</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR6</name>
|
|
<description>Capture/Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR3_Output</name>
|
|
<displayName>CCMR3_Output</displayName>
|
|
<description>capture/compare mode register 2 (output mode)</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OC6M_bit3</name>
|
|
<description>Output Compare 6 mode bit 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5M_bit3</name>
|
|
<description>Output Compare 5 mode bit 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6CE</name>
|
|
<description>Output compare 6 clear enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6M</name>
|
|
<description>Output compare 6 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6PE</name>
|
|
<description>Output compare 6 preload enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC6FE</name>
|
|
<description>Output compare 6 fast enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5CE</name>
|
|
<description>Output compare 5 clear enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5M</name>
|
|
<description>Output compare 5 mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5PE</name>
|
|
<description>Output compare 5 preload enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OC5FE</name>
|
|
<description>Output compare 5 fast enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTR2</name>
|
|
<displayName>DTR2</displayName>
|
|
<description>timer Deadtime Register 2</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTPE</name>
|
|
<description>Deadtime Preload Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTAE</name>
|
|
<description>Deadtime Asymmetric Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTGF</name>
|
|
<description>Dead-time falling edge generator setup</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECR</name>
|
|
<displayName>ECR</displayName>
|
|
<description>DMA control register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>Index Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDIR</name>
|
|
<description>Index Direction</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBLK</name>
|
|
<description>Index Blanking</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIDX</name>
|
|
<description>First Index</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPOS</name>
|
|
<description>Index Positioning</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PW</name>
|
|
<description>Pulse width</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWPRSC</name>
|
|
<description>Pulse Width prescaler</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TISEL</name>
|
|
<displayName>TISEL</displayName>
|
|
<description>TIM timer input selection register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TI1SEL</name>
|
|
<description>TI1[0] to TI1[15] input selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI2SEL</name>
|
|
<description>TI2[0] to TI2[15] input selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI3SEL</name>
|
|
<description>TI3[0] to TI3[15] input selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TI4SEL</name>
|
|
<description>TI4[0] to TI4[15] input selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF1</name>
|
|
<displayName>AF1</displayName>
|
|
<description>TIM alternate function option register 1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETRSEL</name>
|
|
<description>ETR source selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP4P</name>
|
|
<description>BRK COMP4 input polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3P</name>
|
|
<description>BRK COMP3 input polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2P</name>
|
|
<description>BRK COMP2 input polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1P</name>
|
|
<description>BRK COMP1 input polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINP</name>
|
|
<description>BRK BKIN input polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP7E</name>
|
|
<description>BRK COMP7 enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP6E</name>
|
|
<description>BRK COMP6 enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP5E</name>
|
|
<description>BRK COMP5 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP4E</name>
|
|
<description>BRK COMP4 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP3E</name>
|
|
<description>BRK COMP3 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP2E</name>
|
|
<description>BRK COMP2 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKCMP1E</name>
|
|
<description>BRK COMP1 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINE</name>
|
|
<description>BRK BKIN input enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AF2</name>
|
|
<displayName>AF2</displayName>
|
|
<description>TIM alternate function option register 2</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCRSEL</name>
|
|
<description>OCREF_CLR source selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP4P</name>
|
|
<description>BRK2 COMP4 input polarity</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP3P</name>
|
|
<description>BRK2 COMP3 input polarity</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP2P</name>
|
|
<description>BRK2 COMP2 input polarity</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP1P</name>
|
|
<description>BRK2 COMP1 input polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2INP</name>
|
|
<description>BRK2 BKIN input polarity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP7E</name>
|
|
<description>BRK2 COMP7 enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP6E</name>
|
|
<description>BRK2 COMP6 enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP5E</name>
|
|
<description>BRK2 COMP5 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP4E</name>
|
|
<description>BRK2 COMP4 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP3E</name>
|
|
<description>BRK2 COMP3 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP2E</name>
|
|
<description>BRK2 COMP2 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BK2CMP1E</name>
|
|
<description>BRK2 COMP1 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKINE</name>
|
|
<description>BRK BKIN input enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<displayName>DCR</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x3DC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>DMA burst length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>DMA base address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<displayName>DMAR</displayName>
|
|
<description>DMA address for full transfer</description>
|
|
<addressOffset>0x3E0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>DMA register for burst accesses</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM2">
|
|
<name>TIM3</name>
|
|
<baseAddress>0x40000400</baseAddress>
|
|
<interrupt>
|
|
<name>TIM3</name>
|
|
<description>TIM3</description>
|
|
<value>29</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM2">
|
|
<name>TIM4</name>
|
|
<baseAddress>0x40000800</baseAddress>
|
|
<interrupt>
|
|
<name>TIM4</name>
|
|
<description>TIM4</description>
|
|
<value>30</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM2">
|
|
<name>TIM5</name>
|
|
<baseAddress>0x40000C00</baseAddress>
|
|
<interrupt>
|
|
<name>TIM5</name>
|
|
<description>TIM5</description>
|
|
<value>50</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM6</name>
|
|
<description>Basic-timers</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM6_DACUNDER</name>
|
|
<description>TIM6_DACUNDER</description>
|
|
<value>54</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DITHEN</name>
|
|
<description>Dithering Enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIFREMAP</name>
|
|
<description>UIF status bit remapping</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>Auto-reload preload enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>One-pulse mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>Update request source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>Update disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>Master mode selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<displayName>DIER</displayName>
|
|
<description>DMA/Interrupt enable register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>Update DMA request enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>Update interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>Update interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<displayName>EGR</displayName>
|
|
<description>event generation register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>Update generation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>counter</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UIFCPY</name>
|
|
<description>UIF Copy</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Low counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<displayName>PSC</displayName>
|
|
<description>prescaler</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>auto-reload register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Low Auto-reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM6">
|
|
<name>TIM7</name>
|
|
<baseAddress>0x40001400</baseAddress>
|
|
<interrupt>
|
|
<name>TIM7</name>
|
|
<description>TIM7</description>
|
|
<value>55</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPTIMER1</name>
|
|
<description>Low power timer</description>
|
|
<groupName>LPTIM</groupName>
|
|
<baseAddress>0x40007C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DOWN</name>
|
|
<description>Counter direction change up to down</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UP</name>
|
|
<description>Counter direction change down to up</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROK</name>
|
|
<description>Autoreload register update OK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPOK</name>
|
|
<description>Compare register update OK</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTTRIG</name>
|
|
<description>External trigger edge event</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARRM</name>
|
|
<description>Autoreload match</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPM</name>
|
|
<description>Compare match</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DOWNCF</name>
|
|
<description>Direction change to down Clear Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPCF</name>
|
|
<description>Direction change to UP Clear Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROKCF</name>
|
|
<description>Autoreload register update OK Clear Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPOKCF</name>
|
|
<description>Compare register update OK Clear Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTTRIGCF</name>
|
|
<description>External trigger valid edge Clear Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARRMCF</name>
|
|
<description>Autoreload match Clear Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPMCF</name>
|
|
<description>compare match Clear Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DOWNIE</name>
|
|
<description>Direction change to down Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPIE</name>
|
|
<description>Direction change to UP Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROKIE</name>
|
|
<description>Autoreload register update OK Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPOKIE</name>
|
|
<description>Compare register update OK Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTTRIGIE</name>
|
|
<description>External trigger valid edge Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARRMIE</name>
|
|
<description>Autoreload match Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMPMIE</name>
|
|
<description>Compare match Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENC</name>
|
|
<description>Encoder mode enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTMODE</name>
|
|
<description>counter mode enabled</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRELOAD</name>
|
|
<description>Registers update mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAVPOL</name>
|
|
<description>Waveform shape polarity</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAVE</name>
|
|
<description>Waveform shape</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMOUT</name>
|
|
<description>Timeout enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIGEN</name>
|
|
<description>Trigger enable and polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIGSEL</name>
|
|
<description>Trigger selector</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Clock prescaler</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRGFLT</name>
|
|
<description>Configurable digital filter for trigger</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKFLT</name>
|
|
<description>Configurable digital filter for external clock</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPOL</name>
|
|
<description>Clock Polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKSEL</name>
|
|
<description>Clock selector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RSTARE</name>
|
|
<description>RSTARE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTRST</name>
|
|
<description>COUNTRST</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTSTRT</name>
|
|
<description>Timer start in continuous mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SNGSTRT</name>
|
|
<description>LPTIM start in single mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>LPTIM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP</name>
|
|
<displayName>CMP</displayName>
|
|
<description>Compare Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP</name>
|
|
<description>Compare value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>Autoreload Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OR</name>
|
|
<displayName>OR</displayName>
|
|
<description>option register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IN1</name>
|
|
<description>IN1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IN2</name>
|
|
<description>IN2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IN1_2_1</name>
|
|
<description>IN1_2_1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IN2_2_1</name>
|
|
<description>IN2_2_1</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART1</name>
|
|
<description>Universal synchronous asynchronous receiver transmitter</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40013800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART1</name>
|
|
<description>USART1</description>
|
|
<value>37</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFFIE</name>
|
|
<description>RXFFIE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFEIE</name>
|
|
<description>TXFEIE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFOEN</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>M1</name>
|
|
<description>M1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOBIE</name>
|
|
<description>End of Block interrupt enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOIE</name>
|
|
<description>Receiver timeout interrupt enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT4</name>
|
|
<description>Driver Enable assertion time</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT3</name>
|
|
<description>DEAT3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT2</name>
|
|
<description>DEAT2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT1</name>
|
|
<description>DEAT1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT0</name>
|
|
<description>DEAT0</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT4</name>
|
|
<description>Driver Enable de-assertion time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT3</name>
|
|
<description>DEDT3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT2</name>
|
|
<description>DEDT2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT1</name>
|
|
<description>DEDT1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT0</name>
|
|
<description>DEDT0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVER8</name>
|
|
<description>Oversampling mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMIE</name>
|
|
<description>Character match interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MME</name>
|
|
<description>Mute mode enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>M0</name>
|
|
<description>Word length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver wakeup method</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Parity control enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>PE interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission complete interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>RXNE interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEIE</name>
|
|
<description>IDLE interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UESM</name>
|
|
<description>USART enable in Stop mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USART enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD4_7</name>
|
|
<description>Address of the USART node</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADD0_3</name>
|
|
<description>Address of the USART node</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOEN</name>
|
|
<description>Receiver timeout enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRMOD1</name>
|
|
<description>Auto baud rate mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRMOD0</name>
|
|
<description>ABRMOD0</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABREN</name>
|
|
<description>Auto baud rate enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSBFIRST</name>
|
|
<description>Most significant bit first</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAINV</name>
|
|
<description>Binary data inversion</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>TX pin active level inversion</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>RX pin active level inversion</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap TX/RX pins</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LINEN</name>
|
|
<description>LIN mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>STOP bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBCL</name>
|
|
<description>Last bit clock pulse</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDIE</name>
|
|
<description>LIN break detection interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDL</name>
|
|
<description>LIN break detection length</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDM7</name>
|
|
<description>7-bit Address Detection/4-bit Address Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIS_NSS</name>
|
|
<description>DIS_NSS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLVEN</name>
|
|
<description>SLVEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR3</name>
|
|
<displayName>CR3</displayName>
|
|
<description>Control register 3</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFTCFG</name>
|
|
<description>TXFTCFG</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFTIE</name>
|
|
<description>RXFTIE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFTCFG</name>
|
|
<description>RXFTCFG</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCBGTIE</name>
|
|
<description>TCBGTIE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFTIE</name>
|
|
<description>TXFTIE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUFIE</name>
|
|
<description>Wakeup from Stop mode interrupt enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUS</name>
|
|
<description>Wakeup from Stop mode interrupt flag selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCARCNT</name>
|
|
<description>Smartcard auto-retry count</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEP</name>
|
|
<description>Driver enable polarity selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEM</name>
|
|
<description>Driver enable mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDRE</name>
|
|
<description>DMA Disable on Reception Error</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRDIS</name>
|
|
<description>Overrun Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONEBIT</name>
|
|
<description>One sample bit method enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSE</name>
|
|
<description>CTS enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTSE</name>
|
|
<description>RTS enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAT</name>
|
|
<description>DMA enable transmitter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAR</name>
|
|
<description>DMA enable receiver</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCEN</name>
|
|
<description>Smartcard mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Smartcard NACK enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDSEL</name>
|
|
<description>Half-duplex selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IRLP</name>
|
|
<description>Ir low-power</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Ir mode enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>Baud rate register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_Mantissa</name>
|
|
<description>DIV_Mantissa</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV_Fraction</name>
|
|
<description>DIV_Fraction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPR</name>
|
|
<displayName>GTPR</displayName>
|
|
<description>Guard time and prescaler register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GT</name>
|
|
<description>Guard time value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTOR</name>
|
|
<displayName>RTOR</displayName>
|
|
<description>Receiver timeout register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLEN</name>
|
|
<description>Block Length</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTO</name>
|
|
<description>Receiver timeout value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQR</name>
|
|
<displayName>RQR</displayName>
|
|
<description>Request register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFRQ</name>
|
|
<description>Transmit data flush request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFRQ</name>
|
|
<description>Receive data flush request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMRQ</name>
|
|
<description>Mute mode request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKRQ</name>
|
|
<description>Send break request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRRQ</name>
|
|
<description>Auto baud rate request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt & status register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFT</name>
|
|
<description>TXFT</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFT</name>
|
|
<description>RXFT</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCBGT</name>
|
|
<description>TCBGT</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFF</name>
|
|
<description>RXFF</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>TXFE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REACK</name>
|
|
<description>REACK</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEACK</name>
|
|
<description>TEACK</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF</name>
|
|
<description>WUF</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>RWU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKF</name>
|
|
<description>SBKF</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMF</name>
|
|
<description>CMF</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>BUSY</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRF</name>
|
|
<description>ABRF</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRE</name>
|
|
<description>ABRE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDR</name>
|
|
<description>UDR</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOBF</name>
|
|
<description>EOBF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOF</name>
|
|
<description>RTOF</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIF</name>
|
|
<description>CTSIF</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDF</name>
|
|
<description>LBDF</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TXE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>TC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>RXNE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>IDLE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>ORE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>NF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>FE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>PE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt flag clear register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WUCF</name>
|
|
<description>Wakeup from Stop mode clear flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMCF</name>
|
|
<description>Character match clear flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDRCF</name>
|
|
<description>UDRCF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOBCF</name>
|
|
<description>End of block clear flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOCF</name>
|
|
<description>Receiver timeout clear flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSCF</name>
|
|
<description>CTS clear flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDCF</name>
|
|
<description>LIN break detection clear flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCBGTCF</name>
|
|
<description>TCBGTCF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCF</name>
|
|
<description>Transmission complete clear flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFECF</name>
|
|
<description>TXFECF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLECF</name>
|
|
<description>Idle line detected clear flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORECF</name>
|
|
<description>Overrun error clear flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NCF</name>
|
|
<description>Noise detected clear flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FECF</name>
|
|
<description>Framing error clear flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECF</name>
|
|
<description>Parity error clear flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<displayName>RDR</displayName>
|
|
<description>Receive data register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receive data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<displayName>TDR</displayName>
|
|
<description>Transmit data register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TDR</name>
|
|
<description>Transmit data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESC</name>
|
|
<displayName>PRESC</displayName>
|
|
<description>USART prescaler register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>PRESCALER</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART1">
|
|
<name>USART2</name>
|
|
<baseAddress>0x40004400</baseAddress>
|
|
<interrupt>
|
|
<name>USART2</name>
|
|
<description>USART2</description>
|
|
<value>38</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART1">
|
|
<name>USART3</name>
|
|
<baseAddress>0x40004800</baseAddress>
|
|
<interrupt>
|
|
<name>USART3</name>
|
|
<description>USART3</description>
|
|
<value>39</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UART4</name>
|
|
<description>Universal synchronous asynchronous receiver transmitter</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40004C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UART4</name>
|
|
<description>UART4</description>
|
|
<value>52</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFFIE</name>
|
|
<description>RXFFIE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFEIE</name>
|
|
<description>TXFEIE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFOEN</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>M1</name>
|
|
<description>M1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOBIE</name>
|
|
<description>End of Block interrupt enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOIE</name>
|
|
<description>Receiver timeout interrupt enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT4</name>
|
|
<description>Driver Enable assertion time</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT3</name>
|
|
<description>DEAT3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT2</name>
|
|
<description>DEAT2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT1</name>
|
|
<description>DEAT1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT0</name>
|
|
<description>DEAT0</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT4</name>
|
|
<description>Driver Enable de-assertion time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT3</name>
|
|
<description>DEDT3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT2</name>
|
|
<description>DEDT2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT1</name>
|
|
<description>DEDT1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT0</name>
|
|
<description>DEDT0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVER8</name>
|
|
<description>Oversampling mode</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMIE</name>
|
|
<description>Character match interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MME</name>
|
|
<description>Mute mode enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>M0</name>
|
|
<description>Word length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver wakeup method</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Parity control enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>PE interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission complete interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>RXNE interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEIE</name>
|
|
<description>IDLE interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UESM</name>
|
|
<description>USART enable in Stop mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USART enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD4_7</name>
|
|
<description>Address of the USART node</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADD0_3</name>
|
|
<description>Address of the USART node</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOEN</name>
|
|
<description>Receiver timeout enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRMOD1</name>
|
|
<description>Auto baud rate mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRMOD0</name>
|
|
<description>ABRMOD0</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABREN</name>
|
|
<description>Auto baud rate enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSBFIRST</name>
|
|
<description>Most significant bit first</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAINV</name>
|
|
<description>Binary data inversion</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>TX pin active level inversion</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>RX pin active level inversion</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap TX/RX pins</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LINEN</name>
|
|
<description>LIN mode enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>STOP bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBCL</name>
|
|
<description>Last bit clock pulse</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDIE</name>
|
|
<description>LIN break detection interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDL</name>
|
|
<description>LIN break detection length</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDM7</name>
|
|
<description>7-bit Address Detection/4-bit Address Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIS_NSS</name>
|
|
<description>DIS_NSS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLVEN</name>
|
|
<description>SLVEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR3</name>
|
|
<displayName>CR3</displayName>
|
|
<description>Control register 3</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFTCFG</name>
|
|
<description>TXFTCFG</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFTIE</name>
|
|
<description>RXFTIE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFTCFG</name>
|
|
<description>RXFTCFG</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCBGTIE</name>
|
|
<description>TCBGTIE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFTIE</name>
|
|
<description>TXFTIE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUFIE</name>
|
|
<description>Wakeup from Stop mode interrupt enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUS</name>
|
|
<description>Wakeup from Stop mode interrupt flag selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCARCNT</name>
|
|
<description>Smartcard auto-retry count</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEP</name>
|
|
<description>Driver enable polarity selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEM</name>
|
|
<description>Driver enable mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDRE</name>
|
|
<description>DMA Disable on Reception Error</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRDIS</name>
|
|
<description>Overrun Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ONEBIT</name>
|
|
<description>One sample bit method enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSE</name>
|
|
<description>CTS enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTSE</name>
|
|
<description>RTS enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAT</name>
|
|
<description>DMA enable transmitter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAR</name>
|
|
<description>DMA enable receiver</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCEN</name>
|
|
<description>Smartcard mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>Smartcard NACK enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDSEL</name>
|
|
<description>Half-duplex selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IRLP</name>
|
|
<description>Ir low-power</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>Ir mode enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>Baud rate register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_Mantissa</name>
|
|
<description>DIV_Mantissa</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV_Fraction</name>
|
|
<description>DIV_Fraction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPR</name>
|
|
<displayName>GTPR</displayName>
|
|
<description>Guard time and prescaler register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GT</name>
|
|
<description>Guard time value</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>Prescaler value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTOR</name>
|
|
<displayName>RTOR</displayName>
|
|
<description>Receiver timeout register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLEN</name>
|
|
<description>Block Length</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTO</name>
|
|
<description>Receiver timeout value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQR</name>
|
|
<displayName>RQR</displayName>
|
|
<description>Request register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFRQ</name>
|
|
<description>Transmit data flush request</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFRQ</name>
|
|
<description>Receive data flush request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMRQ</name>
|
|
<description>Mute mode request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKRQ</name>
|
|
<description>Send break request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRRQ</name>
|
|
<description>Auto baud rate request</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt & status register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x000000C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFT</name>
|
|
<description>TXFT</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFT</name>
|
|
<description>RXFT</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCBGT</name>
|
|
<description>TCBGT</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFF</name>
|
|
<description>RXFF</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>TXFE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REACK</name>
|
|
<description>REACK</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEACK</name>
|
|
<description>TEACK</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF</name>
|
|
<description>WUF</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>RWU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKF</name>
|
|
<description>SBKF</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMF</name>
|
|
<description>CMF</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>BUSY</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRF</name>
|
|
<description>ABRF</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABRE</name>
|
|
<description>ABRE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDR</name>
|
|
<description>UDR</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOBF</name>
|
|
<description>EOBF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOF</name>
|
|
<description>RTOF</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIF</name>
|
|
<description>CTSIF</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDF</name>
|
|
<description>LBDF</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TXE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>TC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>RXNE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>IDLE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>ORE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>NF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>FE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>PE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt flag clear register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WUCF</name>
|
|
<description>Wakeup from Stop mode clear flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMCF</name>
|
|
<description>Character match clear flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDRCF</name>
|
|
<description>UDRCF</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOBCF</name>
|
|
<description>End of block clear flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTOCF</name>
|
|
<description>Receiver timeout clear flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSCF</name>
|
|
<description>CTS clear flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBDCF</name>
|
|
<description>LIN break detection clear flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCBGTCF</name>
|
|
<description>TCBGTCF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCF</name>
|
|
<description>Transmission complete clear flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFECF</name>
|
|
<description>TXFECF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLECF</name>
|
|
<description>Idle line detected clear flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORECF</name>
|
|
<description>Overrun error clear flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NCF</name>
|
|
<description>Noise detected clear flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FECF</name>
|
|
<description>Framing error clear flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECF</name>
|
|
<description>Parity error clear flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<displayName>RDR</displayName>
|
|
<description>Receive data register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receive data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<displayName>TDR</displayName>
|
|
<description>Transmit data register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TDR</name>
|
|
<description>Transmit data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESC</name>
|
|
<displayName>PRESC</displayName>
|
|
<description>USART prescaler register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>PRESCALER</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="UART4">
|
|
<name>UART5</name>
|
|
<baseAddress>0x40005000</baseAddress>
|
|
<interrupt>
|
|
<name>UART5</name>
|
|
<description>UART5</description>
|
|
<value>53</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPUART1</name>
|
|
<description>Universal synchronous asynchronous receiver transmitter</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40008000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LPTIM1</name>
|
|
<description>LPTIM1</description>
|
|
<value>49</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>LPUART</name>
|
|
<description>LPUART</description>
|
|
<value>91</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFFIE</name>
|
|
<description>RXFFIE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFEIE</name>
|
|
<description>TXFEIE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIFOEN</name>
|
|
<description>FIFOEN</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>M1</name>
|
|
<description>Word length</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT4</name>
|
|
<description>Driver Enable assertion time</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT3</name>
|
|
<description>DEAT3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT2</name>
|
|
<description>DEAT2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT1</name>
|
|
<description>DEAT1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEAT0</name>
|
|
<description>DEAT0</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT4</name>
|
|
<description>Driver Enable de-assertion time</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT3</name>
|
|
<description>DEDT3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT2</name>
|
|
<description>DEDT2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT1</name>
|
|
<description>DEDT1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEDT0</name>
|
|
<description>DEDT0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMIE</name>
|
|
<description>Character match interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MME</name>
|
|
<description>Mute mode enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>M0</name>
|
|
<description>Word length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Receiver wakeup method</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Parity control enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>PE interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission complete interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>RXNE interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEIE</name>
|
|
<description>IDLE interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UESM</name>
|
|
<description>USART enable in Stop mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USART enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD4_7</name>
|
|
<description>Address of the USART node</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADD0_3</name>
|
|
<description>Address of the USART node</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSBFIRST</name>
|
|
<description>Most significant bit first</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAINV</name>
|
|
<description>Binary data inversion</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXINV</name>
|
|
<description>TX pin active level inversion</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXINV</name>
|
|
<description>RX pin active level inversion</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWAP</name>
|
|
<description>Swap TX/RX pins</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>STOP bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDM7</name>
|
|
<description>7-bit Address Detection/4-bit Address Detection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR3</name>
|
|
<displayName>CR3</displayName>
|
|
<description>Control register 3</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFTCFG</name>
|
|
<description>TXFTCFG</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFTIE</name>
|
|
<description>RXFTIE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFTCFG</name>
|
|
<description>RXFTCFG</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFTIE</name>
|
|
<description>TXFTIE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUFIE</name>
|
|
<description>Wakeup from Stop mode interrupt enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUS</name>
|
|
<description>Wakeup from Stop mode interrupt flag selection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEP</name>
|
|
<description>Driver enable polarity selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEM</name>
|
|
<description>Driver enable mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DDRE</name>
|
|
<description>DMA Disable on Reception Error</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRDIS</name>
|
|
<description>Overrun Disable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSE</name>
|
|
<description>CTS enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTSE</name>
|
|
<description>RTS enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAT</name>
|
|
<description>DMA enable transmitter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAR</name>
|
|
<description>DMA enable receiver</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDSEL</name>
|
|
<description>Half-duplex selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>Baud rate register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BRR</name>
|
|
<description>BRR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RQR</name>
|
|
<displayName>RQR</displayName>
|
|
<description>Request register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFRQ</name>
|
|
<description>TXFRQ</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFRQ</name>
|
|
<description>Receive data flush request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMRQ</name>
|
|
<description>Mute mode request</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKRQ</name>
|
|
<description>Send break request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt & status register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXFT</name>
|
|
<description>TXFT</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFT</name>
|
|
<description>RXFT</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFF</name>
|
|
<description>RXFF</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXFE</name>
|
|
<description>TXFE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REACK</name>
|
|
<description>REACK</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEACK</name>
|
|
<description>TEACK</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUF</name>
|
|
<description>WUF</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>RWU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SBKF</name>
|
|
<description>SBKF</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMF</name>
|
|
<description>CMF</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>BUSY</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIF</name>
|
|
<description>CTSIF</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>TXE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>TC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>RXNE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>IDLE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>ORE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NF</name>
|
|
<description>NF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>FE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>PE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt flag clear register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WUCF</name>
|
|
<description>Wakeup from Stop mode clear flag</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMCF</name>
|
|
<description>Character match clear flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSCF</name>
|
|
<description>CTS clear flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCF</name>
|
|
<description>Transmission complete clear flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLECF</name>
|
|
<description>Idle line detected clear flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ORECF</name>
|
|
<description>Overrun error clear flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NCF</name>
|
|
<description>Noise detected clear flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FECF</name>
|
|
<description>Framing error clear flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PECF</name>
|
|
<description>Parity error clear flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDR</name>
|
|
<displayName>RDR</displayName>
|
|
<description>Receive data register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDR</name>
|
|
<description>Receive data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDR</name>
|
|
<displayName>TDR</displayName>
|
|
<description>Transmit data register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TDR</name>
|
|
<description>Transmit data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRESC</name>
|
|
<displayName>PRESC</displayName>
|
|
<description>Prescaler register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>PRESCALER</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI1</name>
|
|
<description>Serial peripheral interface/Inter-IC sound</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40013000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<description>SPI1</description>
|
|
<value>35</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BIDIMODE</name>
|
|
<description>Bidirectional data mode enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIDIOE</name>
|
|
<description>Output enable in bidirectional mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>Hardware CRC calculation enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCNEXT</name>
|
|
<description>CRC transfer next</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFF</name>
|
|
<description>Data frame format</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXONLY</name>
|
|
<description>Receive only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Software slave management</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSI</name>
|
|
<description>Internal slave select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSBFIRST</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>SPI enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR</name>
|
|
<description>Baud rate control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000700</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>Rx buffer DMA enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>Tx buffer DMA enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSOE</name>
|
|
<description>SS output enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSSP</name>
|
|
<description>NSS pulse management</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>RX buffer not empty interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>Tx buffer empty interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>Data size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRXTH</name>
|
|
<description>FIFO reception threshold</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_RX</name>
|
|
<description>Last DMA transfer for reception</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_TX</name>
|
|
<description>Last DMA transfer for transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>Receive buffer not empty</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmit buffer empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>CRC error flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode fault</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Overrun flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIFRFE</name>
|
|
<description>TI frame format error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRLVL</name>
|
|
<description>FIFO reception level</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FTLVL</name>
|
|
<description>FIFO transmission level</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>data register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Data register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCPR</name>
|
|
<displayName>CRCPR</displayName>
|
|
<description>CRC polynomial register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCPOLY</name>
|
|
<description>CRC polynomial register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCRCR</name>
|
|
<displayName>RXCRCR</displayName>
|
|
<description>RX CRC register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RxCRC</name>
|
|
<description>Rx CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCRCR</name>
|
|
<displayName>TXCRCR</displayName>
|
|
<description>TX CRC register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TxCRC</name>
|
|
<description>Tx CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCFGR</name>
|
|
<displayName>I2SCFGR</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHLEN</name>
|
|
<description>CHLEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLEN</name>
|
|
<description>DATLEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPOL</name>
|
|
<description>CKPOL</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SSTD</name>
|
|
<description>I2SSTD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCMSYNC</name>
|
|
<description>PCMSYNC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SCFG</name>
|
|
<description>I2SCFG</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SE</name>
|
|
<description>I2SE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SMOD</name>
|
|
<description>I2SMOD</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SPR</name>
|
|
<displayName>I2SPR</displayName>
|
|
<description>prescaler register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2SDIV</name>
|
|
<description>I2SDIV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODD</name>
|
|
<description>ODD</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCKOE</name>
|
|
<description>MCKOE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI4</name>
|
|
<description>Serial peripheral interface/Inter-IC sound</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40013C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI4</name>
|
|
<description>SPI4</description>
|
|
<value>84</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000700</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BIDIMODE</name>
|
|
<description>Bidirectional data mode enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIDIOE</name>
|
|
<description>Output enable in bidirectional mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>Hardware CRC calculation enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCNEXT</name>
|
|
<description>CRC transfer next</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFF</name>
|
|
<description>Data frame format</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXONLY</name>
|
|
<description>Receive only</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>Software slave management</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSI</name>
|
|
<description>Internal slave select</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSBFIRST</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>SPI enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR</name>
|
|
<description>Baud rate control</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>Master selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>Rx buffer DMA enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>Tx buffer DMA enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSOE</name>
|
|
<description>SS output enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSSP</name>
|
|
<description>NSS pulse management</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRF</name>
|
|
<description>Frame format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>RX buffer not empty interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>Tx buffer empty interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>Data size</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRXTH</name>
|
|
<description>FIFO reception threshold</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_RX</name>
|
|
<description>Last DMA transfer for reception</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_TX</name>
|
|
<description>Last DMA transfer for transmission</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>Receive buffer not empty</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmit buffer empty</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>CRC error flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>Mode fault</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Overrun flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIFRFE</name>
|
|
<description>TI frame format error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRLVL</name>
|
|
<description>FIFO reception level</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FTLVL</name>
|
|
<description>FIFO transmission level</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>data register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Data register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCPR</name>
|
|
<displayName>CRCPR</displayName>
|
|
<description>CRC polynomial register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCPOLY</name>
|
|
<description>CRC polynomial register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCRCR</name>
|
|
<displayName>RXCRCR</displayName>
|
|
<description>RX CRC register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RxCRC</name>
|
|
<description>Rx CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCRCR</name>
|
|
<displayName>TXCRCR</displayName>
|
|
<description>TX CRC register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TxCRC</name>
|
|
<description>Tx CRC register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCFGR</name>
|
|
<displayName>I2SCFGR</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHLEN</name>
|
|
<description>CHLEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLEN</name>
|
|
<description>DATLEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKPOL</name>
|
|
<description>CKPOL</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SSTD</name>
|
|
<description>I2SSTD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCMSYNC</name>
|
|
<description>PCMSYNC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SCFG</name>
|
|
<description>I2SCFG</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SE</name>
|
|
<description>I2SE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2SMOD</name>
|
|
<description>I2SMOD</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SPR</name>
|
|
<displayName>I2SPR</displayName>
|
|
<description>prescaler register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2SDIV</name>
|
|
<description>I2SDIV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ODD</name>
|
|
<description>ODD</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCKOE</name>
|
|
<description>MCKOE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI4">
|
|
<name>SPI3</name>
|
|
<baseAddress>0x40003C00</baseAddress>
|
|
<interrupt>
|
|
<name>SPI3</name>
|
|
<description>SPI3</description>
|
|
<value>51</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI4">
|
|
<name>SPI2</name>
|
|
<baseAddress>0x40003800</baseAddress>
|
|
<interrupt>
|
|
<name>SPI2</name>
|
|
<description>SPI2</description>
|
|
<value>36</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EXTI</name>
|
|
<description>External interrupt/event controller</description>
|
|
<groupName>EXTI</groupName>
|
|
<baseAddress>0x40010400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PVD_PVM</name>
|
|
<description>PVD through EXTI line detection</description>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI0</name>
|
|
<description>EXTI Line0 interrupt</description>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI1</name>
|
|
<description>EXTI Line1 interrupt</description>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI2</name>
|
|
<description>EXTI Line2 interrupt</description>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI3</name>
|
|
<description>EXTI Line3 interrupt</description>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI4</name>
|
|
<description>EXTI Line4 interrupt</description>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_HP</name>
|
|
<description>USB_HP</description>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USB_LP</name>
|
|
<description>USB_LP</description>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI9_5</name>
|
|
<description>EXTI9_5</description>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI15_10</name>
|
|
<description>EXTI15_10</description>
|
|
<value>40</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>USBWakeUP</name>
|
|
<description>USBWakeUP</description>
|
|
<value>42</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>CRS</name>
|
|
<description>CRS</description>
|
|
<value>75</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>IMR1</name>
|
|
<displayName>IMR1</displayName>
|
|
<description>Interrupt mask register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF820000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IM0</name>
|
|
<description>Interrupt Mask on line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM1</name>
|
|
<description>Interrupt Mask on line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM2</name>
|
|
<description>Interrupt Mask on line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM3</name>
|
|
<description>Interrupt Mask on line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM4</name>
|
|
<description>Interrupt Mask on line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM5</name>
|
|
<description>Interrupt Mask on line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM6</name>
|
|
<description>Interrupt Mask on line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM7</name>
|
|
<description>Interrupt Mask on line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM8</name>
|
|
<description>Interrupt Mask on line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM9</name>
|
|
<description>Interrupt Mask on line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM10</name>
|
|
<description>Interrupt Mask on line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM11</name>
|
|
<description>Interrupt Mask on line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM12</name>
|
|
<description>Interrupt Mask on line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM13</name>
|
|
<description>Interrupt Mask on line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM14</name>
|
|
<description>Interrupt Mask on line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM15</name>
|
|
<description>Interrupt Mask on line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM16</name>
|
|
<description>Interrupt Mask on line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM17</name>
|
|
<description>Interrupt Mask on line 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM18</name>
|
|
<description>Interrupt Mask on line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM19</name>
|
|
<description>Interrupt Mask on line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM20</name>
|
|
<description>Interrupt Mask on line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM21</name>
|
|
<description>Interrupt Mask on line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM22</name>
|
|
<description>Interrupt Mask on line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM23</name>
|
|
<description>Interrupt Mask on line 23</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM24</name>
|
|
<description>Interrupt Mask on line 24</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM25</name>
|
|
<description>Interrupt Mask on line 25</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM26</name>
|
|
<description>Interrupt Mask on line 26</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM27</name>
|
|
<description>Interrupt Mask on line 27</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM28</name>
|
|
<description>Interrupt Mask on line 28</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM29</name>
|
|
<description>Interrupt Mask on line 29</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM30</name>
|
|
<description>Interrupt Mask on line 30</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM31</name>
|
|
<description>Interrupt Mask on line 31</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR1</name>
|
|
<displayName>EMR1</displayName>
|
|
<description>Event mask register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>Event Mask on line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>Event Mask on line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>Event Mask on line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>Event Mask on line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM4</name>
|
|
<description>Event Mask on line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM5</name>
|
|
<description>Event Mask on line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM6</name>
|
|
<description>Event Mask on line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM7</name>
|
|
<description>Event Mask on line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM8</name>
|
|
<description>Event Mask on line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM9</name>
|
|
<description>Event Mask on line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM10</name>
|
|
<description>Event Mask on line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM11</name>
|
|
<description>Event Mask on line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM12</name>
|
|
<description>Event Mask on line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM13</name>
|
|
<description>Event Mask on line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM14</name>
|
|
<description>Event Mask on line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM15</name>
|
|
<description>Event Mask on line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM16</name>
|
|
<description>Event Mask on line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM17</name>
|
|
<description>Event Mask on line 17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM18</name>
|
|
<description>Event Mask on line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM19</name>
|
|
<description>Event Mask on line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM20</name>
|
|
<description>Event Mask on line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM21</name>
|
|
<description>Event Mask on line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM22</name>
|
|
<description>Event Mask on line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM23</name>
|
|
<description>Event Mask on line 23</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM24</name>
|
|
<description>Event Mask on line 24</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM25</name>
|
|
<description>Event Mask on line 25</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM26</name>
|
|
<description>Event Mask on line 26</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM27</name>
|
|
<description>Event Mask on line 27</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM28</name>
|
|
<description>Event Mask on line 28</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM29</name>
|
|
<description>Event Mask on line 29</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM30</name>
|
|
<description>Event Mask on line 30</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM31</name>
|
|
<description>Event Mask on line 31</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTSR1</name>
|
|
<displayName>RTSR1</displayName>
|
|
<description>Rising Trigger selection register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RT0</name>
|
|
<description>Rising trigger event configuration of line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT1</name>
|
|
<description>Rising trigger event configuration of line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT2</name>
|
|
<description>Rising trigger event configuration of line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT3</name>
|
|
<description>Rising trigger event configuration of line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT4</name>
|
|
<description>Rising trigger event configuration of line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT5</name>
|
|
<description>Rising trigger event configuration of line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT6</name>
|
|
<description>Rising trigger event configuration of line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT7</name>
|
|
<description>Rising trigger event configuration of line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT8</name>
|
|
<description>Rising trigger event configuration of line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT9</name>
|
|
<description>Rising trigger event configuration of line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT10</name>
|
|
<description>Rising trigger event configuration of line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT11</name>
|
|
<description>Rising trigger event configuration of line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT12</name>
|
|
<description>Rising trigger event configuration of line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT13</name>
|
|
<description>Rising trigger event configuration of line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT14</name>
|
|
<description>Rising trigger event configuration of line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT15</name>
|
|
<description>Rising trigger event configuration of line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT16</name>
|
|
<description>Rising trigger event configuration of line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT18</name>
|
|
<description>Rising trigger event configuration of line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT19</name>
|
|
<description>Rising trigger event configuration of line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT20</name>
|
|
<description>Rising trigger event configuration of line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT21</name>
|
|
<description>Rising trigger event configuration of line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT22</name>
|
|
<description>Rising trigger event configuration of line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT</name>
|
|
<description>RT</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTSR1</name>
|
|
<displayName>FTSR1</displayName>
|
|
<description>Falling Trigger selection register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FT0</name>
|
|
<description>Falling trigger event configuration of line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT1</name>
|
|
<description>Falling trigger event configuration of line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT2</name>
|
|
<description>Falling trigger event configuration of line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT3</name>
|
|
<description>Falling trigger event configuration of line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT4</name>
|
|
<description>Falling trigger event configuration of line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT5</name>
|
|
<description>Falling trigger event configuration of line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT6</name>
|
|
<description>Falling trigger event configuration of line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT7</name>
|
|
<description>Falling trigger event configuration of line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT8</name>
|
|
<description>Falling trigger event configuration of line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT9</name>
|
|
<description>Falling trigger event configuration of line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT10</name>
|
|
<description>Falling trigger event configuration of line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT11</name>
|
|
<description>Falling trigger event configuration of line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT12</name>
|
|
<description>Falling trigger event configuration of line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT13</name>
|
|
<description>Falling trigger event configuration of line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT14</name>
|
|
<description>Falling trigger event configuration of line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT15</name>
|
|
<description>Falling trigger event configuration of line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT16</name>
|
|
<description>Falling trigger event configuration of line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT18</name>
|
|
<description>Falling trigger event configuration of line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT19</name>
|
|
<description>Falling trigger event configuration of line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT20</name>
|
|
<description>Falling trigger event configuration of line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT21</name>
|
|
<description>Falling trigger event configuration of line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT22</name>
|
|
<description>Falling trigger event configuration of line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWIER1</name>
|
|
<displayName>SWIER1</displayName>
|
|
<description>Software interrupt event register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWI0</name>
|
|
<description>Software Interrupt on line 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI1</name>
|
|
<description>Software Interrupt on line 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI2</name>
|
|
<description>Software Interrupt on line 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI3</name>
|
|
<description>Software Interrupt on line 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI4</name>
|
|
<description>Software Interrupt on line 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI5</name>
|
|
<description>Software Interrupt on line 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI6</name>
|
|
<description>Software Interrupt on line 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI7</name>
|
|
<description>Software Interrupt on line 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI8</name>
|
|
<description>Software Interrupt on line 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI9</name>
|
|
<description>Software Interrupt on line 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI10</name>
|
|
<description>Software Interrupt on line 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI11</name>
|
|
<description>Software Interrupt on line 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI12</name>
|
|
<description>Software Interrupt on line 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI13</name>
|
|
<description>Software Interrupt on line 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI14</name>
|
|
<description>Software Interrupt on line 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI15</name>
|
|
<description>Software Interrupt on line 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI16</name>
|
|
<description>Software Interrupt on line 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI18</name>
|
|
<description>Software Interrupt on line 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI19</name>
|
|
<description>Software Interrupt on line 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI20</name>
|
|
<description>Software Interrupt on line 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI21</name>
|
|
<description>Software Interrupt on line 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI22</name>
|
|
<description>Software Interrupt on line 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR1</name>
|
|
<displayName>PR1</displayName>
|
|
<description>Pending register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PIF0</name>
|
|
<description>Pending bit 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF1</name>
|
|
<description>Pending bit 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF2</name>
|
|
<description>Pending bit 2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF3</name>
|
|
<description>Pending bit 3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF4</name>
|
|
<description>Pending bit 4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF5</name>
|
|
<description>Pending bit 5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF6</name>
|
|
<description>Pending bit 6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF7</name>
|
|
<description>Pending bit 7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF8</name>
|
|
<description>Pending bit 8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF9</name>
|
|
<description>Pending bit 9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF10</name>
|
|
<description>Pending bit 10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF11</name>
|
|
<description>Pending bit 11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF12</name>
|
|
<description>Pending bit 12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF13</name>
|
|
<description>Pending bit 13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF14</name>
|
|
<description>Pending bit 14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF15</name>
|
|
<description>Pending bit 15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF16</name>
|
|
<description>Pending bit 16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF18</name>
|
|
<description>Pending bit 18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF19</name>
|
|
<description>Pending bit 19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF20</name>
|
|
<description>Pending bit 20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF21</name>
|
|
<description>Pending bit 21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF22</name>
|
|
<description>Pending bit 22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR2</name>
|
|
<displayName>IMR2</displayName>
|
|
<description>Interrupt mask register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFF87</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IM32</name>
|
|
<description>Interrupt Mask on external/internal line 32</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM33</name>
|
|
<description>Interrupt Mask on external/internal line 33</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM34</name>
|
|
<description>Interrupt Mask on external/internal line 34</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM35</name>
|
|
<description>Interrupt Mask on external/internal line 35</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM36</name>
|
|
<description>Interrupt Mask on external/internal line 36</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM37</name>
|
|
<description>Interrupt Mask on external/internal line 37</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM38</name>
|
|
<description>Interrupt Mask on external/internal line 38</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM39</name>
|
|
<description>Interrupt Mask on external/internal line 39</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM40</name>
|
|
<description>Interrupt Mask on external/internal line 40</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM41</name>
|
|
<description>Interrupt Mask on external/internal line 41</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM42</name>
|
|
<description>Interrupt Mask on external/internal line 42</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM43</name>
|
|
<description>Interrupt Mask on external/internal line 43</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR2</name>
|
|
<displayName>EMR2</displayName>
|
|
<description>Event mask register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EM32</name>
|
|
<description>Event mask on external/internal line 32</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM33</name>
|
|
<description>Event mask on external/internal line 33</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM34</name>
|
|
<description>Event mask on external/internal line 34</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM35</name>
|
|
<description>Event mask on external/internal line 35</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM36</name>
|
|
<description>Event mask on external/internal line 36</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM37</name>
|
|
<description>Event mask on external/internal line 37</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM38</name>
|
|
<description>Event mask on external/internal line 38</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM39</name>
|
|
<description>Event mask on external/internal line 39</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM40</name>
|
|
<description>Event mask on external/internal line 40</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RTSR2</name>
|
|
<displayName>RTSR2</displayName>
|
|
<description>Rising Trigger selection register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RT32</name>
|
|
<description>Rising trigger event configuration bit of line 32</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT33</name>
|
|
<description>Rising trigger event configuration bit of line 32</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT38</name>
|
|
<description>Rising trigger event configuration bit of line 38</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT39</name>
|
|
<description>Rising trigger event configuration bit of line 39</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT40</name>
|
|
<description>Rising trigger event configuration bit of line 40</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT41</name>
|
|
<description>Rising trigger event configuration bit of line 41</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTSR2</name>
|
|
<displayName>FTSR2</displayName>
|
|
<description>Falling Trigger selection register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FT35</name>
|
|
<description>Falling trigger event configuration bit of line 35</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT36</name>
|
|
<description>Falling trigger event configuration bit of line 36</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT37</name>
|
|
<description>Falling trigger event configuration bit of line 37</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT38</name>
|
|
<description>Falling trigger event configuration bit of line 38</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWIER2</name>
|
|
<displayName>SWIER2</displayName>
|
|
<description>Software interrupt event register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWI35</name>
|
|
<description>Software interrupt on line 35</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI36</name>
|
|
<description>Software interrupt on line 36</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI37</name>
|
|
<description>Software interrupt on line 37</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI38</name>
|
|
<description>Software interrupt on line 38</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR2</name>
|
|
<displayName>PR2</displayName>
|
|
<description>Pending register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PIF35</name>
|
|
<description>Pending interrupt flag on line 35</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF36</name>
|
|
<description>Pending interrupt flag on line 36</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF37</name>
|
|
<description>Pending interrupt flag on line 37</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PIF38</name>
|
|
<description>Pending interrupt flag on line 38</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>Real-time clock</description>
|
|
<groupName>RTC</groupName>
|
|
<baseAddress>0x40002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC_TAMP_CSS_LSE</name>
|
|
<description>RTC_TAMP_CSS_LSE</description>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>RTC_WKUP</name>
|
|
<description>RTC Wakeup timer</description>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>RTC_ALARM</name>
|
|
<description>RTC_ALARM</description>
|
|
<value>41</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TR</name>
|
|
<displayName>TR</displayName>
|
|
<description>time register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM notation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HT</name>
|
|
<description>Hour tens in BCD format</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HU</name>
|
|
<description>Hour units in BCD format</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Second tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SU</name>
|
|
<description>Second units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>date register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00002101</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>YT</name>
|
|
<description>Year tens in BCD format</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YU</name>
|
|
<description>Year units in BCD format</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDU</name>
|
|
<description>Week day units</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MT</name>
|
|
<description>Month tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MU</name>
|
|
<description>Month units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Date tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DU</name>
|
|
<description>Date units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SSR</name>
|
|
<displayName>SSR</displayName>
|
|
<description>sub second register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SS</name>
|
|
<description>Sub second value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<displayName>ICSR</displayName>
|
|
<description>initialization and status register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALRAWF</name>
|
|
<description>Alarm A write flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRBWF</name>
|
|
<description>Alarm B write flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WUTWF</name>
|
|
<description>Wakeup timer write flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SHPF</name>
|
|
<description>Shift operation pending</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INITS</name>
|
|
<description>Initialization status flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RSF</name>
|
|
<description>Registers synchronization flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INITF</name>
|
|
<description>Initialization flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>Initialization mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RECALPF</name>
|
|
<description>Recalibration pending Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRER</name>
|
|
<displayName>PRER</displayName>
|
|
<description>prescaler register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x007F00FF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PREDIV_A</name>
|
|
<description>Asynchronous prescaler factor</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREDIV_S</name>
|
|
<description>Synchronous prescaler factor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WUTR</name>
|
|
<displayName>WUTR</displayName>
|
|
<description>wakeup timer register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WUT</name>
|
|
<description>Wakeup auto-reload value bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WCKSEL</name>
|
|
<description>Wakeup clock selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEDGE</name>
|
|
<description>Time-stamp event active edge</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REFCKON</name>
|
|
<description>Reference clock detection enable (50 or 60 Hz)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BYPSHAD</name>
|
|
<description>Bypass the shadow registers</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMT</name>
|
|
<description>Hour format</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALRAE</name>
|
|
<description>Alarm A enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALRBE</name>
|
|
<description>Alarm B enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUTE</name>
|
|
<description>Wakeup timer enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSE</name>
|
|
<description>Time stamp enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALRAIE</name>
|
|
<description>Alarm A interrupt enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALRBIE</name>
|
|
<description>Alarm B interrupt enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUTIE</name>
|
|
<description>Wakeup timer interrupt enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSIE</name>
|
|
<description>Time-stamp interrupt enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADD1H</name>
|
|
<description>Add 1 hour (summer time change)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUB1H</name>
|
|
<description>Subtract 1 hour (winter time change)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>Backup</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COSEL</name>
|
|
<description>Calibration output selection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>Output polarity</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSEL</name>
|
|
<description>Output selection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COE</name>
|
|
<description>Calibration output enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITSE</name>
|
|
<description>timestamp on internal event enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPTS</name>
|
|
<description>TAMPTS</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPOE</name>
|
|
<description>TAMPOE</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPALRM_PU</name>
|
|
<description>TAMPALRM_PU</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPALRM_TYPE</name>
|
|
<description>TAMPALRM_TYPE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OUT2EN</name>
|
|
<description>OUT2EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WPR</name>
|
|
<displayName>WPR</displayName>
|
|
<description>write protection register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Write protection key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALR</name>
|
|
<displayName>CALR</displayName>
|
|
<description>calibration register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALP</name>
|
|
<description>Increase frequency of RTC by 488.5 ppm</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALW8</name>
|
|
<description>Use an 8-second calibration cycle period</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALW16</name>
|
|
<description>Use a 16-second calibration cycle period</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALM</name>
|
|
<description>Calibration minus</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHIFTR</name>
|
|
<displayName>SHIFTR</displayName>
|
|
<description>shift control register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD1S</name>
|
|
<description>Add one second</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUBFS</name>
|
|
<description>Subtract a fraction of a second</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSTR</name>
|
|
<displayName>TSTR</displayName>
|
|
<description>time stamp time register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SU</name>
|
|
<description>Second units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Second tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HU</name>
|
|
<description>Hour units in BCD format</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HT</name>
|
|
<description>Hour tens in BCD format</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM notation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSDR</name>
|
|
<displayName>TSDR</displayName>
|
|
<description>time stamp date register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDU</name>
|
|
<description>Week day units</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MT</name>
|
|
<description>Month tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MU</name>
|
|
<description>Month units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Date tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DU</name>
|
|
<description>Date units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSSSR</name>
|
|
<displayName>TSSSR</displayName>
|
|
<description>timestamp sub second register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SS</name>
|
|
<description>Sub second value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRMAR</name>
|
|
<displayName>ALRMAR</displayName>
|
|
<description>alarm A register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSK4</name>
|
|
<description>Alarm A date mask</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDSEL</name>
|
|
<description>Week day selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Date tens in BCD format</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DU</name>
|
|
<description>Date units or day in BCD format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSK3</name>
|
|
<description>Alarm A hours mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM notation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HT</name>
|
|
<description>Hour tens in BCD format</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HU</name>
|
|
<description>Hour units in BCD format</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSK2</name>
|
|
<description>Alarm A minutes mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSK1</name>
|
|
<description>Alarm A seconds mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Second tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SU</name>
|
|
<description>Second units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRMASSR</name>
|
|
<displayName>ALRMASSR</displayName>
|
|
<description>alarm A sub second register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MASKSS</name>
|
|
<description>Mask the most-significant bits starting at this bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SS</name>
|
|
<description>Sub seconds value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRMBR</name>
|
|
<displayName>ALRMBR</displayName>
|
|
<description>alarm B register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSK4</name>
|
|
<description>Alarm B date mask</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDSEL</name>
|
|
<description>Week day selection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DT</name>
|
|
<description>Date tens in BCD format</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DU</name>
|
|
<description>Date units or day in BCD format</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSK3</name>
|
|
<description>Alarm B hours mask</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PM</name>
|
|
<description>AM/PM notation</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HT</name>
|
|
<description>Hour tens in BCD format</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HU</name>
|
|
<description>Hour units in BCD format</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSK2</name>
|
|
<description>Alarm B minutes mask</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNT</name>
|
|
<description>Minute tens in BCD format</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MNU</name>
|
|
<description>Minute units in BCD format</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSK1</name>
|
|
<description>Alarm B seconds mask</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ST</name>
|
|
<description>Second tens in BCD format</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SU</name>
|
|
<description>Second units in BCD format</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRMBSSR</name>
|
|
<displayName>ALRMBSSR</displayName>
|
|
<description>alarm B sub second register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MASKSS</name>
|
|
<description>Mask the most-significant bits starting at this bit</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SS</name>
|
|
<description>Sub seconds value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>15</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALRAF</name>
|
|
<description>ALRAF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALRBF</name>
|
|
<description>ALRBF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUTF</name>
|
|
<description>WUTF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSF</name>
|
|
<description>TSF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSOVF</name>
|
|
<description>TSOVF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITSF</name>
|
|
<description>ITSF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISR</name>
|
|
<displayName>MISR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALRAMF</name>
|
|
<description>ALRAMF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALRBMF</name>
|
|
<description>ALRBMF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUTMF</name>
|
|
<description>WUTMF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSMF</name>
|
|
<description>TSMF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSOVMF</name>
|
|
<description>TSOVMF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITSMF</name>
|
|
<description>ITSMF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<displayName>SCR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALRAF</name>
|
|
<description>CALRAF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALRBF</name>
|
|
<description>CALRBF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CWUTF</name>
|
|
<description>CWUTF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSF</name>
|
|
<description>CTSF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSOVF</name>
|
|
<description>CTSOVF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITSF</name>
|
|
<description>CITSF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FMC</name>
|
|
<description>Flexible memory controller</description>
|
|
<groupName>FMC</groupName>
|
|
<baseAddress>0xA0000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FMC</name>
|
|
<description>FMC</description>
|
|
<value>48</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BCR1</name>
|
|
<displayName>BCR1</displayName>
|
|
<description>SRAM/NOR-Flash chip-select control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>MBKEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>MUXEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>MTYP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>MWID</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>FACCEN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>BURSTEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>WAITPOL</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>WAITCFG</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>WREN</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAITEN</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>EXTMOD</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>ASYNCWAIT</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CPSIZE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>CBURSTRW</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>CCLKEN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>WFDIS</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBLSET</name>
|
|
<description>NBLSET</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR1</name>
|
|
<displayName>BTR1</displayName>
|
|
<description>SRAM/NOR-Flash chip-select timing register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>DATLAT</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>CLKDIV</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR2</name>
|
|
<displayName>BCR2</displayName>
|
|
<description>SRAM/NOR-Flash chip-select control register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>MBKEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>MUXEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>MTYP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>MWID</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>FACCEN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>BURSTEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>WAITPOL</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>WAITCFG</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>WREN</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAITEN</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>EXTMOD</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>ASYNCWAIT</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CPSIZE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>CBURSTRW</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>CCLKEN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>WFDIS</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBLSET</name>
|
|
<description>NBLSET</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR2</name>
|
|
<displayName>BTR2</displayName>
|
|
<description>SRAM/NOR-Flash chip-select timing register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>DATLAT</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>CLKDIV</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR3</name>
|
|
<displayName>BCR3</displayName>
|
|
<description>SRAM/NOR-Flash chip-select control register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>MBKEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>MUXEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>MTYP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>MWID</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>FACCEN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>BURSTEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>WAITPOL</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>WAITCFG</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>WREN</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAITEN</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>EXTMOD</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>ASYNCWAIT</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CPSIZE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>CBURSTRW</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>CCLKEN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>WFDIS</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBLSET</name>
|
|
<description>NBLSET</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR3</name>
|
|
<displayName>BTR3</displayName>
|
|
<description>SRAM/NOR-Flash chip-select timing register 3</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>DATLAT</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>CLKDIV</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR4</name>
|
|
<displayName>BCR4</displayName>
|
|
<description>SRAM/NOR-Flash chip-select control register 4</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000030D0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MBKEN</name>
|
|
<description>MBKEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUXEN</name>
|
|
<description>MUXEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTYP</name>
|
|
<description>MTYP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MWID</name>
|
|
<description>MWID</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FACCEN</name>
|
|
<description>FACCEN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BURSTEN</name>
|
|
<description>BURSTEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITPOL</name>
|
|
<description>WAITPOL</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITCFG</name>
|
|
<description>WAITCFG</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WREN</name>
|
|
<description>WREN</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAITEN</name>
|
|
<description>WAITEN</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTMOD</name>
|
|
<description>EXTMOD</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASYNCWAIT</name>
|
|
<description>ASYNCWAIT</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPSIZE</name>
|
|
<description>CPSIZE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CBURSTRW</name>
|
|
<description>CBURSTRW</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCLKEN</name>
|
|
<description>CCLKEN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WFDIS</name>
|
|
<description>WFDIS</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBLSET</name>
|
|
<description>NBLSET</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTR4</name>
|
|
<displayName>BTR4</displayName>
|
|
<description>SRAM/NOR-Flash chip-select timing register 4</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATLAT</name>
|
|
<description>DATLAT</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKDIV</name>
|
|
<description>CLKDIV</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCSCNTR</name>
|
|
<displayName>PCSCNTR</displayName>
|
|
<description>PSRAM chip select counter register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSCOUNT</name>
|
|
<description>CSCOUNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTB1EN</name>
|
|
<description>CNTB1EN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTB2EN</name>
|
|
<description>CNTB2EN</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTB3EN</name>
|
|
<description>CNTB3EN</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTB4EN</name>
|
|
<description>CNTB4EN</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCR</name>
|
|
<displayName>PCR</displayName>
|
|
<description>PC Card/NAND Flash control register 3</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000018</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCPS</name>
|
|
<description>ECCPS</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAR</name>
|
|
<description>TAR</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCLR</name>
|
|
<description>TCLR</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCEN</name>
|
|
<description>ECCEN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWID</name>
|
|
<description>PWID</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PTYP</name>
|
|
<description>PTYP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PBKEN</name>
|
|
<description>PBKEN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWAITEN</name>
|
|
<description>PWAITEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>FIFO status and interrupt register 3</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FEMPT</name>
|
|
<description>FEMPT</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IFEN</name>
|
|
<description>IFEN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ILEN</name>
|
|
<description>ILEN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>IREN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IFS</name>
|
|
<description>IFS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ILS</name>
|
|
<description>ILS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRS</name>
|
|
<description>IRS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PMEM</name>
|
|
<displayName>PMEM</displayName>
|
|
<description>Common memory space timing register 3</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MEMHIZx</name>
|
|
<description>MEMHIZx</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMHOLDx</name>
|
|
<description>MEMHOLDx</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMWAITx</name>
|
|
<description>MEMWAITx</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMSETx</name>
|
|
<description>MEMSETx</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PATT</name>
|
|
<displayName>PATT</displayName>
|
|
<description>Attribute memory space timing register 3</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFCFCFCFC</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ATTHIZx</name>
|
|
<description>ATTHIZx</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTHOLDx</name>
|
|
<description>ATTHOLDx</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTWAITx</name>
|
|
<description>ATTWAITx</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ATTSETx</name>
|
|
<description>ATTSETx</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECCR</name>
|
|
<displayName>ECCR</displayName>
|
|
<description>ECC result register 3</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ECCx</name>
|
|
<description>ECCx</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR1</name>
|
|
<displayName>BWTR1</displayName>
|
|
<description>SRAM/NOR-Flash write timing registers 1</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR2</name>
|
|
<displayName>BWTR2</displayName>
|
|
<description>SRAM/NOR-Flash write timing registers 2</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR3</name>
|
|
<displayName>BWTR3</displayName>
|
|
<description>SRAM/NOR-Flash write timing registers 3</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BWTR4</name>
|
|
<displayName>BWTR4</displayName>
|
|
<description>SRAM/NOR-Flash write timing registers 4</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATAHLD</name>
|
|
<description>DATAHLD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACCMOD</name>
|
|
<description>ACCMOD</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSTURN</name>
|
|
<description>BUSTURN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DATAST</name>
|
|
<description>DATAST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDHLD</name>
|
|
<description>ADDHLD</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDSET</name>
|
|
<description>ADDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA1</name>
|
|
<description>DMA controller</description>
|
|
<groupName>DMA</groupName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA1_CH1</name>
|
|
<description>DMA1 channel 1 interrupt</description>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_CH2</name>
|
|
<description>DMA1 channel 2 interrupt</description>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_CH3</name>
|
|
<description>DMA1 channel 3 interrupt</description>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_CH4</name>
|
|
<description>DMA1 channel 4 interrupt</description>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_CH5</name>
|
|
<description>DMA1 channel 5 interrupt</description>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_CH6</name>
|
|
<description>DMA1 channel 6 interrupt</description>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_CH8</name>
|
|
<description>DMA1_CH8</description>
|
|
<value>96</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>interrupt status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF8</name>
|
|
<description>TEIF8</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF8</name>
|
|
<description>HTIF8</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF8</name>
|
|
<description>TCIF8</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF8</name>
|
|
<description>GIF8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF7</name>
|
|
<description>TEIF7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF7</name>
|
|
<description>HTIF7</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF7</name>
|
|
<description>TCIF7</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF7</name>
|
|
<description>GIF7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF6</name>
|
|
<description>TEIF6</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF6</name>
|
|
<description>HTIF6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF6</name>
|
|
<description>TCIF6</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF6</name>
|
|
<description>GIF6</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF5</name>
|
|
<description>TEIF5</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF5</name>
|
|
<description>HTIF5</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF5</name>
|
|
<description>TCIF5</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF5</name>
|
|
<description>GIF5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF4</name>
|
|
<description>TEIF4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF4</name>
|
|
<description>HTIF4</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF4</name>
|
|
<description>TCIF4</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF4</name>
|
|
<description>GIF4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF3</name>
|
|
<description>TEIF3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF3</name>
|
|
<description>HTIF3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF3</name>
|
|
<description>TCIF3</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF3</name>
|
|
<description>GIF3</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF2</name>
|
|
<description>TEIF2</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF2</name>
|
|
<description>HTIF2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF2</name>
|
|
<description>TCIF2</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF2</name>
|
|
<description>GIF2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF1</name>
|
|
<description>TEIF1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF1</name>
|
|
<description>HTIF1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF1</name>
|
|
<description>TCIF1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF1</name>
|
|
<description>GIF1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFCR</name>
|
|
<displayName>IFCR</displayName>
|
|
<description>DMA interrupt flag clear register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEIF8</name>
|
|
<description>TEIF8</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF8</name>
|
|
<description>HTIF8</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF8</name>
|
|
<description>TCIF8</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF8</name>
|
|
<description>GIF8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF7</name>
|
|
<description>TEIF7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF7</name>
|
|
<description>HTIF7</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF7</name>
|
|
<description>TCIF7</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF7</name>
|
|
<description>GIF7</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF6</name>
|
|
<description>TEIF6</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF6</name>
|
|
<description>HTIF6</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF6</name>
|
|
<description>TCIF6</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF6</name>
|
|
<description>GIF6</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF5</name>
|
|
<description>TEIF5</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF5</name>
|
|
<description>HTIF5</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF5</name>
|
|
<description>TCIF5</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF5</name>
|
|
<description>GIF5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF4</name>
|
|
<description>TEIF4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF4</name>
|
|
<description>HTIF4</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF4</name>
|
|
<description>TCIF4</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF4</name>
|
|
<description>GIF4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF3</name>
|
|
<description>TEIF3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF3</name>
|
|
<description>HTIF3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF3</name>
|
|
<description>TCIF3</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF3</name>
|
|
<description>GIF3</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF2</name>
|
|
<description>TEIF2</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF2</name>
|
|
<description>HTIF2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF2</name>
|
|
<description>TCIF2</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF2</name>
|
|
<description>GIF2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIF1</name>
|
|
<description>TEIF1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIF1</name>
|
|
<description>HTIF1</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIF1</name>
|
|
<description>TCIF1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GIF1</name>
|
|
<description>GIF1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<displayName>CCR1</displayName>
|
|
<description>DMA channel 1 configuration register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<displayName>CCR2</displayName>
|
|
<description>DMA channel 2 configuration register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<displayName>CCR3</displayName>
|
|
<description>DMA channel 3 configuration register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<displayName>CCR4</displayName>
|
|
<description>DMA channel 3 configuration register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR5</name>
|
|
<displayName>CCR5</displayName>
|
|
<description>DMA channel 4 configuration register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR6</name>
|
|
<displayName>CCR6</displayName>
|
|
<description>DMA channel 5 configuration register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR7</name>
|
|
<displayName>CCR7</displayName>
|
|
<description>DMA channel 6 configuration register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR8</name>
|
|
<displayName>CCR8</displayName>
|
|
<description>DMA channel 7 configuration register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>channel enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>TCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>HTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>TEIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>CIRC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>PINC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>MINC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>PSIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>MSIZE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>PL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>MEM2MEM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR1</name>
|
|
<displayName>CNDTR1</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR2</name>
|
|
<displayName>CNDTR2</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR3</name>
|
|
<displayName>CNDTR3</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR4</name>
|
|
<displayName>CNDTR4</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR5</name>
|
|
<displayName>CNDTR5</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR6</name>
|
|
<displayName>CNDTR6</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR7</name>
|
|
<displayName>CNDTR7</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR8</name>
|
|
<displayName>CNDTR8</displayName>
|
|
<description>channel x number of data to transfer register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>Number of data items to transfer</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR1</name>
|
|
<displayName>CPAR1</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR2</name>
|
|
<displayName>CPAR2</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR3</name>
|
|
<displayName>CPAR3</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR4</name>
|
|
<displayName>CPAR4</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR5</name>
|
|
<displayName>CPAR5</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR6</name>
|
|
<displayName>CPAR6</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR7</name>
|
|
<displayName>CPAR7</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR8</name>
|
|
<displayName>CPAR8</displayName>
|
|
<description>DMA channel x peripheral address register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>Peripheral address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR1</name>
|
|
<displayName>CMAR1</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR2</name>
|
|
<displayName>CMAR2</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR3</name>
|
|
<displayName>CMAR3</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR4</name>
|
|
<displayName>CMAR4</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR5</name>
|
|
<displayName>CMAR5</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR6</name>
|
|
<displayName>CMAR6</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR7</name>
|
|
<displayName>CMAR7</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR8</name>
|
|
<displayName>CMAR8</displayName>
|
|
<description>DMA channel x memory address register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>Memory 1 address (used in case of Double buffer mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DMA1">
|
|
<name>DMA2</name>
|
|
<baseAddress>0x40020400</baseAddress>
|
|
<interrupt>
|
|
<name>DMA1_CH7</name>
|
|
<description>DMA1 channel 7 interrupt</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH1</name>
|
|
<description>DMA2_CH1</description>
|
|
<value>56</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH2</name>
|
|
<description>DMA2_CH2</description>
|
|
<value>57</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH3</name>
|
|
<description>DMA2_CH3</description>
|
|
<value>58</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH4</name>
|
|
<description>DMA2_CH4</description>
|
|
<value>59</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH5</name>
|
|
<description>DMA2_CH5</description>
|
|
<value>60</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH6</name>
|
|
<description>DMA2_CH6</description>
|
|
<value>97</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH7</name>
|
|
<description>DMA2_CH7</description>
|
|
<value>98</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA2_CH8</name>
|
|
<description>DMA2_CH8</description>
|
|
<value>99</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMAMUX</name>
|
|
<description>DMAMUX</description>
|
|
<groupName>DMAMUX</groupName>
|
|
<baseAddress>0x40020800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMAMUX_OVR</name>
|
|
<description>DMAMUX_OVR</description>
|
|
<value>94</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>C0CR</name>
|
|
<displayName>C0CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C1CR</name>
|
|
<displayName>C1CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C2CR</name>
|
|
<displayName>C2CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C3CR</name>
|
|
<displayName>C3CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C4CR</name>
|
|
<displayName>C4CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C5CR</name>
|
|
<displayName>C5CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C6CR</name>
|
|
<displayName>C6CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C7CR</name>
|
|
<displayName>C7CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C8CR</name>
|
|
<displayName>C8CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C9CR</name>
|
|
<displayName>C9CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C10CR</name>
|
|
<displayName>C10CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C11CR</name>
|
|
<displayName>C11CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C12CR</name>
|
|
<displayName>C12CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C13CR</name>
|
|
<displayName>C13CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C14CR</name>
|
|
<displayName>C14CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>C15CR</name>
|
|
<displayName>C15CR</displayName>
|
|
<description>DMAMux - DMA request line multiplexer channel x control register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAREQ_ID</name>
|
|
<description>Input DMA request line selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOIE</name>
|
|
<description>Interrupt enable at synchronization event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EGE</name>
|
|
<description>Event generation enable/disable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SE</name>
|
|
<description>Synchronous operating mode enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPOL</name>
|
|
<description>Synchronization event type selector Defines the synchronization event on the selected synchronization input:</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBREQ</name>
|
|
<description>Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_ID</name>
|
|
<description>Synchronization input selected</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG0CR</name>
|
|
<displayName>RG0CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x control register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG1CR</name>
|
|
<displayName>RG1CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x control register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG2CR</name>
|
|
<displayName>RG2CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x control register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RG3CR</name>
|
|
<displayName>RG3CR</displayName>
|
|
<description>DMAMux - DMA request generator channel x control register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SIG_ID</name>
|
|
<description>DMA request trigger input selected</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OIE</name>
|
|
<description>Interrupt enable at trigger event overrun</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GE</name>
|
|
<description>DMA request generator channel enable/disable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPOL</name>
|
|
<description>DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GNBREQ</name>
|
|
<description>Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RGSR</name>
|
|
<displayName>RGSR</displayName>
|
|
<description>DMAMux - DMA request generator status register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OF</name>
|
|
<description>Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RGCFR</name>
|
|
<displayName>RGCFR</displayName>
|
|
<description>DMAMux - DMA request generator clear flag register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COF</name>
|
|
<description>Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>DMAMUX request line multiplexer interrupt channel status register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>Synchronization overrun event flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFR</name>
|
|
<displayName>CFR</displayName>
|
|
<description>DMAMUX request line multiplexer interrupt clear flag register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CSOF</name>
|
|
<description>Clear synchronization overrun event flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCFG</name>
|
|
<description>System configuration controller</description>
|
|
<groupName>SYSCFG</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x2A</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MEMRMP</name>
|
|
<displayName>MEMRMP</displayName>
|
|
<description>Remap Memory register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MEM_MODE</name>
|
|
<description>Memory mapping selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FB_mode</name>
|
|
<description>User Flash Bank mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR1</name>
|
|
<displayName>CFGR1</displayName>
|
|
<description>peripheral mode configuration register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7C000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOOSTEN</name>
|
|
<description>BOOSTEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANASWVDD</name>
|
|
<description>GPIO analog switch control voltage selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C_PB6_FMP</name>
|
|
<description>FM+ drive capability on PB6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C_PB7_FMP</name>
|
|
<description>FM+ drive capability on PB6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C_PB8_FMP</name>
|
|
<description>FM+ drive capability on PB6</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C_PB9_FMP</name>
|
|
<description>FM+ drive capability on PB6</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1_FMP</name>
|
|
<description>I2C1 FM+ drive capability enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2_FMP</name>
|
|
<description>I2C1 FM+ drive capability enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C3_FMP</name>
|
|
<description>I2C1 FM+ drive capability enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C4_FMP</name>
|
|
<description>I2C1 FM+ drive capability enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FPU_IE</name>
|
|
<description>FPU Interrupts Enable</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR1</name>
|
|
<displayName>EXTICR1</displayName>
|
|
<description>external interrupt configuration register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI3</name>
|
|
<description>EXTI x configuration (x = 0 to 3)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI2</name>
|
|
<description>EXTI x configuration (x = 0 to 3)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI1</name>
|
|
<description>EXTI x configuration (x = 0 to 3)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI0</name>
|
|
<description>EXTI x configuration (x = 0 to 3)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR2</name>
|
|
<displayName>EXTICR2</displayName>
|
|
<description>external interrupt configuration register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI7</name>
|
|
<description>EXTI x configuration (x = 4 to 7)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI6</name>
|
|
<description>EXTI x configuration (x = 4 to 7)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI5</name>
|
|
<description>EXTI x configuration (x = 4 to 7)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI4</name>
|
|
<description>EXTI x configuration (x = 4 to 7)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR3</name>
|
|
<displayName>EXTICR3</displayName>
|
|
<description>external interrupt configuration register 3</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI11</name>
|
|
<description>EXTI x configuration (x = 8 to 11)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI10</name>
|
|
<description>EXTI10</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI9</name>
|
|
<description>EXTI x configuration (x = 8 to 11)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI8</name>
|
|
<description>EXTI x configuration (x = 8 to 11)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR4</name>
|
|
<displayName>EXTICR4</displayName>
|
|
<description>external interrupt configuration register 4</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI15</name>
|
|
<description>EXTI x configuration (x = 12 to 15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI14</name>
|
|
<description>EXTI x configuration (x = 12 to 15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI13</name>
|
|
<description>EXTI x configuration (x = 12 to 15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI12</name>
|
|
<description>EXTI x configuration (x = 12 to 15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCSR</name>
|
|
<displayName>SCSR</displayName>
|
|
<description>CCM SRAM control and status register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCMER</name>
|
|
<description>CCM SRAM Erase</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCMBSY</name>
|
|
<description>CCM SRAM busy by erase operation</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR2</name>
|
|
<displayName>CFGR2</displayName>
|
|
<description>configuration register 2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLL</name>
|
|
<description>Core Lockup Lock</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPL</name>
|
|
<description>SRAM Parity Lock</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVDL</name>
|
|
<description>PVD Lock</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ECCL</name>
|
|
<description>ECC Lock</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPF</name>
|
|
<description>SRAM Parity Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWPR</name>
|
|
<displayName>SWPR</displayName>
|
|
<description>SRAM Write protection register 1</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>Page0_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page1_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page2_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page3_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page4_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page5_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page6_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page7_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page8_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page9_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page10_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page11_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page12_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page13_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page14_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page15_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page16_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page17_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page18_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page19_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page20_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page21_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page22_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page23_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page24_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page25_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page26_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page27_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page28_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page29_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page30_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Page31_WP</name>
|
|
<description>Write protection</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SKR</name>
|
|
<displayName>SKR</displayName>
|
|
<description>SRAM2 Key Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>SRAM2 Key for software erase</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>VREFBUF</name>
|
|
<description>Voltage reference buffer</description>
|
|
<groupName>VREFBUF</groupName>
|
|
<baseAddress>0x40010030</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x1D0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>VREFBUF_CSR</name>
|
|
<displayName>VREFBUF_CSR</displayName>
|
|
<description>VREF_BUF Control and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENVR</name>
|
|
<description>Enable Voltage Reference</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HIZ</name>
|
|
<description>High impedence mode for the VREF_BUF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VRR</name>
|
|
<description>Voltage reference buffer ready</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VRS</name>
|
|
<description>Voltage reference scale</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VREFBUF_CCR</name>
|
|
<displayName>VREFBUF_CCR</displayName>
|
|
<description>VREF_BUF Calibration Control Register</description>
|
|
<addressOffset>0x04</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRIM</name>
|
|
<description>Trimming code</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP</name>
|
|
<description>Comparator control and status register</description>
|
|
<groupName>COMP</groupName>
|
|
<baseAddress>0x40010200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>COMP1_2_3</name>
|
|
<description>COMP1_2_3</description>
|
|
<value>64</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>COMP4_5_6</name>
|
|
<description>COMP4_5_6</description>
|
|
<value>65</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>COMP7</name>
|
|
<description>COMP7</description>
|
|
<value>66</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>COMP_C1CSR</name>
|
|
<displayName>COMP_C1CSR</displayName>
|
|
<description>Comparator control/status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP_DEGLITCH_EN</name>
|
|
<description>COMP_DEGLITCH_EN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>INMSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>INPSEL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>POL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>HYST</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLANKSEL</name>
|
|
<description>BLANKSEL</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRGEN</name>
|
|
<description>BRGEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCALEN</name>
|
|
<description>SCALEN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP_C2CSR</name>
|
|
<displayName>COMP_C2CSR</displayName>
|
|
<description>Comparator control/status register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP_DEGLITCH_EN</name>
|
|
<description>COMP_DEGLITCH_EN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>INMSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>INPSEL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>POL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>HYST</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLANKSEL</name>
|
|
<description>BLANKSEL</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRGEN</name>
|
|
<description>BRGEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCALEN</name>
|
|
<description>SCALEN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP_C3CSR</name>
|
|
<displayName>COMP_C3CSR</displayName>
|
|
<description>Comparator control/status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP_DEGLITCH_EN</name>
|
|
<description>COMP_DEGLITCH_EN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>INMSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>INPSEL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>POL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>HYST</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLANKSEL</name>
|
|
<description>BLANKSEL</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRGEN</name>
|
|
<description>BRGEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCALEN</name>
|
|
<description>SCALEN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP_C4CSR</name>
|
|
<displayName>COMP_C4CSR</displayName>
|
|
<description>Comparator control/status register</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP_DEGLITCH_EN</name>
|
|
<description>COMP_DEGLITCH_EN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>INMSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>INPSEL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>POL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>HYST</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLANKSEL</name>
|
|
<description>BLANKSEL</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRGEN</name>
|
|
<description>BRGEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCALEN</name>
|
|
<description>SCALEN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP_C5CSR</name>
|
|
<displayName>COMP_C5CSR</displayName>
|
|
<description>Comparator control/status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP_DEGLITCH_EN</name>
|
|
<description>COMP_DEGLITCH_EN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>INMSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>INPSEL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>POL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>HYST</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLANKSEL</name>
|
|
<description>BLANKSEL</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRGEN</name>
|
|
<description>BRGEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCALEN</name>
|
|
<description>SCALEN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP_C6CSR</name>
|
|
<displayName>COMP_C6CSR</displayName>
|
|
<description>Comparator control/status register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP_DEGLITCH_EN</name>
|
|
<description>COMP_DEGLITCH_EN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>INMSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>INPSEL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>POL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>HYST</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLANKSEL</name>
|
|
<description>BLANKSEL</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRGEN</name>
|
|
<description>BRGEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCALEN</name>
|
|
<description>SCALEN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>COMP_C7CSR</name>
|
|
<displayName>COMP_C7CSR</displayName>
|
|
<description>Comparator control/status register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP_DEGLITCH_EN</name>
|
|
<description>COMP_DEGLITCH_EN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>INMSEL</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>INPSEL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POL</name>
|
|
<description>POL</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>HYST</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BLANKSEL</name>
|
|
<description>BLANKSEL</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRGEN</name>
|
|
<description>BRGEN</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCALEN</name>
|
|
<description>SCALEN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>VALUE</name>
|
|
<description>VALUE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OPAMP</name>
|
|
<description>Operational amplifiers</description>
|
|
<groupName>OPAMP</groupName>
|
|
<baseAddress>0x40010300</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x100</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>OPAMP1_CSR</name>
|
|
<displayName>OPAMP1_CSR</displayName>
|
|
<description>OPAMP1 control/status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPAEN</name>
|
|
<description>Operational amplifier Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_VP</name>
|
|
<description>FORCE_VP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VP_SEL</name>
|
|
<description>VP_SEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERTRIM</name>
|
|
<description>USERTRIM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VM_SEL</name>
|
|
<description>VM_SEL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAHSM</name>
|
|
<description>OPAHSM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAINTOEN</name>
|
|
<description>OPAINTOEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALON</name>
|
|
<description>CALON</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALSEL</name>
|
|
<description>CALSEL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGA_GAIN</name>
|
|
<description>PGA_GAIN</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETP</name>
|
|
<description>TRIMOFFSETP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETN</name>
|
|
<description>TRIMOFFSETN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALOUT</name>
|
|
<description>CALOUT</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP2_CSR</name>
|
|
<displayName>OPAMP2_CSR</displayName>
|
|
<description>OPAMP2 control/status register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPAEN</name>
|
|
<description>Operational amplifier Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_VP</name>
|
|
<description>FORCE_VP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VP_SEL</name>
|
|
<description>VP_SEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERTRIM</name>
|
|
<description>USERTRIM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VM_SEL</name>
|
|
<description>VM_SEL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAHSM</name>
|
|
<description>OPAHSM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAINTOEN</name>
|
|
<description>OPAINTOEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALON</name>
|
|
<description>CALON</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALSEL</name>
|
|
<description>CALSEL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGA_GAIN</name>
|
|
<description>PGA_GAIN</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETP</name>
|
|
<description>TRIMOFFSETP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETN</name>
|
|
<description>TRIMOFFSETN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALOUT</name>
|
|
<description>CALOUT</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP3_CSR</name>
|
|
<displayName>OPAMP3_CSR</displayName>
|
|
<description>OPAMP3 control/status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPAEN</name>
|
|
<description>Operational amplifier Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_VP</name>
|
|
<description>FORCE_VP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VP_SEL</name>
|
|
<description>VP_SEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERTRIM</name>
|
|
<description>USERTRIM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VM_SEL</name>
|
|
<description>VM_SEL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAHSM</name>
|
|
<description>OPAHSM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAINTOEN</name>
|
|
<description>OPAINTOEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALON</name>
|
|
<description>CALON</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALSEL</name>
|
|
<description>CALSEL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGA_GAIN</name>
|
|
<description>PGA_GAIN</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETP</name>
|
|
<description>TRIMOFFSETP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETN</name>
|
|
<description>TRIMOFFSETN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALOUT</name>
|
|
<description>CALOUT</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP4_CSR</name>
|
|
<displayName>OPAMP4_CSR</displayName>
|
|
<description>OPAMP4 control/status register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPAEN</name>
|
|
<description>Operational amplifier Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_VP</name>
|
|
<description>FORCE_VP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VP_SEL</name>
|
|
<description>VP_SEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERTRIM</name>
|
|
<description>USERTRIM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VM_SEL</name>
|
|
<description>VM_SEL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAHSM</name>
|
|
<description>OPAHSM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAINTOEN</name>
|
|
<description>OPAINTOEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALON</name>
|
|
<description>CALON</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALSEL</name>
|
|
<description>CALSEL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGA_GAIN</name>
|
|
<description>PGA_GAIN</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETP</name>
|
|
<description>TRIMOFFSETP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETN</name>
|
|
<description>TRIMOFFSETN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALOUT</name>
|
|
<description>CALOUT</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP5_CSR</name>
|
|
<displayName>OPAMP5_CSR</displayName>
|
|
<description>OPAMP5 control/status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPAEN</name>
|
|
<description>Operational amplifier Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_VP</name>
|
|
<description>FORCE_VP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VP_SEL</name>
|
|
<description>VP_SEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERTRIM</name>
|
|
<description>USERTRIM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VM_SEL</name>
|
|
<description>VM_SEL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAHSM</name>
|
|
<description>OPAHSM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAINTOEN</name>
|
|
<description>OPAINTOEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALON</name>
|
|
<description>CALON</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALSEL</name>
|
|
<description>CALSEL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGA_GAIN</name>
|
|
<description>PGA_GAIN</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETP</name>
|
|
<description>TRIMOFFSETP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETN</name>
|
|
<description>TRIMOFFSETN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALOUT</name>
|
|
<description>CALOUT</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP6_CSR</name>
|
|
<displayName>OPAMP6_CSR</displayName>
|
|
<description>OPAMP6 control/status register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPAEN</name>
|
|
<description>Operational amplifier Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCE_VP</name>
|
|
<description>FORCE_VP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VP_SEL</name>
|
|
<description>VP_SEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERTRIM</name>
|
|
<description>USERTRIM</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VM_SEL</name>
|
|
<description>VM_SEL</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAHSM</name>
|
|
<description>OPAHSM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPAINTOEN</name>
|
|
<description>OPAINTOEN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALON</name>
|
|
<description>CALON</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALSEL</name>
|
|
<description>CALSEL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGA_GAIN</name>
|
|
<description>PGA_GAIN</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETP</name>
|
|
<description>TRIMOFFSETP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOFFSETN</name>
|
|
<description>TRIMOFFSETN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALOUT</name>
|
|
<description>CALOUT</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP1_TCMR</name>
|
|
<displayName>OPAMP1_TCMR</displayName>
|
|
<description>OPAMP1 control/status register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VMS_SEL</name>
|
|
<description>VMS_SEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPS_SEL</name>
|
|
<description>VPS_SEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1CM_EN</name>
|
|
<description>T1CM_EN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T8CM_EN</name>
|
|
<description>T8CM_EN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T20CM_EN</name>
|
|
<description>T20CM_EN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP2_TCMR</name>
|
|
<displayName>OPAMP2_TCMR</displayName>
|
|
<description>OPAMP2 control/status register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VMS_SEL</name>
|
|
<description>VMS_SEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPS_SEL</name>
|
|
<description>VPS_SEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1CM_EN</name>
|
|
<description>T1CM_EN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T8CM_EN</name>
|
|
<description>T8CM_EN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T20CM_EN</name>
|
|
<description>T20CM_EN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP3_TCMR</name>
|
|
<displayName>OPAMP3_TCMR</displayName>
|
|
<description>OPAMP3 control/status register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VMS_SEL</name>
|
|
<description>VMS_SEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPS_SEL</name>
|
|
<description>VPS_SEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1CM_EN</name>
|
|
<description>T1CM_EN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T8CM_EN</name>
|
|
<description>T8CM_EN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T20CM_EN</name>
|
|
<description>T20CM_EN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP4_TCMR</name>
|
|
<displayName>OPAMP4_TCMR</displayName>
|
|
<description>OPAMP4 control/status register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VMS_SEL</name>
|
|
<description>VMS_SEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPS_SEL</name>
|
|
<description>VPS_SEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1CM_EN</name>
|
|
<description>T1CM_EN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T8CM_EN</name>
|
|
<description>T8CM_EN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T20CM_EN</name>
|
|
<description>T20CM_EN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP5_TCMR</name>
|
|
<displayName>OPAMP5_TCMR</displayName>
|
|
<description>OPAMP5 control/status register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VMS_SEL</name>
|
|
<description>VMS_SEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPS_SEL</name>
|
|
<description>VPS_SEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1CM_EN</name>
|
|
<description>T1CM_EN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T8CM_EN</name>
|
|
<description>T8CM_EN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T20CM_EN</name>
|
|
<description>T20CM_EN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
|
|
<register>
|
|
<name>OPAMP6_TCMR</name>
|
|
<displayName>OPAMP6_TCMR</displayName>
|
|
<description>OPAMP6 control/status register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VMS_SEL</name>
|
|
<description>VMS_SEL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VPS_SEL</name>
|
|
<description>VPS_SEL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T1CM_EN</name>
|
|
<description>T1CM_EN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T8CM_EN</name>
|
|
<description>T8CM_EN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>T20CM_EN</name>
|
|
<description>T20CM_EN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>LOCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_Master</name>
|
|
<description>High Resolution Timer: Master Timers</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HRTIM_Master_IRQn</name>
|
|
<description>HRTIM_Master_IRQn</description>
|
|
<value>67</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>MCR</name>
|
|
<displayName>MCR</displayName>
|
|
<description>Master Timer Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BRSTDMA</name>
|
|
<description>Burst DMA Update</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MREPU</name>
|
|
<description>Master Timer Repetition update</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREEN</name>
|
|
<description>Preload enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSYNC</name>
|
|
<description>AC Synchronization</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCEN</name>
|
|
<description>Timer F counter enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECEN</name>
|
|
<description>Timer E counter enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCEN</name>
|
|
<description>Timer D counter enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCEN</name>
|
|
<description>Timer C counter enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCEN</name>
|
|
<description>Timer B counter enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACEN</name>
|
|
<description>Timer A counter enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCEN</name>
|
|
<description>Master Counter enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_SRC</name>
|
|
<description>Synchronization source</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_OUT</name>
|
|
<description>Synchronization output</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSTRTM</name>
|
|
<description>Synchronization Starts Master</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCRSTM</name>
|
|
<description>Synchronization Resets Master</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC_IN</name>
|
|
<description>synchronization input</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTLVD</name>
|
|
<description>Interleaved mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETRIG</name>
|
|
<description>Master Re-triggerable mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Master Continuous mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CK_PSC</name>
|
|
<description>HRTIM Master Clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISR</name>
|
|
<displayName>MISR</displayName>
|
|
<description>Master Timer Interrupt Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MUPD</name>
|
|
<description>Master Update Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNC</name>
|
|
<description>Sync Input Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MREP</name>
|
|
<description>Master Repetition Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP4</name>
|
|
<description>Master Compare 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP3</name>
|
|
<description>Master Compare 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP2</name>
|
|
<description>Master Compare 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP1</name>
|
|
<description>Master Compare 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MICR</name>
|
|
<displayName>MICR</displayName>
|
|
<description>Master Timer Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MUPDC</name>
|
|
<description>Master update Interrupt flag clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCC</name>
|
|
<description>Sync Input Interrupt flag clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MREPC</name>
|
|
<description>Repetition Interrupt flag clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP4C</name>
|
|
<description>Master Compare 4 Interrupt flag clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP3C</name>
|
|
<description>Master Compare 3 Interrupt flag clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP2C</name>
|
|
<description>Master Compare 2 Interrupt flag clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP1C</name>
|
|
<description>Master Compare 1 Interrupt flag clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MDIER</name>
|
|
<displayName>MDIER</displayName>
|
|
<description>HRTIM Master Timer DMA / Interrupt Enable Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MUPDDE</name>
|
|
<description>MUPDDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCDE</name>
|
|
<description>SYNCDE</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MREPDE</name>
|
|
<description>MREPDE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP4DE</name>
|
|
<description>MCMP4DE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP3DE</name>
|
|
<description>MCMP3DE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP2DE</name>
|
|
<description>MCMP2DE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP1DE</name>
|
|
<description>MCMP1DE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUPDIE</name>
|
|
<description>MUPDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCIE</name>
|
|
<description>SYNCIE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MREPIE</name>
|
|
<description>MREPIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP4IE</name>
|
|
<description>MCMP4IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP3IE</name>
|
|
<description>MCMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP2IE</name>
|
|
<description>MCMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP1IE</name>
|
|
<description>MCMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCNTR</name>
|
|
<displayName>MCNTR</displayName>
|
|
<description>Master Timer Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MPER</name>
|
|
<displayName>MPER</displayName>
|
|
<description>Master Timer Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MPER</name>
|
|
<description>Master Timer Period value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MREP</name>
|
|
<displayName>MREP</displayName>
|
|
<description>Master Timer Repetition Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MREP</name>
|
|
<description>Master Timer Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCMP1R</name>
|
|
<displayName>MCMP1R</displayName>
|
|
<description>Master Timer Compare 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCMP1</name>
|
|
<description>Master Timer Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCMP2R</name>
|
|
<displayName>MCMP2R</displayName>
|
|
<description>Master Timer Compare 2 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCMP2</name>
|
|
<description>Master Timer Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCMP3R</name>
|
|
<displayName>MCMP3R</displayName>
|
|
<description>Master Timer Compare 3 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCMP3</name>
|
|
<description>Master Timer Compare 3 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCMP4R</name>
|
|
<displayName>MCMP4R</displayName>
|
|
<description>Master Timer Compare 4 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCMP4</name>
|
|
<description>Master Timer Compare 4 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_TIMA</name>
|
|
<description>High Resolution Timer: TIMA</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016880</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HRTIM_TIMA_IRQn</name>
|
|
<description>HRTIM_TIMA_IRQn</description>
|
|
<value>68</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIMACR</name>
|
|
<displayName>TIMACR</displayName>
|
|
<description>Timerx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDGAT</name>
|
|
<description>Update Gating</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREEN</name>
|
|
<description>Preload enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSYNC</name>
|
|
<description>AC Synchronization</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTU</name>
|
|
<description>Master Timer update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEU</name>
|
|
<description>TEU</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDU</name>
|
|
<description>TDU</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCU</name>
|
|
<description>TCU</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBU</name>
|
|
<description>TBU</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxRSTU</name>
|
|
<description>Timerx reset update</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxREPU</name>
|
|
<description>Timer x Repetition update</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFU</name>
|
|
<description>TFU</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP4</name>
|
|
<description>Delayed CMP4 mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP2</name>
|
|
<description>Delayed CMP2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSTRTx</name>
|
|
<description>Synchronization Starts Timer x</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCRSTx</name>
|
|
<description>Synchronization Resets Timer x</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCU</name>
|
|
<description>Re-Synchronized Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTLVD</name>
|
|
<description>Interleaved mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSHPLL</name>
|
|
<description>Push-Pull mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETRIG</name>
|
|
<description>Re-triggerable mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CK_PSCx</name>
|
|
<description>HRTIM Timer x Clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMAISR</name>
|
|
<displayName>TIMAISR</displayName>
|
|
<description>Timerx Interrupt Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>O2CPY</name>
|
|
<description>Output 2 Copy</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1CPY</name>
|
|
<description>Output 1 Copy</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O2STAT</name>
|
|
<description>Output 2 State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1STAT</name>
|
|
<description>Output 1 State</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPPSTAT</name>
|
|
<description>Idle Push Pull Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPPSTAT</name>
|
|
<description>Current Push Pull Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Reset Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2</name>
|
|
<description>Output 2 Reset Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2</name>
|
|
<description>Output 2 Set Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1</name>
|
|
<description>Output 1 Reset Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx1</name>
|
|
<description>Output 1 Set Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2</name>
|
|
<description>Capture2 Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1</name>
|
|
<description>Capture1 Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPD</name>
|
|
<description>Update Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Compare 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMAICR</name>
|
|
<displayName>TIMAICR</displayName>
|
|
<description>Timerx Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTC</name>
|
|
<description>Delayed Protection Flag Clear</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC</name>
|
|
<description>Reset Interrupt flag Clear</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2C</name>
|
|
<description>Output 2 Reset flag Clear</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET2xC</name>
|
|
<description>Output 2 Set flag Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1C</name>
|
|
<description>Output 1 Reset flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xC</name>
|
|
<description>Output 1 Set flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2C</name>
|
|
<description>Capture2 Interrupt flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1C</name>
|
|
<description>Capture1 Interrupt flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDC</name>
|
|
<description>Update Interrupt flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPC</name>
|
|
<description>Repetition Interrupt flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4C</name>
|
|
<description>Compare 4 Interrupt flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3C</name>
|
|
<description>Compare 3 Interrupt flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2C</name>
|
|
<description>Compare 2 Interrupt flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1C</name>
|
|
<description>Compare 1 Interrupt flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMADIER</name>
|
|
<displayName>TIMADIER</displayName>
|
|
<description>TIMxDIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTDE</name>
|
|
<description>DLYPRTDE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTDE</name>
|
|
<description>RSTDE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2DE</name>
|
|
<description>RSTx2DE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2DE</name>
|
|
<description>SETx2DE</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1DE</name>
|
|
<description>RSTx1DE</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xDE</name>
|
|
<description>SET1xDE</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2DE</name>
|
|
<description>CPT2DE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1DE</name>
|
|
<description>CPT1DE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDDE</name>
|
|
<description>UPDDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPDE</name>
|
|
<description>REPDE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4DE</name>
|
|
<description>CMP4DE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3DE</name>
|
|
<description>CMP3DE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2DE</name>
|
|
<description>CMP2DE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1DE</name>
|
|
<description>CMP1DE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTIE</name>
|
|
<description>DLYPRTIE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>RSTIE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2IE</name>
|
|
<description>RSTx2IE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2IE</name>
|
|
<description>SETx2IE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1IE</name>
|
|
<description>RSTx1IE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xIE</name>
|
|
<description>SET1xIE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2IE</name>
|
|
<description>CPT2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1IE</name>
|
|
<description>CPT1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIE</name>
|
|
<description>UPDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPIE</name>
|
|
<description>REPIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4IE</name>
|
|
<description>CMP4IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3IE</name>
|
|
<description>CMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2IE</name>
|
|
<description>CMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1IE</name>
|
|
<description>CMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTAR</name>
|
|
<displayName>CNTAR</displayName>
|
|
<description>Timerx Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNTx</name>
|
|
<description>Timerx Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERAR</name>
|
|
<displayName>PERAR</displayName>
|
|
<description>Timerx Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERx</name>
|
|
<description>Timerx Period value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REPAR</name>
|
|
<displayName>REPAR</displayName>
|
|
<description>Timerx Repetition Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1AR</name>
|
|
<displayName>CMP1AR</displayName>
|
|
<description>Timerx Compare 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1CAR</name>
|
|
<displayName>CMP1CAR</displayName>
|
|
<description>Timerx Compare 1 Compound Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition value (aliased from HRTIM_REPx register)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP2AR</name>
|
|
<displayName>CMP2AR</displayName>
|
|
<description>Timerx Compare 2 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP2x</name>
|
|
<description>Timerx Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP3AR</name>
|
|
<displayName>CMP3AR</displayName>
|
|
<description>Timerx Compare 3 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP3x</name>
|
|
<description>Timerx Compare 3 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP4AR</name>
|
|
<displayName>CMP4AR</displayName>
|
|
<description>Timerx Compare 4 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP4x</name>
|
|
<description>Timerx Compare 4 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1AR</name>
|
|
<displayName>CPT1AR</displayName>
|
|
<description>Timerx Capture 1 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT1x</name>
|
|
<description>Timerx Capture 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2AR</name>
|
|
<displayName>CPT2AR</displayName>
|
|
<description>Timerx Capture 2 Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2x</name>
|
|
<description>Timerx Capture 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTAR</name>
|
|
<displayName>DTAR</displayName>
|
|
<description>Timerx Deadtime Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTFLKx</name>
|
|
<description>Deadtime Falling Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFSLKx</name>
|
|
<description>Deadtime Falling Sign Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTFx</name>
|
|
<description>Sign Deadtime Falling value</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFx</name>
|
|
<description>Deadtime Falling value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRLKx</name>
|
|
<description>Deadtime Rising Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRSLKx</name>
|
|
<description>Deadtime Rising Sign Lock</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSC</name>
|
|
<description>Deadtime Prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTRx</name>
|
|
<description>Sign Deadtime Rising value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRx</name>
|
|
<description>Deadtime Rising value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETA1R</name>
|
|
<displayName>SETA1R</displayName>
|
|
<description>Timerx Output1 Set Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Registers update (transfer preload to active)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>Timer Event 9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>Timer Event 8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>Timer Event 7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>Timer Event 6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>Timer Event 5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>Timer Event 4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>Timer Event 3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>Timer Event 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>Timer Event 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master Compare 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master Compare 3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master Compare 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master Compare 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master Period</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Timer A compare 3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Timer A compare 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Timer A Period</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>Timer A resynchronizaton</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Software Set trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTA1R</name>
|
|
<displayName>RSTA1R</displayName>
|
|
<description>Timerx Output1 Reset Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETA2R</name>
|
|
<displayName>SETA2R</displayName>
|
|
<description>Timerx Output2 Set Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>SST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTA2R</name>
|
|
<displayName>RSTA2R</displayName>
|
|
<description>Timerx Output2 Reset Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFAR1</name>
|
|
<displayName>EEFAR1</displayName>
|
|
<description>Timerx External Event Filtering Register 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE5FLTR</name>
|
|
<description>External Event 5 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5LTCH</name>
|
|
<description>External Event 5 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4FLTR</name>
|
|
<description>External Event 4 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4LTCH</name>
|
|
<description>External Event 4 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3FLTR</name>
|
|
<description>External Event 3 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3LTCH</name>
|
|
<description>External Event 3 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2FLTR</name>
|
|
<description>External Event 2 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2LTCH</name>
|
|
<description>External Event 2 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1FLTR</name>
|
|
<description>External Event 1 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1LTCH</name>
|
|
<description>External Event 1 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFAR2</name>
|
|
<displayName>EEFAR2</displayName>
|
|
<description>Timerx External Event Filtering Register 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE10FLTR</name>
|
|
<description>External Event 10 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10LTCH</name>
|
|
<description>External Event 10 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9FLTR</name>
|
|
<description>External Event 9 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9LTCH</name>
|
|
<description>External Event 9 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8FLTR</name>
|
|
<description>External Event 8 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8LTCH</name>
|
|
<description>External Event 8 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7FLTR</name>
|
|
<description>External Event 7 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7LTCH</name>
|
|
<description>External Event 7 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6FLTR</name>
|
|
<description>External Event 6 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6LTCH</name>
|
|
<description>External Event 6 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTAR</name>
|
|
<displayName>RSTAR</displayName>
|
|
<description>TimerA Reset Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMFCPM2</name>
|
|
<description>Timer F Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP4</name>
|
|
<description>Timer E Compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP4</name>
|
|
<description>Timer D Compare 4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP4</name>
|
|
<description>Timer C Compare 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP4</name>
|
|
<description>Timer B Compare 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master compare 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master compare 3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master compare 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master compare 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master timer Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4 reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2 reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDT</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMFCMP1</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPAR</name>
|
|
<displayName>CHPAR</displayName>
|
|
<description>Timerx Chopper Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRTPW</name>
|
|
<description>STRTPW</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPDTY</name>
|
|
<description>Timerx chopper duty cycle value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPFRQ</name>
|
|
<description>Timerx carrier frequency value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1ACR</name>
|
|
<displayName>CPT1ACR</displayName>
|
|
<description>Timerx Capture 2 Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2ACR</name>
|
|
<displayName>CPT2ACR</displayName>
|
|
<description>CPT2xCR</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTAR</name>
|
|
<displayName>OUTAR</displayName>
|
|
<description>Timerx Output Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIDL2</name>
|
|
<description>Output 2 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP2</name>
|
|
<description>Output 2 Chopper enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2</name>
|
|
<description>Output 2 Fault state</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES2</name>
|
|
<description>Output 2 Idle State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM2</name>
|
|
<description>Output 2 Idle mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Output 2 polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAR</name>
|
|
<description>Balanced Idle Automatic Resume</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTEN</name>
|
|
<description>Delayed Protection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>Deadtime enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIDL1</name>
|
|
<description>Output 1 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP1</name>
|
|
<description>Output 1 Chopper enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Output 1 Fault state</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES1</name>
|
|
<description>Output 1 Idle State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM1</name>
|
|
<description>Output 1 Idle mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Output 1 polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTAR</name>
|
|
<displayName>FLTAR</displayName>
|
|
<description>Timerx Fault Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTLCK</name>
|
|
<description>Fault sources Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6EN</name>
|
|
<description>Fault 6 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5EN</name>
|
|
<description>Fault 5 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4EN</name>
|
|
<description>Fault 4 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3EN</name>
|
|
<description>Fault 3 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2EN</name>
|
|
<description>Fault 2 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1EN</name>
|
|
<description>Fault 1 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMACR2</name>
|
|
<displayName>TIMACR2</displayName>
|
|
<description>HRTIM Timerx Control Register 2</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGHLF</name>
|
|
<description>Triggered-half mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP3</name>
|
|
<description>Greater than Compare 3 PWM mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP1</name>
|
|
<description>Greater than Compare 1 PWM mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEROM</name>
|
|
<description>Fault and Event Roll-Over Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMROM</name>
|
|
<description>Burst Mode Roll-Over Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADROM</name>
|
|
<description>ADC Roll-Over Mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OUTROM</name>
|
|
<description>Output Roll-Over Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Roll-Over Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDM</name>
|
|
<description>Up-Down Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDR</name>
|
|
<description>Dual Channel DAC Reset trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDS</name>
|
|
<description>Dual Channel DAC Step trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDE</name>
|
|
<description>Dual Channel DAC trigger enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AEEFR3</name>
|
|
<displayName>AEEFR3</displayName>
|
|
<description>HRTIM Timerx External Event Filtering Register 3</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EEVACNT</name>
|
|
<description>External Event A counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVASEL</name>
|
|
<description>External Event A Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVARSTM</name>
|
|
<description>External Event A Reset Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACRES</name>
|
|
<description>External Event A Counter Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACE</name>
|
|
<description>External Event A Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_TIMB</name>
|
|
<description>High Resolution Timer: TIMB</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016900</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HRTIM_TIMB_IRQn</name>
|
|
<description>HRTIM_TIMB_IRQn</description>
|
|
<value>69</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIMBCR</name>
|
|
<displayName>TIMBCR</displayName>
|
|
<description>Timerx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDGAT</name>
|
|
<description>Update Gating</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREEN</name>
|
|
<description>Preload enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSYNC</name>
|
|
<description>AC Synchronization</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTU</name>
|
|
<description>Master Timer update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEU</name>
|
|
<description>TEU</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDU</name>
|
|
<description>TDU</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCU</name>
|
|
<description>TCU</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAU</name>
|
|
<description>TAU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxRSTU</name>
|
|
<description>Timerx reset update</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxREPU</name>
|
|
<description>Timer x Repetition update</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFU</name>
|
|
<description>TFU</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP4</name>
|
|
<description>Delayed CMP4 mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP2</name>
|
|
<description>Delayed CMP2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSTRTx</name>
|
|
<description>Synchronization Starts Timer x</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCRSTx</name>
|
|
<description>Synchronization Resets Timer x</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCU</name>
|
|
<description>Re-Synchronized Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTLVD</name>
|
|
<description>Interleaved mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSHPLL</name>
|
|
<description>Push-Pull mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETRIG</name>
|
|
<description>Re-triggerable mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CK_PSCx</name>
|
|
<description>HRTIM Timer x Clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMBISR</name>
|
|
<displayName>TIMBISR</displayName>
|
|
<description>Timerx Interrupt Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>O2CPY</name>
|
|
<description>Output 2 Copy</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1CPY</name>
|
|
<description>Output 1 Copy</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O2STAT</name>
|
|
<description>Output 2 State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1STAT</name>
|
|
<description>Output 1 State</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPPSTAT</name>
|
|
<description>Idle Push Pull Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPPSTAT</name>
|
|
<description>Current Push Pull Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Reset Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2</name>
|
|
<description>Output 2 Reset Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2</name>
|
|
<description>Output 2 Set Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1</name>
|
|
<description>Output 1 Reset Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx1</name>
|
|
<description>Output 1 Set Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2</name>
|
|
<description>Capture2 Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1</name>
|
|
<description>Capture1 Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPD</name>
|
|
<description>Update Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Compare 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMBICR</name>
|
|
<displayName>TIMBICR</displayName>
|
|
<description>Timerx Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTC</name>
|
|
<description>Delayed Protection Flag Clear</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC</name>
|
|
<description>Reset Interrupt flag Clear</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2C</name>
|
|
<description>Output 2 Reset flag Clear</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET2xC</name>
|
|
<description>Output 2 Set flag Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1C</name>
|
|
<description>Output 1 Reset flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xC</name>
|
|
<description>Output 1 Set flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2C</name>
|
|
<description>Capture2 Interrupt flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1C</name>
|
|
<description>Capture1 Interrupt flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDC</name>
|
|
<description>Update Interrupt flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPC</name>
|
|
<description>Repetition Interrupt flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4C</name>
|
|
<description>Compare 4 Interrupt flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3C</name>
|
|
<description>Compare 3 Interrupt flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2C</name>
|
|
<description>Compare 2 Interrupt flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1C</name>
|
|
<description>Compare 1 Interrupt flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMBDIER</name>
|
|
<displayName>TIMBDIER</displayName>
|
|
<description>TIMxDIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTDE</name>
|
|
<description>DLYPRTDE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTDE</name>
|
|
<description>RSTDE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2DE</name>
|
|
<description>RSTx2DE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2DE</name>
|
|
<description>SETx2DE</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1DE</name>
|
|
<description>RSTx1DE</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xDE</name>
|
|
<description>SET1xDE</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2DE</name>
|
|
<description>CPT2DE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1DE</name>
|
|
<description>CPT1DE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDDE</name>
|
|
<description>UPDDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPDE</name>
|
|
<description>REPDE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4DE</name>
|
|
<description>CMP4DE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3DE</name>
|
|
<description>CMP3DE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2DE</name>
|
|
<description>CMP2DE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1DE</name>
|
|
<description>CMP1DE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTIE</name>
|
|
<description>DLYPRTIE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>RSTIE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2IE</name>
|
|
<description>RSTx2IE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2IE</name>
|
|
<description>SETx2IE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1IE</name>
|
|
<description>RSTx1IE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xIE</name>
|
|
<description>SET1xIE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2IE</name>
|
|
<description>CPT2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1IE</name>
|
|
<description>CPT1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIE</name>
|
|
<description>UPDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPIE</name>
|
|
<description>REPIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4IE</name>
|
|
<description>CMP4IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3IE</name>
|
|
<description>CMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2IE</name>
|
|
<description>CMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1IE</name>
|
|
<description>CMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTR</name>
|
|
<displayName>CNTR</displayName>
|
|
<description>Timerx Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNTx</name>
|
|
<description>Timerx Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERBR</name>
|
|
<displayName>PERBR</displayName>
|
|
<description>Timerx Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERx</name>
|
|
<description>Timerx Period value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REPBR</name>
|
|
<displayName>REPBR</displayName>
|
|
<description>Timerx Repetition Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1BR</name>
|
|
<displayName>CMP1BR</displayName>
|
|
<description>Timerx Compare 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1CBR</name>
|
|
<displayName>CMP1CBR</displayName>
|
|
<description>Timerx Compare 1 Compound Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition value (aliased from HRTIM_REPx register)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP2BR</name>
|
|
<displayName>CMP2BR</displayName>
|
|
<description>Timerx Compare 2 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP2x</name>
|
|
<description>Timerx Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP3BR</name>
|
|
<displayName>CMP3BR</displayName>
|
|
<description>Timerx Compare 3 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP3x</name>
|
|
<description>Timerx Compare 3 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP4BR</name>
|
|
<displayName>CMP4BR</displayName>
|
|
<description>Timerx Compare 4 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP4x</name>
|
|
<description>Timerx Compare 4 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1BR</name>
|
|
<displayName>CPT1BR</displayName>
|
|
<description>Timerx Capture 1 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT1x</name>
|
|
<description>Timerx Capture 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2BR</name>
|
|
<displayName>CPT2BR</displayName>
|
|
<description>Timerx Capture 2 Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT2x</name>
|
|
<description>Timerx Capture 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTBR</name>
|
|
<displayName>DTBR</displayName>
|
|
<description>Timerx Deadtime Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTFLKx</name>
|
|
<description>Deadtime Falling Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFSLKx</name>
|
|
<description>Deadtime Falling Sign Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTFx</name>
|
|
<description>Sign Deadtime Falling value</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFx</name>
|
|
<description>Deadtime Falling value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRLKx</name>
|
|
<description>Deadtime Rising Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRSLKx</name>
|
|
<description>Deadtime Rising Sign Lock</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSC</name>
|
|
<description>Deadtime Prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTRx</name>
|
|
<description>Sign Deadtime Rising value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRx</name>
|
|
<description>Deadtime Rising value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETB1R</name>
|
|
<displayName>SETB1R</displayName>
|
|
<description>Timerx Output1 Set Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Registers update (transfer preload to active)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>Timer Event 9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>Timer Event 8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>Timer Event 7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>Timer Event 6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>Timer Event 5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>Timer Event 4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>Timer Event 3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>Timer Event 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>Timer Event 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master Compare 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master Compare 3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master Compare 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master Compare 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master Period</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Timer A compare 3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Timer A compare 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Timer A Period</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>Timer A resynchronizaton</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Software Set trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTB1R</name>
|
|
<displayName>RSTB1R</displayName>
|
|
<description>Timerx Output1 Reset Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETB2R</name>
|
|
<displayName>SETB2R</displayName>
|
|
<description>Timerx Output2 Set Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>SST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTB2R</name>
|
|
<displayName>RSTB2R</displayName>
|
|
<description>Timerx Output2 Reset Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFBR1</name>
|
|
<displayName>EEFBR1</displayName>
|
|
<description>Timerx External Event Filtering Register 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE5FLTR</name>
|
|
<description>External Event 5 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5LTCH</name>
|
|
<description>External Event 5 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4FLTR</name>
|
|
<description>External Event 4 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4LTCH</name>
|
|
<description>External Event 4 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3FLTR</name>
|
|
<description>External Event 3 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3LTCH</name>
|
|
<description>External Event 3 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2FLTR</name>
|
|
<description>External Event 2 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2LTCH</name>
|
|
<description>External Event 2 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1FLTR</name>
|
|
<description>External Event 1 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1LTCH</name>
|
|
<description>External Event 1 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFBR2</name>
|
|
<displayName>EEFBR2</displayName>
|
|
<description>Timerx External Event Filtering Register 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE10FLTR</name>
|
|
<description>External Event 10 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10LTCH</name>
|
|
<description>External Event 10 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9FLTR</name>
|
|
<description>External Event 9 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9LTCH</name>
|
|
<description>External Event 9 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8FLTR</name>
|
|
<description>External Event 8 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8LTCH</name>
|
|
<description>External Event 8 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7FLTR</name>
|
|
<description>External Event 7 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7LTCH</name>
|
|
<description>External Event 7 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6FLTR</name>
|
|
<description>External Event 6 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6LTCH</name>
|
|
<description>External Event 6 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTBR</name>
|
|
<displayName>RSTBR</displayName>
|
|
<description>TimerA Reset Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMFCPM2</name>
|
|
<description>Timer F Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP4</name>
|
|
<description>Timer E Compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP4</name>
|
|
<description>Timer D Compare 4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP4</name>
|
|
<description>Timer C Compare 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP4</name>
|
|
<description>Timer A Compare 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master compare 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master compare 3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master compare 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master compare 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master timer Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4 reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2 reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDT</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMFCMP1</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPBR</name>
|
|
<displayName>CHPBR</displayName>
|
|
<description>Timerx Chopper Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRTPW</name>
|
|
<description>STRTPW</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPDTY</name>
|
|
<description>Timerx chopper duty cycle value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPFRQ</name>
|
|
<description>Timerx carrier frequency value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1BCR</name>
|
|
<displayName>CPT1BCR</displayName>
|
|
<description>Timerx Capture 2 Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2BCR</name>
|
|
<displayName>CPT2BCR</displayName>
|
|
<description>CPT2xCR</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTBR</name>
|
|
<displayName>OUTBR</displayName>
|
|
<description>Timerx Output Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIDL2</name>
|
|
<description>Output 2 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP2</name>
|
|
<description>Output 2 Chopper enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2</name>
|
|
<description>Output 2 Fault state</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES2</name>
|
|
<description>Output 2 Idle State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM2</name>
|
|
<description>Output 2 Idle mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Output 2 polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAR</name>
|
|
<description>Balanced Idle Automatic Resume</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTEN</name>
|
|
<description>Delayed Protection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>Deadtime enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIDL1</name>
|
|
<description>Output 1 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP1</name>
|
|
<description>Output 1 Chopper enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Output 1 Fault state</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES1</name>
|
|
<description>Output 1 Idle State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM1</name>
|
|
<description>Output 1 Idle mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Output 1 polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTBR</name>
|
|
<displayName>FLTBR</displayName>
|
|
<description>Timerx Fault Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTLCK</name>
|
|
<description>Fault sources Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6EN</name>
|
|
<description>Fault 6 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5EN</name>
|
|
<description>Fault 5 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4EN</name>
|
|
<description>Fault 4 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3EN</name>
|
|
<description>Fault 3 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2EN</name>
|
|
<description>Fault 2 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1EN</name>
|
|
<description>Fault 1 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMBCR2</name>
|
|
<displayName>TIMBCR2</displayName>
|
|
<description>HRTIM Timerx Control Register 2</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGHLF</name>
|
|
<description>Triggered-half mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP3</name>
|
|
<description>Greater than Compare 3 PWM mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP1</name>
|
|
<description>Greater than Compare 1 PWM mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEROM</name>
|
|
<description>Fault and Event Roll-Over Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMROM</name>
|
|
<description>Burst Mode Roll-Over Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADROM</name>
|
|
<description>ADC Roll-Over Mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OUTROM</name>
|
|
<description>Output Roll-Over Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Roll-Over Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDM</name>
|
|
<description>Up-Down Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDR</name>
|
|
<description>Dual Channel DAC Reset trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDS</name>
|
|
<description>Dual Channel DAC Step trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDE</name>
|
|
<description>Dual Channel DAC trigger enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BEEFR3</name>
|
|
<displayName>BEEFR3</displayName>
|
|
<description>HRTIM Timerx External Event Filtering Register 3</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EEVACNT</name>
|
|
<description>External Event A counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVASEL</name>
|
|
<description>External Event A Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVARSTM</name>
|
|
<description>External Event A Reset Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACRES</name>
|
|
<description>External Event A Counter Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACE</name>
|
|
<description>External Event A Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_TIMC</name>
|
|
<description>High Resolution Timer: TIMC</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016980</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HRTIM_TIMC_IRQn</name>
|
|
<description>HRTIM_TIMC_IRQn</description>
|
|
<value>70</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIMCCR</name>
|
|
<displayName>TIMCCR</displayName>
|
|
<description>Timerx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDGAT</name>
|
|
<description>Update Gating</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREEN</name>
|
|
<description>Preload enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSYNC</name>
|
|
<description>AC Synchronization</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTU</name>
|
|
<description>Master Timer update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEU</name>
|
|
<description>TEU</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDU</name>
|
|
<description>TDU</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBU</name>
|
|
<description>TBU</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAU</name>
|
|
<description>TAU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxRSTU</name>
|
|
<description>Timerx reset update</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxREPU</name>
|
|
<description>Timer x Repetition update</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFU</name>
|
|
<description>TFU</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP4</name>
|
|
<description>Delayed CMP4 mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP2</name>
|
|
<description>Delayed CMP2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSTRTx</name>
|
|
<description>Synchronization Starts Timer x</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCRSTx</name>
|
|
<description>Synchronization Resets Timer x</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCU</name>
|
|
<description>Re-Synchronized Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTLVD</name>
|
|
<description>Interleaved mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSHPLL</name>
|
|
<description>Push-Pull mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETRIG</name>
|
|
<description>Re-triggerable mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CK_PSCx</name>
|
|
<description>HRTIM Timer x Clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMCISR</name>
|
|
<displayName>TIMCISR</displayName>
|
|
<description>Timerx Interrupt Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>O2CPY</name>
|
|
<description>Output 2 Copy</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1CPY</name>
|
|
<description>Output 1 Copy</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O2STAT</name>
|
|
<description>Output 2 State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1STAT</name>
|
|
<description>Output 1 State</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPPSTAT</name>
|
|
<description>Idle Push Pull Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPPSTAT</name>
|
|
<description>Current Push Pull Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Reset Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2</name>
|
|
<description>Output 2 Reset Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2</name>
|
|
<description>Output 2 Set Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1</name>
|
|
<description>Output 1 Reset Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx1</name>
|
|
<description>Output 1 Set Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2</name>
|
|
<description>Capture2 Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1</name>
|
|
<description>Capture1 Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPD</name>
|
|
<description>Update Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Compare 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMCICR</name>
|
|
<displayName>TIMCICR</displayName>
|
|
<description>Timerx Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTC</name>
|
|
<description>Delayed Protection Flag Clear</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC</name>
|
|
<description>Reset Interrupt flag Clear</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2C</name>
|
|
<description>Output 2 Reset flag Clear</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET2xC</name>
|
|
<description>Output 2 Set flag Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1C</name>
|
|
<description>Output 1 Reset flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xC</name>
|
|
<description>Output 1 Set flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2C</name>
|
|
<description>Capture2 Interrupt flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1C</name>
|
|
<description>Capture1 Interrupt flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDC</name>
|
|
<description>Update Interrupt flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPC</name>
|
|
<description>Repetition Interrupt flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4C</name>
|
|
<description>Compare 4 Interrupt flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3C</name>
|
|
<description>Compare 3 Interrupt flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2C</name>
|
|
<description>Compare 2 Interrupt flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1C</name>
|
|
<description>Compare 1 Interrupt flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMCDIER</name>
|
|
<displayName>TIMCDIER</displayName>
|
|
<description>TIMxDIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTDE</name>
|
|
<description>DLYPRTDE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTDE</name>
|
|
<description>RSTDE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2DE</name>
|
|
<description>RSTx2DE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2DE</name>
|
|
<description>SETx2DE</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1DE</name>
|
|
<description>RSTx1DE</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xDE</name>
|
|
<description>SET1xDE</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2DE</name>
|
|
<description>CPT2DE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1DE</name>
|
|
<description>CPT1DE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDDE</name>
|
|
<description>UPDDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPDE</name>
|
|
<description>REPDE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4DE</name>
|
|
<description>CMP4DE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3DE</name>
|
|
<description>CMP3DE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2DE</name>
|
|
<description>CMP2DE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1DE</name>
|
|
<description>CMP1DE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTIE</name>
|
|
<description>DLYPRTIE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>RSTIE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2IE</name>
|
|
<description>RSTx2IE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2IE</name>
|
|
<description>SETx2IE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1IE</name>
|
|
<description>RSTx1IE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xIE</name>
|
|
<description>SET1xIE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2IE</name>
|
|
<description>CPT2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1IE</name>
|
|
<description>CPT1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIE</name>
|
|
<description>UPDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPIE</name>
|
|
<description>REPIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4IE</name>
|
|
<description>CMP4IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3IE</name>
|
|
<description>CMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2IE</name>
|
|
<description>CMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1IE</name>
|
|
<description>CMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTCR</name>
|
|
<displayName>CNTCR</displayName>
|
|
<description>Timerx Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNTx</name>
|
|
<description>Timerx Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERCR</name>
|
|
<displayName>PERCR</displayName>
|
|
<description>Timerx Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERx</name>
|
|
<description>Timerx Period value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REPCR</name>
|
|
<displayName>REPCR</displayName>
|
|
<description>Timerx Repetition Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1CR</name>
|
|
<displayName>CMP1CR</displayName>
|
|
<description>Timerx Compare 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1CCR</name>
|
|
<displayName>CMP1CCR</displayName>
|
|
<description>Timerx Compare 1 Compound Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition value (aliased from HRTIM_REPx register)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP2CR</name>
|
|
<displayName>CMP2CR</displayName>
|
|
<description>Timerx Compare 2 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP2x</name>
|
|
<description>Timerx Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP3CR</name>
|
|
<displayName>CMP3CR</displayName>
|
|
<description>Timerx Compare 3 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP3x</name>
|
|
<description>Timerx Compare 3 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP4CR</name>
|
|
<displayName>CMP4CR</displayName>
|
|
<description>Timerx Compare 4 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP4x</name>
|
|
<description>Timerx Compare 4 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1CR</name>
|
|
<displayName>CPT1CR</displayName>
|
|
<description>Timerx Capture 1 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT1x</name>
|
|
<description>Timerx Capture 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2CR</name>
|
|
<displayName>CPT2CR</displayName>
|
|
<description>Timerx Capture 2 Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT2x</name>
|
|
<description>Timerx Capture 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTCR</name>
|
|
<displayName>DTCR</displayName>
|
|
<description>Timerx Deadtime Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTFLKx</name>
|
|
<description>Deadtime Falling Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFSLKx</name>
|
|
<description>Deadtime Falling Sign Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTFx</name>
|
|
<description>Sign Deadtime Falling value</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFx</name>
|
|
<description>Deadtime Falling value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRLKx</name>
|
|
<description>Deadtime Rising Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRSLKx</name>
|
|
<description>Deadtime Rising Sign Lock</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSC</name>
|
|
<description>Deadtime Prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTRx</name>
|
|
<description>Sign Deadtime Rising value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRx</name>
|
|
<description>Deadtime Rising value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETC1R</name>
|
|
<displayName>SETC1R</displayName>
|
|
<description>Timerx Output1 Set Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Registers update (transfer preload to active)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>Timer Event 9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>Timer Event 8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>Timer Event 7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>Timer Event 6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>Timer Event 5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>Timer Event 4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>Timer Event 3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>Timer Event 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>Timer Event 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master Compare 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master Compare 3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master Compare 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master Compare 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master Period</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Timer A compare 3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Timer A compare 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Timer A Period</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>Timer A resynchronizaton</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Software Set trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTC1R</name>
|
|
<displayName>RSTC1R</displayName>
|
|
<description>Timerx Output1 Reset Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETC2R</name>
|
|
<displayName>SETC2R</displayName>
|
|
<description>Timerx Output2 Set Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>SST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTC2R</name>
|
|
<displayName>RSTC2R</displayName>
|
|
<description>Timerx Output2 Reset Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFCR1</name>
|
|
<displayName>EEFCR1</displayName>
|
|
<description>Timerx External Event Filtering Register 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE5FLTR</name>
|
|
<description>External Event 5 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5LTCH</name>
|
|
<description>External Event 5 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4FLTR</name>
|
|
<description>External Event 4 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4LTCH</name>
|
|
<description>External Event 4 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3FLTR</name>
|
|
<description>External Event 3 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3LTCH</name>
|
|
<description>External Event 3 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2FLTR</name>
|
|
<description>External Event 2 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2LTCH</name>
|
|
<description>External Event 2 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1FLTR</name>
|
|
<description>External Event 1 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1LTCH</name>
|
|
<description>External Event 1 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFCR2</name>
|
|
<displayName>EEFCR2</displayName>
|
|
<description>Timerx External Event Filtering Register 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE10FLTR</name>
|
|
<description>External Event 10 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10LTCH</name>
|
|
<description>External Event 10 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9FLTR</name>
|
|
<description>External Event 9 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9LTCH</name>
|
|
<description>External Event 9 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8FLTR</name>
|
|
<description>External Event 8 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8LTCH</name>
|
|
<description>External Event 8 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7FLTR</name>
|
|
<description>External Event 7 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7LTCH</name>
|
|
<description>External Event 7 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6FLTR</name>
|
|
<description>External Event 6 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6LTCH</name>
|
|
<description>External Event 6 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTCR</name>
|
|
<displayName>RSTCR</displayName>
|
|
<description>TimerA Reset Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMFCPM2</name>
|
|
<description>Timer F Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP4</name>
|
|
<description>Timer E Compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP4</name>
|
|
<description>Timer D Compare 4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP4</name>
|
|
<description>Timer B Compare 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP4</name>
|
|
<description>Timer A Compare 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master compare 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master compare 3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master compare 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master compare 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master timer Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4 reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2 reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDT</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMFCMP1</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPCR</name>
|
|
<displayName>CHPCR</displayName>
|
|
<description>Timerx Chopper Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRTPW</name>
|
|
<description>STRTPW</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPDTY</name>
|
|
<description>Timerx chopper duty cycle value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPFRQ</name>
|
|
<description>Timerx carrier frequency value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1CCR</name>
|
|
<displayName>CPT1CCR</displayName>
|
|
<description>Timerx Capture 2 Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2CCR</name>
|
|
<displayName>CPT2CCR</displayName>
|
|
<description>CPT2xCR</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1CMP2</name>
|
|
<description>TF1CMP2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1CMP1</name>
|
|
<description>TF1CMP1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTCR</name>
|
|
<displayName>OUTCR</displayName>
|
|
<description>Timerx Output Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIDL2</name>
|
|
<description>Output 2 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP2</name>
|
|
<description>Output 2 Chopper enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2</name>
|
|
<description>Output 2 Fault state</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES2</name>
|
|
<description>Output 2 Idle State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM2</name>
|
|
<description>Output 2 Idle mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Output 2 polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAR</name>
|
|
<description>Balanced Idle Automatic Resume</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTEN</name>
|
|
<description>Delayed Protection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>Deadtime enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIDL1</name>
|
|
<description>Output 1 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP1</name>
|
|
<description>Output 1 Chopper enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Output 1 Fault state</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES1</name>
|
|
<description>Output 1 Idle State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM1</name>
|
|
<description>Output 1 Idle mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Output 1 polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCR</name>
|
|
<displayName>FLTCR</displayName>
|
|
<description>Timerx Fault Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTLCK</name>
|
|
<description>Fault sources Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6EN</name>
|
|
<description>Fault 6 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5EN</name>
|
|
<description>Fault 5 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4EN</name>
|
|
<description>Fault 4 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3EN</name>
|
|
<description>Fault 3 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2EN</name>
|
|
<description>Fault 2 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1EN</name>
|
|
<description>Fault 1 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMCCR2</name>
|
|
<displayName>TIMCCR2</displayName>
|
|
<description>HRTIM Timerx Control Register 2</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGHLF</name>
|
|
<description>Triggered-half mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP3</name>
|
|
<description>Greater than Compare 3 PWM mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP1</name>
|
|
<description>Greater than Compare 1 PWM mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEROM</name>
|
|
<description>Fault and Event Roll-Over Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMROM</name>
|
|
<description>Burst Mode Roll-Over Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADROM</name>
|
|
<description>ADC Roll-Over Mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OUTROM</name>
|
|
<description>Output Roll-Over Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Roll-Over Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDM</name>
|
|
<description>Up-Down Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDR</name>
|
|
<description>Dual Channel DAC Reset trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDS</name>
|
|
<description>Dual Channel DAC Step trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDE</name>
|
|
<description>Dual Channel DAC trigger enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CEEFR3</name>
|
|
<displayName>CEEFR3</displayName>
|
|
<description>HRTIM Timerx External Event Filtering Register 3</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EEVACNT</name>
|
|
<description>External Event A counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVASEL</name>
|
|
<description>External Event A Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVARSTM</name>
|
|
<description>External Event A Reset Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACRES</name>
|
|
<description>External Event A Counter Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACE</name>
|
|
<description>External Event A Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_TIMD</name>
|
|
<description>High Resolution Timer: TIMD</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016A00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HRTIM_TIMD_IRQn</name>
|
|
<description>HRTIM_TIMD_IRQn</description>
|
|
<value>71</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIMDCR</name>
|
|
<displayName>TIMDCR</displayName>
|
|
<description>Timerx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDGAT</name>
|
|
<description>Update Gating</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREEN</name>
|
|
<description>Preload enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSYNC</name>
|
|
<description>AC Synchronization</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTU</name>
|
|
<description>Master Timer update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEU</name>
|
|
<description>TEU</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCU</name>
|
|
<description>TCU</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBU</name>
|
|
<description>TBU</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAU</name>
|
|
<description>TAU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxRSTU</name>
|
|
<description>Timerx reset update</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxREPU</name>
|
|
<description>Timer x Repetition update</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFU</name>
|
|
<description>TFU</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP4</name>
|
|
<description>Delayed CMP4 mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP2</name>
|
|
<description>Delayed CMP2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSTRTx</name>
|
|
<description>Synchronization Starts Timer x</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCRSTx</name>
|
|
<description>Synchronization Resets Timer x</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCU</name>
|
|
<description>Re-Synchronized Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTLVD</name>
|
|
<description>Interleaved mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSHPLL</name>
|
|
<description>Push-Pull mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETRIG</name>
|
|
<description>Re-triggerable mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CK_PSCx</name>
|
|
<description>HRTIM Timer x Clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMDISR</name>
|
|
<displayName>TIMDISR</displayName>
|
|
<description>Timerx Interrupt Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>O2CPY</name>
|
|
<description>Output 2 Copy</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1CPY</name>
|
|
<description>Output 1 Copy</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O2STAT</name>
|
|
<description>Output 2 State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1STAT</name>
|
|
<description>Output 1 State</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPPSTAT</name>
|
|
<description>Idle Push Pull Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPPSTAT</name>
|
|
<description>Current Push Pull Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Reset Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2</name>
|
|
<description>Output 2 Reset Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2</name>
|
|
<description>Output 2 Set Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1</name>
|
|
<description>Output 1 Reset Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx1</name>
|
|
<description>Output 1 Set Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2</name>
|
|
<description>Capture2 Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1</name>
|
|
<description>Capture1 Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPD</name>
|
|
<description>Update Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Compare 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMDICR</name>
|
|
<displayName>TIMDICR</displayName>
|
|
<description>Timerx Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTC</name>
|
|
<description>Delayed Protection Flag Clear</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC</name>
|
|
<description>Reset Interrupt flag Clear</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2C</name>
|
|
<description>Output 2 Reset flag Clear</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET2xC</name>
|
|
<description>Output 2 Set flag Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1C</name>
|
|
<description>Output 1 Reset flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xC</name>
|
|
<description>Output 1 Set flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2C</name>
|
|
<description>Capture2 Interrupt flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1C</name>
|
|
<description>Capture1 Interrupt flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDC</name>
|
|
<description>Update Interrupt flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPC</name>
|
|
<description>Repetition Interrupt flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4C</name>
|
|
<description>Compare 4 Interrupt flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3C</name>
|
|
<description>Compare 3 Interrupt flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2C</name>
|
|
<description>Compare 2 Interrupt flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1C</name>
|
|
<description>Compare 1 Interrupt flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMDDIER</name>
|
|
<displayName>TIMDDIER</displayName>
|
|
<description>TIMxDIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTDE</name>
|
|
<description>DLYPRTDE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTDE</name>
|
|
<description>RSTDE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2DE</name>
|
|
<description>RSTx2DE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2DE</name>
|
|
<description>SETx2DE</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1DE</name>
|
|
<description>RSTx1DE</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xDE</name>
|
|
<description>SET1xDE</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2DE</name>
|
|
<description>CPT2DE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1DE</name>
|
|
<description>CPT1DE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDDE</name>
|
|
<description>UPDDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPDE</name>
|
|
<description>REPDE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4DE</name>
|
|
<description>CMP4DE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3DE</name>
|
|
<description>CMP3DE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2DE</name>
|
|
<description>CMP2DE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1DE</name>
|
|
<description>CMP1DE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTIE</name>
|
|
<description>DLYPRTIE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>RSTIE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2IE</name>
|
|
<description>RSTx2IE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2IE</name>
|
|
<description>SETx2IE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1IE</name>
|
|
<description>RSTx1IE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xIE</name>
|
|
<description>SET1xIE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2IE</name>
|
|
<description>CPT2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1IE</name>
|
|
<description>CPT1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIE</name>
|
|
<description>UPDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPIE</name>
|
|
<description>REPIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4IE</name>
|
|
<description>CMP4IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3IE</name>
|
|
<description>CMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2IE</name>
|
|
<description>CMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1IE</name>
|
|
<description>CMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTDR</name>
|
|
<displayName>CNTDR</displayName>
|
|
<description>Timerx Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNTx</name>
|
|
<description>Timerx Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERDR</name>
|
|
<displayName>PERDR</displayName>
|
|
<description>Timerx Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERx</name>
|
|
<description>Timerx Period value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REPDR</name>
|
|
<displayName>REPDR</displayName>
|
|
<description>Timerx Repetition Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1DR</name>
|
|
<displayName>CMP1DR</displayName>
|
|
<description>Timerx Compare 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1CDR</name>
|
|
<displayName>CMP1CDR</displayName>
|
|
<description>Timerx Compare 1 Compound Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition value (aliased from HRTIM_REPx register)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP2DR</name>
|
|
<displayName>CMP2DR</displayName>
|
|
<description>Timerx Compare 2 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP2x</name>
|
|
<description>Timerx Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP3DR</name>
|
|
<displayName>CMP3DR</displayName>
|
|
<description>Timerx Compare 3 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP3x</name>
|
|
<description>Timerx Compare 3 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP4DR</name>
|
|
<displayName>CMP4DR</displayName>
|
|
<description>Timerx Compare 4 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP4x</name>
|
|
<description>Timerx Compare 4 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1DR</name>
|
|
<displayName>CPT1DR</displayName>
|
|
<description>Timerx Capture 1 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT1x</name>
|
|
<description>Timerx Capture 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2DR</name>
|
|
<displayName>CPT2DR</displayName>
|
|
<description>Timerx Capture 2 Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT2x</name>
|
|
<description>Timerx Capture 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTDR</name>
|
|
<displayName>DTDR</displayName>
|
|
<description>Timerx Deadtime Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTFLKx</name>
|
|
<description>Deadtime Falling Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFSLKx</name>
|
|
<description>Deadtime Falling Sign Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTFx</name>
|
|
<description>Sign Deadtime Falling value</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFx</name>
|
|
<description>Deadtime Falling value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRLKx</name>
|
|
<description>Deadtime Rising Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRSLKx</name>
|
|
<description>Deadtime Rising Sign Lock</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSC</name>
|
|
<description>Deadtime Prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTRx</name>
|
|
<description>Sign Deadtime Rising value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRx</name>
|
|
<description>Deadtime Rising value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETD1R</name>
|
|
<displayName>SETD1R</displayName>
|
|
<description>Timerx Output1 Set Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Registers update (transfer preload to active)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>Timer Event 9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>Timer Event 8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>Timer Event 7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>Timer Event 6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>Timer Event 5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>Timer Event 4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>Timer Event 3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>Timer Event 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>Timer Event 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master Compare 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master Compare 3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master Compare 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master Compare 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master Period</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Timer A compare 3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Timer A compare 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Timer A Period</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>Timer A resynchronizaton</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Software Set trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTD1R</name>
|
|
<displayName>RSTD1R</displayName>
|
|
<description>Timerx Output1 Reset Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETD2R</name>
|
|
<displayName>SETD2R</displayName>
|
|
<description>Timerx Output2 Set Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>SST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTD2R</name>
|
|
<displayName>RSTD2R</displayName>
|
|
<description>Timerx Output2 Reset Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFDR1</name>
|
|
<displayName>EEFDR1</displayName>
|
|
<description>Timerx External Event Filtering Register 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE5FLTR</name>
|
|
<description>External Event 5 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5LTCH</name>
|
|
<description>External Event 5 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4FLTR</name>
|
|
<description>External Event 4 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4LTCH</name>
|
|
<description>External Event 4 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3FLTR</name>
|
|
<description>External Event 3 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3LTCH</name>
|
|
<description>External Event 3 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2FLTR</name>
|
|
<description>External Event 2 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2LTCH</name>
|
|
<description>External Event 2 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1FLTR</name>
|
|
<description>External Event 1 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1LTCH</name>
|
|
<description>External Event 1 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFDR2</name>
|
|
<displayName>EEFDR2</displayName>
|
|
<description>Timerx External Event Filtering Register 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE10FLTR</name>
|
|
<description>External Event 10 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10LTCH</name>
|
|
<description>External Event 10 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9FLTR</name>
|
|
<description>External Event 9 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9LTCH</name>
|
|
<description>External Event 9 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8FLTR</name>
|
|
<description>External Event 8 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8LTCH</name>
|
|
<description>External Event 8 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7FLTR</name>
|
|
<description>External Event 7 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7LTCH</name>
|
|
<description>External Event 7 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6FLTR</name>
|
|
<description>External Event 6 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6LTCH</name>
|
|
<description>External Event 6 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTDR</name>
|
|
<displayName>RSTDR</displayName>
|
|
<description>TimerA Reset Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMFCPM2</name>
|
|
<description>Timer F Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP4</name>
|
|
<description>Timer E Compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP4</name>
|
|
<description>Timer C Compare 4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP4</name>
|
|
<description>Timer B Compare 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP4</name>
|
|
<description>Timer A Compare 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master compare 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master compare 3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master compare 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master compare 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master timer Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4 reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2 reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDT</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMFCMP1</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPDR</name>
|
|
<displayName>CHPDR</displayName>
|
|
<description>Timerx Chopper Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRTPW</name>
|
|
<description>STRTPW</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPDTY</name>
|
|
<description>Timerx chopper duty cycle value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPFRQ</name>
|
|
<description>Timerx carrier frequency value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1DCR</name>
|
|
<displayName>CPT1DCR</displayName>
|
|
<description>Timerx Capture 2 Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2DCR</name>
|
|
<displayName>CPT2DCR</displayName>
|
|
<description>CPT2xCR</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>Timer E Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>Timer E Compare 1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>Timer E output 1 Reset</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>Timer E output 1 Set</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTDR</name>
|
|
<displayName>OUTDR</displayName>
|
|
<description>Timerx Output Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIDL2</name>
|
|
<description>Output 2 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP2</name>
|
|
<description>Output 2 Chopper enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2</name>
|
|
<description>Output 2 Fault state</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES2</name>
|
|
<description>Output 2 Idle State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM2</name>
|
|
<description>Output 2 Idle mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Output 2 polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAR</name>
|
|
<description>Balanced Idle Automatic Resume</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTEN</name>
|
|
<description>Delayed Protection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>Deadtime enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIDL1</name>
|
|
<description>Output 1 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP1</name>
|
|
<description>Output 1 Chopper enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Output 1 Fault state</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES1</name>
|
|
<description>Output 1 Idle State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM1</name>
|
|
<description>Output 1 Idle mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Output 1 polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTDR</name>
|
|
<displayName>FLTDR</displayName>
|
|
<description>Timerx Fault Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTLCK</name>
|
|
<description>Fault sources Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6EN</name>
|
|
<description>Fault 6 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5EN</name>
|
|
<description>Fault 5 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4EN</name>
|
|
<description>Fault 4 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3EN</name>
|
|
<description>Fault 3 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2EN</name>
|
|
<description>Fault 2 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1EN</name>
|
|
<description>Fault 1 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMDCR2</name>
|
|
<displayName>TIMDCR2</displayName>
|
|
<description>HRTIM Timerx Control Register 2</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGHLF</name>
|
|
<description>Triggered-half mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP3</name>
|
|
<description>Greater than Compare 3 PWM mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP1</name>
|
|
<description>Greater than Compare 1 PWM mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEROM</name>
|
|
<description>Fault and Event Roll-Over Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMROM</name>
|
|
<description>Burst Mode Roll-Over Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADROM</name>
|
|
<description>ADC Roll-Over Mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OUTROM</name>
|
|
<description>Output Roll-Over Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Roll-Over Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDM</name>
|
|
<description>Up-Down Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDR</name>
|
|
<description>Dual Channel DAC Reset trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDS</name>
|
|
<description>Dual Channel DAC Step trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDE</name>
|
|
<description>Dual Channel DAC trigger enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DEEFR3</name>
|
|
<displayName>DEEFR3</displayName>
|
|
<description>HRTIM Timerx External Event Filtering Register 3</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EEVACNT</name>
|
|
<description>External Event A counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVASEL</name>
|
|
<description>External Event A Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVARSTM</name>
|
|
<description>External Event A Reset Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACRES</name>
|
|
<description>External Event A Counter Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACE</name>
|
|
<description>External Event A Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_TIME</name>
|
|
<description>High Resolution Timer: TIME</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016A80</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TIMECR</name>
|
|
<displayName>TIMECR</displayName>
|
|
<description>Timerx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDGAT</name>
|
|
<description>Update Gating</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREEN</name>
|
|
<description>Preload enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSYNC</name>
|
|
<description>AC Synchronization</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTU</name>
|
|
<description>Master Timer update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDU</name>
|
|
<description>TDU</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCU</name>
|
|
<description>TCU</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBU</name>
|
|
<description>TBU</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAU</name>
|
|
<description>TAU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxRSTU</name>
|
|
<description>Timerx reset update</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxREPU</name>
|
|
<description>Timer x Repetition update</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFU</name>
|
|
<description>TFU</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP4</name>
|
|
<description>Delayed CMP4 mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP2</name>
|
|
<description>Delayed CMP2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSTRTx</name>
|
|
<description>Synchronization Starts Timer x</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCRSTx</name>
|
|
<description>Synchronization Resets Timer x</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCU</name>
|
|
<description>Re-Synchronized Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTLVD</name>
|
|
<description>Interleaved mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSHPLL</name>
|
|
<description>Push-Pull mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETRIG</name>
|
|
<description>Re-triggerable mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CK_PSCx</name>
|
|
<description>HRTIM Timer x Clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMEISR</name>
|
|
<displayName>TIMEISR</displayName>
|
|
<description>Timerx Interrupt Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>O2CPY</name>
|
|
<description>Output 2 Copy</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1CPY</name>
|
|
<description>Output 1 Copy</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O2STAT</name>
|
|
<description>Output 2 State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1STAT</name>
|
|
<description>Output 1 State</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPPSTAT</name>
|
|
<description>Idle Push Pull Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPPSTAT</name>
|
|
<description>Current Push Pull Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Reset Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2</name>
|
|
<description>Output 2 Reset Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2</name>
|
|
<description>Output 2 Set Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1</name>
|
|
<description>Output 1 Reset Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx1</name>
|
|
<description>Output 1 Set Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2</name>
|
|
<description>Capture2 Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1</name>
|
|
<description>Capture1 Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPD</name>
|
|
<description>Update Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Compare 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMEICR</name>
|
|
<displayName>TIMEICR</displayName>
|
|
<description>Timerx Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTC</name>
|
|
<description>Delayed Protection Flag Clear</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC</name>
|
|
<description>Reset Interrupt flag Clear</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2C</name>
|
|
<description>Output 2 Reset flag Clear</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET2xC</name>
|
|
<description>Output 2 Set flag Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1C</name>
|
|
<description>Output 1 Reset flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xC</name>
|
|
<description>Output 1 Set flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2C</name>
|
|
<description>Capture2 Interrupt flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1C</name>
|
|
<description>Capture1 Interrupt flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDC</name>
|
|
<description>Update Interrupt flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPC</name>
|
|
<description>Repetition Interrupt flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4C</name>
|
|
<description>Compare 4 Interrupt flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3C</name>
|
|
<description>Compare 3 Interrupt flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2C</name>
|
|
<description>Compare 2 Interrupt flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1C</name>
|
|
<description>Compare 1 Interrupt flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMEDIER</name>
|
|
<displayName>TIMEDIER</displayName>
|
|
<description>TIMxDIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTDE</name>
|
|
<description>DLYPRTDE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTDE</name>
|
|
<description>RSTDE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2DE</name>
|
|
<description>RSTx2DE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2DE</name>
|
|
<description>SETx2DE</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1DE</name>
|
|
<description>RSTx1DE</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xDE</name>
|
|
<description>SET1xDE</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2DE</name>
|
|
<description>CPT2DE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1DE</name>
|
|
<description>CPT1DE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDDE</name>
|
|
<description>UPDDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPDE</name>
|
|
<description>REPDE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4DE</name>
|
|
<description>CMP4DE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3DE</name>
|
|
<description>CMP3DE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2DE</name>
|
|
<description>CMP2DE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1DE</name>
|
|
<description>CMP1DE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTIE</name>
|
|
<description>DLYPRTIE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>RSTIE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2IE</name>
|
|
<description>RSTx2IE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2IE</name>
|
|
<description>SETx2IE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1IE</name>
|
|
<description>RSTx1IE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xIE</name>
|
|
<description>SET1xIE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2IE</name>
|
|
<description>CPT2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1IE</name>
|
|
<description>CPT1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIE</name>
|
|
<description>UPDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPIE</name>
|
|
<description>REPIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4IE</name>
|
|
<description>CMP4IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3IE</name>
|
|
<description>CMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2IE</name>
|
|
<description>CMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1IE</name>
|
|
<description>CMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTER</name>
|
|
<displayName>CNTER</displayName>
|
|
<description>Timerx Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNTx</name>
|
|
<description>Timerx Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERER</name>
|
|
<displayName>PERER</displayName>
|
|
<description>Timerx Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERx</name>
|
|
<description>Timerx Period value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REPER</name>
|
|
<displayName>REPER</displayName>
|
|
<description>Timerx Repetition Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1ER</name>
|
|
<displayName>CMP1ER</displayName>
|
|
<description>Timerx Compare 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1CER</name>
|
|
<displayName>CMP1CER</displayName>
|
|
<description>Timerx Compare 1 Compound Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition value (aliased from HRTIM_REPx register)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP2ER</name>
|
|
<displayName>CMP2ER</displayName>
|
|
<description>Timerx Compare 2 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP2x</name>
|
|
<description>Timerx Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP3ER</name>
|
|
<displayName>CMP3ER</displayName>
|
|
<description>Timerx Compare 3 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP3x</name>
|
|
<description>Timerx Compare 3 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP4ER</name>
|
|
<displayName>CMP4ER</displayName>
|
|
<description>Timerx Compare 4 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP4x</name>
|
|
<description>Timerx Compare 4 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1ER</name>
|
|
<displayName>CPT1ER</displayName>
|
|
<description>Timerx Capture 1 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT1x</name>
|
|
<description>Timerx Capture 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2ER</name>
|
|
<displayName>CPT2ER</displayName>
|
|
<description>Timerx Capture 2 Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT2x</name>
|
|
<description>Timerx Capture 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTER</name>
|
|
<displayName>DTER</displayName>
|
|
<description>Timerx Deadtime Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTFLKx</name>
|
|
<description>Deadtime Falling Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFSLKx</name>
|
|
<description>Deadtime Falling Sign Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTFx</name>
|
|
<description>Sign Deadtime Falling value</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFx</name>
|
|
<description>Deadtime Falling value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRLKx</name>
|
|
<description>Deadtime Rising Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRSLKx</name>
|
|
<description>Deadtime Rising Sign Lock</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSC</name>
|
|
<description>Deadtime Prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTRx</name>
|
|
<description>Sign Deadtime Rising value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRx</name>
|
|
<description>Deadtime Rising value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETE1R</name>
|
|
<displayName>SETE1R</displayName>
|
|
<description>Timerx Output1 Set Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Registers update (transfer preload to active)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>Timer Event 9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>Timer Event 8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>Timer Event 7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>Timer Event 6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>Timer Event 5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>Timer Event 4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>Timer Event 3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>Timer Event 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>Timer Event 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master Compare 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master Compare 3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master Compare 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master Compare 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master Period</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Timer A compare 3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Timer A compare 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Timer A Period</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>Timer A resynchronizaton</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Software Set trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTE1R</name>
|
|
<displayName>RSTE1R</displayName>
|
|
<description>Timerx Output1 Reset Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETE2R</name>
|
|
<displayName>SETE2R</displayName>
|
|
<description>Timerx Output2 Set Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>SST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTE2R</name>
|
|
<displayName>RSTE2R</displayName>
|
|
<description>Timerx Output2 Reset Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFER1</name>
|
|
<displayName>EEFER1</displayName>
|
|
<description>Timerx External Event Filtering Register 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE5FLTR</name>
|
|
<description>External Event 5 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5LTCH</name>
|
|
<description>External Event 5 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4FLTR</name>
|
|
<description>External Event 4 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4LTCH</name>
|
|
<description>External Event 4 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3FLTR</name>
|
|
<description>External Event 3 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3LTCH</name>
|
|
<description>External Event 3 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2FLTR</name>
|
|
<description>External Event 2 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2LTCH</name>
|
|
<description>External Event 2 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1FLTR</name>
|
|
<description>External Event 1 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1LTCH</name>
|
|
<description>External Event 1 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFER2</name>
|
|
<displayName>EEFER2</displayName>
|
|
<description>Timerx External Event Filtering Register 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE10FLTR</name>
|
|
<description>External Event 10 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10LTCH</name>
|
|
<description>External Event 10 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9FLTR</name>
|
|
<description>External Event 9 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9LTCH</name>
|
|
<description>External Event 9 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8FLTR</name>
|
|
<description>External Event 8 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8LTCH</name>
|
|
<description>External Event 8 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7FLTR</name>
|
|
<description>External Event 7 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7LTCH</name>
|
|
<description>External Event 7 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6FLTR</name>
|
|
<description>External Event 6 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6LTCH</name>
|
|
<description>External Event 6 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTER</name>
|
|
<displayName>RSTER</displayName>
|
|
<description>TimerA Reset Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMFCPM2</name>
|
|
<description>Timer F Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP4</name>
|
|
<description>Timer D Compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP4</name>
|
|
<description>Timer C Compare 4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP4</name>
|
|
<description>Timer B Compare 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP4</name>
|
|
<description>Timer A Compare 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master compare 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master compare 3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master compare 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master compare 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master timer Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4 reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2 reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDT</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMFCMP1</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPER</name>
|
|
<displayName>CHPER</displayName>
|
|
<description>Timerx Chopper Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRTPW</name>
|
|
<description>STRTPW</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPDTY</name>
|
|
<description>Timerx chopper duty cycle value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPFRQ</name>
|
|
<description>Timerx carrier frequency value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1ECR</name>
|
|
<displayName>CPT1ECR</displayName>
|
|
<description>Timerx Capture 2 Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2ECR</name>
|
|
<displayName>CPT2ECR</displayName>
|
|
<description>CPT2xCR</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFCMP2</name>
|
|
<description>TFCMP2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFCMP1</name>
|
|
<description>TFCMP1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1RST</name>
|
|
<description>TF1RST</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1SET</name>
|
|
<description>TF1SET</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTER</name>
|
|
<displayName>OUTER</displayName>
|
|
<description>Timerx Output Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIDL2</name>
|
|
<description>Output 2 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP2</name>
|
|
<description>Output 2 Chopper enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2</name>
|
|
<description>Output 2 Fault state</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES2</name>
|
|
<description>Output 2 Idle State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM2</name>
|
|
<description>Output 2 Idle mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Output 2 polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAR</name>
|
|
<description>Balanced Idle Automatic Resume</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTEN</name>
|
|
<description>Delayed Protection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>Deadtime enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIDL1</name>
|
|
<description>Output 1 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP1</name>
|
|
<description>Output 1 Chopper enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Output 1 Fault state</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES1</name>
|
|
<description>Output 1 Idle State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM1</name>
|
|
<description>Output 1 Idle mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Output 1 polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTER</name>
|
|
<displayName>FLTER</displayName>
|
|
<description>Timerx Fault Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTLCK</name>
|
|
<description>Fault sources Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6EN</name>
|
|
<description>Fault 6 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5EN</name>
|
|
<description>Fault 5 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4EN</name>
|
|
<description>Fault 4 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3EN</name>
|
|
<description>Fault 3 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2EN</name>
|
|
<description>Fault 2 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1EN</name>
|
|
<description>Fault 1 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMECR2</name>
|
|
<displayName>TIMECR2</displayName>
|
|
<description>HRTIM Timerx Control Register 2</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGHLF</name>
|
|
<description>Triggered-half mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP3</name>
|
|
<description>Greater than Compare 3 PWM mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP1</name>
|
|
<description>Greater than Compare 1 PWM mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEROM</name>
|
|
<description>Fault and Event Roll-Over Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMROM</name>
|
|
<description>Burst Mode Roll-Over Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADROM</name>
|
|
<description>ADC Roll-Over Mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OUTROM</name>
|
|
<description>Output Roll-Over Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Roll-Over Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDM</name>
|
|
<description>Up-Down Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDR</name>
|
|
<description>Dual Channel DAC Reset trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDS</name>
|
|
<description>Dual Channel DAC Step trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDE</name>
|
|
<description>Dual Channel DAC trigger enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEEFR3</name>
|
|
<displayName>EEEFR3</displayName>
|
|
<description>HRTIM Timerx External Event Filtering Register 3</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EEVACNT</name>
|
|
<description>External Event A counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVASEL</name>
|
|
<description>External Event A Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVARSTM</name>
|
|
<description>External Event A Reset Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACRES</name>
|
|
<description>External Event A Counter Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACE</name>
|
|
<description>External Event A Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_TIMF</name>
|
|
<description>High Resolution Timer: TIMF</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016B00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x80</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HRTIM_TIME_IRQn</name>
|
|
<description>HRTIM_TIME_IRQn</description>
|
|
<value>72</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>HRTIM_TIMF_IRQn</name>
|
|
<description>HRTIM_TIMF_IRQn</description>
|
|
<value>74</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TIMFCR</name>
|
|
<displayName>TIMFCR</displayName>
|
|
<description>Timerx Control Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDGAT</name>
|
|
<description>Update Gating</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PREEN</name>
|
|
<description>Preload enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACSYNC</name>
|
|
<description>AC Synchronization</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTU</name>
|
|
<description>Master Timer update</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDU</name>
|
|
<description>TDU</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCU</name>
|
|
<description>TCU</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBU</name>
|
|
<description>TBU</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAU</name>
|
|
<description>TAU</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxRSTU</name>
|
|
<description>Timerx reset update</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TxREPU</name>
|
|
<description>Timer x Repetition update</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP4</name>
|
|
<description>Delayed CMP4 mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELCMP2</name>
|
|
<description>Delayed CMP2 mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSTRTx</name>
|
|
<description>Synchronization Starts Timer x</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCRSTx</name>
|
|
<description>Synchronization Resets Timer x</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSYNCU</name>
|
|
<description>Re-Synchronized Update</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTLVD</name>
|
|
<description>Interleaved mode</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSHPLL</name>
|
|
<description>Push-Pull mode enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HALF</name>
|
|
<description>Half mode enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETRIG</name>
|
|
<description>Re-triggerable mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>Continuous mode</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CK_PSCx</name>
|
|
<description>HRTIM Timer x Clock prescaler</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMFISR</name>
|
|
<displayName>TIMFISR</displayName>
|
|
<description>Timerx Interrupt Status Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>O2CPY</name>
|
|
<description>Output 2 Copy</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1CPY</name>
|
|
<description>Output 1 Copy</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O2STAT</name>
|
|
<description>Output 2 State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>O1STAT</name>
|
|
<description>Output 1 State</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPPSTAT</name>
|
|
<description>Idle Push Pull Status</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPPSTAT</name>
|
|
<description>Current Push Pull Status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection Flag</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RST</name>
|
|
<description>Reset Interrupt Flag</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2</name>
|
|
<description>Output 2 Reset Interrupt Flag</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2</name>
|
|
<description>Output 2 Set Interrupt Flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1</name>
|
|
<description>Output 1 Reset Interrupt Flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx1</name>
|
|
<description>Output 1 Set Interrupt Flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2</name>
|
|
<description>Capture2 Interrupt Flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1</name>
|
|
<description>Capture1 Interrupt Flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPD</name>
|
|
<description>Update Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>Repetition Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Compare 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Compare 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Compare 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Compare 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMFICR</name>
|
|
<displayName>TIMFICR</displayName>
|
|
<description>Timerx Interrupt Clear Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTC</name>
|
|
<description>Delayed Protection Flag Clear</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTC</name>
|
|
<description>Reset Interrupt flag Clear</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2C</name>
|
|
<description>Output 2 Reset flag Clear</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET2xC</name>
|
|
<description>Output 2 Set flag Clear</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1C</name>
|
|
<description>Output 1 Reset flag Clear</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xC</name>
|
|
<description>Output 1 Set flag Clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2C</name>
|
|
<description>Capture2 Interrupt flag Clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1C</name>
|
|
<description>Capture1 Interrupt flag Clear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDC</name>
|
|
<description>Update Interrupt flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPC</name>
|
|
<description>Repetition Interrupt flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4C</name>
|
|
<description>Compare 4 Interrupt flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3C</name>
|
|
<description>Compare 3 Interrupt flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2C</name>
|
|
<description>Compare 2 Interrupt flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1C</name>
|
|
<description>Compare 1 Interrupt flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMFDIER</name>
|
|
<displayName>TIMFDIER</displayName>
|
|
<description>TIMxDIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYPRTDE</name>
|
|
<description>DLYPRTDE</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTDE</name>
|
|
<description>RSTDE</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2DE</name>
|
|
<description>RSTx2DE</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2DE</name>
|
|
<description>SETx2DE</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1DE</name>
|
|
<description>RSTx1DE</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xDE</name>
|
|
<description>SET1xDE</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2DE</name>
|
|
<description>CPT2DE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1DE</name>
|
|
<description>CPT1DE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDDE</name>
|
|
<description>UPDDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPDE</name>
|
|
<description>REPDE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4DE</name>
|
|
<description>CMP4DE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3DE</name>
|
|
<description>CMP3DE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2DE</name>
|
|
<description>CMP2DE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1DE</name>
|
|
<description>CMP1DE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTIE</name>
|
|
<description>DLYPRTIE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTIE</name>
|
|
<description>RSTIE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx2IE</name>
|
|
<description>RSTx2IE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETx2IE</name>
|
|
<description>SETx2IE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RSTx1IE</name>
|
|
<description>RSTx1IE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SET1xIE</name>
|
|
<description>SET1xIE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT2IE</name>
|
|
<description>CPT2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPT1IE</name>
|
|
<description>CPT1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDIE</name>
|
|
<description>UPDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REPIE</name>
|
|
<description>REPIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4IE</name>
|
|
<description>CMP4IE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3IE</name>
|
|
<description>CMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2IE</name>
|
|
<description>CMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1IE</name>
|
|
<description>CMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTFR</name>
|
|
<displayName>CNTFR</displayName>
|
|
<description>Timerx Counter Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNTx</name>
|
|
<description>Timerx Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERFR</name>
|
|
<displayName>PERFR</displayName>
|
|
<description>Timerx Period Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERx</name>
|
|
<description>Timerx Period value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REPFR</name>
|
|
<displayName>REPFR</displayName>
|
|
<description>Timerx Repetition Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1FR</name>
|
|
<displayName>CMP1FR</displayName>
|
|
<description>Timerx Compare 1 Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP1CFR</name>
|
|
<displayName>CMP1CFR</displayName>
|
|
<description>Timerx Compare 1 Compound Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REPx</name>
|
|
<description>Timerx Repetition value (aliased from HRTIM_REPx register)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1x</name>
|
|
<description>Timerx Compare 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP2FR</name>
|
|
<displayName>CMP2FR</displayName>
|
|
<description>Timerx Compare 2 Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP2x</name>
|
|
<description>Timerx Compare 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP3FR</name>
|
|
<displayName>CMP3FR</displayName>
|
|
<description>Timerx Compare 3 Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP3x</name>
|
|
<description>Timerx Compare 3 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMP4FR</name>
|
|
<displayName>CMP4FR</displayName>
|
|
<description>Timerx Compare 4 Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CMP4x</name>
|
|
<description>Timerx Compare 4 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1FR</name>
|
|
<displayName>CPT1FR</displayName>
|
|
<description>Timerx Capture 1 Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT1x</name>
|
|
<description>Timerx Capture 1 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2FR</name>
|
|
<displayName>CPT2FR</displayName>
|
|
<description>Timerx Capture 2 Register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPT2x</name>
|
|
<description>Timerx Capture 2 value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>Timerx Capture 1 Direction status</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DTFR</name>
|
|
<displayName>DTFR</displayName>
|
|
<description>Timerx Deadtime Register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DTFLKx</name>
|
|
<description>Deadtime Falling Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFSLKx</name>
|
|
<description>Deadtime Falling Sign Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTFx</name>
|
|
<description>Sign Deadtime Falling value</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTFx</name>
|
|
<description>Deadtime Falling value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRLKx</name>
|
|
<description>Deadtime Rising Lock</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRSLKx</name>
|
|
<description>Deadtime Rising Sign Lock</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTPRSC</name>
|
|
<description>Deadtime Prescaler</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDTRx</name>
|
|
<description>Sign Deadtime Rising value</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTRx</name>
|
|
<description>Deadtime Rising value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETF1R</name>
|
|
<displayName>SETF1R</displayName>
|
|
<description>Timerx Output1 Set Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>Registers update (transfer preload to active)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>Timer Event 9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>Timer Event 8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>Timer Event 7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>Timer Event 6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>Timer Event 5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>Timer Event 4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>Timer Event 3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>Timer Event 2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>Timer Event 1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master Compare 4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master Compare 3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master Compare 2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master Compare 1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master Period</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>Timer A compare 3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>Timer A compare 1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Timer A Period</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>Timer A resynchronizaton</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>Software Set trigger</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTE1R</name>
|
|
<displayName>RSTE1R</displayName>
|
|
<description>Timerx Output1 Reset Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SETF2R</name>
|
|
<displayName>SETF2R</displayName>
|
|
<description>Timerx Output2 Set Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SST</name>
|
|
<description>SST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTF2R</name>
|
|
<displayName>RSTF2R</displayName>
|
|
<description>Timerx Output2 Reset Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>EXTEVNT10</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>EXTEVNT9</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>EXTEVNT8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>EXTEVNT7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>EXTEVNT6</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>EXTEVNT5</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>EXTEVNT4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>EXTEVNT3</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>EXTEVNT2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>EXTEVNT1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT9</name>
|
|
<description>TIMEVNT9</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT8</name>
|
|
<description>TIMEVNT8</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT7</name>
|
|
<description>TIMEVNT7</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT6</name>
|
|
<description>TIMEVNT6</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT5</name>
|
|
<description>TIMEVNT5</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT4</name>
|
|
<description>TIMEVNT4</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT3</name>
|
|
<description>TIMEVNT3</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT2</name>
|
|
<description>TIMEVNT2</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMEVNT1</name>
|
|
<description>TIMEVNT1</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>MSTPER</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>CMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP3</name>
|
|
<description>CMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>CMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP1</name>
|
|
<description>CMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>PER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESYNC</name>
|
|
<description>RESYNC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRT</name>
|
|
<description>SRT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFFR1</name>
|
|
<displayName>EEFFR1</displayName>
|
|
<description>Timerx External Event Filtering Register 1</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE5FLTR</name>
|
|
<description>External Event 5 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5LTCH</name>
|
|
<description>External Event 5 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4FLTR</name>
|
|
<description>External Event 4 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4LTCH</name>
|
|
<description>External Event 4 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3FLTR</name>
|
|
<description>External Event 3 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3LTCH</name>
|
|
<description>External Event 3 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2FLTR</name>
|
|
<description>External Event 2 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2LTCH</name>
|
|
<description>External Event 2 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1FLTR</name>
|
|
<description>External Event 1 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1LTCH</name>
|
|
<description>External Event 1 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EEFFR2</name>
|
|
<displayName>EEFFR2</displayName>
|
|
<description>Timerx External Event Filtering Register 2</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE10FLTR</name>
|
|
<description>External Event 10 filter</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10LTCH</name>
|
|
<description>External Event 10 latch</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9FLTR</name>
|
|
<description>External Event 9 filter</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9LTCH</name>
|
|
<description>External Event 9 latch</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8FLTR</name>
|
|
<description>External Event 8 filter</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8LTCH</name>
|
|
<description>External Event 8 latch</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7FLTR</name>
|
|
<description>External Event 7 filter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7LTCH</name>
|
|
<description>External Event 7 latch</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6FLTR</name>
|
|
<description>External Event 6 filter</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6LTCH</name>
|
|
<description>External Event 6 latch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RSTFR</name>
|
|
<displayName>RSTFR</displayName>
|
|
<description>TimerA Reset Register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMFCPM2</name>
|
|
<description>Timer F Compare 2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP4</name>
|
|
<description>Timer D Compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP4</name>
|
|
<description>Timer C Compare 4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP4</name>
|
|
<description>Timer B Compare 4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP4</name>
|
|
<description>Timer A Compare 4</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT10</name>
|
|
<description>External Event 10</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT9</name>
|
|
<description>External Event 9</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT8</name>
|
|
<description>External Event 8</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT7</name>
|
|
<description>External Event 7</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT6</name>
|
|
<description>External Event 6</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT5</name>
|
|
<description>External Event 5</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT4</name>
|
|
<description>External Event 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT3</name>
|
|
<description>External Event 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT2</name>
|
|
<description>External Event 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEVNT1</name>
|
|
<description>External Event 1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>Master compare 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>Master compare 3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>Master compare 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>Master compare 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTPER</name>
|
|
<description>Master timer Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP4</name>
|
|
<description>Timer A compare 4 reset</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CMP2</name>
|
|
<description>Timer A compare 2 reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDT</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMFCMP1</name>
|
|
<description>Timer A Update reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CHPFR</name>
|
|
<displayName>CHPFR</displayName>
|
|
<description>Timerx Chopper Register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRTPW</name>
|
|
<description>STRTPW</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPDTY</name>
|
|
<description>Timerx chopper duty cycle value</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHPFRQ</name>
|
|
<description>Timerx carrier frequency value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT1FCR</name>
|
|
<displayName>CPT1FCR</displayName>
|
|
<description>Timerx Capture 2 Control Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>TECMP2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>TECMP1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>TE1RST</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>TE1SET</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPT2FCR</name>
|
|
<displayName>CPT2FCR</displayName>
|
|
<description>CPT2xCR</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>TECMP2</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>TECMP1</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1RST</name>
|
|
<description>TE1RST</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1SET</name>
|
|
<description>TE1SET</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>Timer D Compare 2</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>Timer D Compare 1</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1RST</name>
|
|
<description>Timer D output 1 Reset</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1SET</name>
|
|
<description>Timer D output 1 Set</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>Timer C Compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>Timer C Compare 1</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1RST</name>
|
|
<description>Timer C output 1 Reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1SET</name>
|
|
<description>Timer C output 1 Set</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>Timer B Compare 2</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>Timer B Compare 1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1RST</name>
|
|
<description>Timer B output 1 Reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1SET</name>
|
|
<description>Timer B output 1 Set</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>Timer A Compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>Timer A Compare 1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1RST</name>
|
|
<description>Timer A output 1 Reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1SET</name>
|
|
<description>Timer A output 1 Set</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV10CPT</name>
|
|
<description>External Event 10 Capture</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV9CPT</name>
|
|
<description>External Event 9 Capture</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV8CPT</name>
|
|
<description>External Event 8 Capture</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV7CPT</name>
|
|
<description>External Event 7 Capture</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV6CPT</name>
|
|
<description>External Event 6 Capture</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV5CPT</name>
|
|
<description>External Event 5 Capture</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV4CPT</name>
|
|
<description>External Event 4 Capture</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV3CPT</name>
|
|
<description>External Event 3 Capture</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV2CPT</name>
|
|
<description>External Event 2 Capture</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXEV1CPT</name>
|
|
<description>External Event 1 Capture</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDPCPT</name>
|
|
<description>Update Capture</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWCPT</name>
|
|
<description>Software Capture</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTFR</name>
|
|
<displayName>OUTFR</displayName>
|
|
<description>Timerx Output Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIDL2</name>
|
|
<description>Output 2 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP2</name>
|
|
<description>Output 2 Chopper enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT2</name>
|
|
<description>Output 2 Fault state</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES2</name>
|
|
<description>Output 2 Idle State</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM2</name>
|
|
<description>Output 2 Idle mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL2</name>
|
|
<description>Output 2 polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAR</name>
|
|
<description>Balanced Idle Automatic Resume</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRT</name>
|
|
<description>Delayed Protection</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYPRTEN</name>
|
|
<description>Delayed Protection Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTEN</name>
|
|
<description>Deadtime enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIDL1</name>
|
|
<description>Output 1 Deadtime upon burst mode Idle entry</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CHP1</name>
|
|
<description>Output 1 Chopper enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FAULT1</name>
|
|
<description>Output 1 Fault state</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLES1</name>
|
|
<description>Output 1 Idle State</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEM1</name>
|
|
<description>Output 1 Idle mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POL1</name>
|
|
<description>Output 1 polarity</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTFR</name>
|
|
<displayName>FLTFR</displayName>
|
|
<description>Timerx Fault Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTLCK</name>
|
|
<description>Fault sources Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6EN</name>
|
|
<description>Fault 6 enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5EN</name>
|
|
<description>Fault 5 enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4EN</name>
|
|
<description>Fault 4 enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3EN</name>
|
|
<description>Fault 3 enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2EN</name>
|
|
<description>Fault 2 enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1EN</name>
|
|
<description>Fault 1 enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TIMFCR2</name>
|
|
<displayName>TIMFCR2</displayName>
|
|
<description>HRTIM Timerx Control Register 2</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRGHLF</name>
|
|
<description>Triggered-half mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP3</name>
|
|
<description>Greater than Compare 3 PWM mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GTCMP1</name>
|
|
<description>Greater than Compare 1 PWM mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEROM</name>
|
|
<description>Fault and Event Roll-Over Mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMROM</name>
|
|
<description>Burst Mode Roll-Over Mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADROM</name>
|
|
<description>ADC Roll-Over Mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OUTROM</name>
|
|
<description>Output Roll-Over Mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>Roll-Over Mode</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UDM</name>
|
|
<description>Up-Down Mode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDR</name>
|
|
<description>Dual Channel DAC Reset trigger</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDS</name>
|
|
<description>Dual Channel DAC Step trigger</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCDE</name>
|
|
<description>Dual Channel DAC trigger enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FEEFR3</name>
|
|
<displayName>FEEFR3</displayName>
|
|
<description>HRTIM Timerx External Event Filtering Register 3</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EEVACNT</name>
|
|
<description>External Event A counter</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVASEL</name>
|
|
<description>External Event A Selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVARSTM</name>
|
|
<description>External Event A Reset Mode</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACRES</name>
|
|
<description>External Event A Counter Reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVACE</name>
|
|
<description>External Event A Counter Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>HRTIM_Common</name>
|
|
<description>High Resolution Timer: Common functions</description>
|
|
<groupName>HRTIM</groupName>
|
|
<baseAddress>0x40016B80</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x91</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>HRTIM_TIM_FLT_IRQn</name>
|
|
<description>HRTIM_TIM_FLT_IRQn</description>
|
|
<value>73</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Control Register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AD4USRC</name>
|
|
<description>ADC Trigger 4 Update Source</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD3USRC</name>
|
|
<description>ADC Trigger 3 Update Source</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2USRC</name>
|
|
<description>ADC Trigger 2 Update Source</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1USRC</name>
|
|
<description>ADC Trigger 1 Update Source</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFUDIS</name>
|
|
<description>Timer f Update Disable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEUDIS</name>
|
|
<description>Timer E Update Disable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDUDIS</name>
|
|
<description>Timer D Update Disable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCUDIS</name>
|
|
<description>Timer C Update Disable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBUDIS</name>
|
|
<description>Timer B Update Disable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAUDIS</name>
|
|
<description>Timer A Update Disable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUDIS</name>
|
|
<description>Master Update Disable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Control Register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWPF</name>
|
|
<description>Swap Timer F outputs</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWPE</name>
|
|
<description>Swap Timer E outputs</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWPD</name>
|
|
<description>Swap Timer D outputs</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWPC</name>
|
|
<description>Swap Timer C outputs</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWPB</name>
|
|
<description>Swap Timer B outputs</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWPA</name>
|
|
<description>Swap Timer A outputs</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFRST</name>
|
|
<description>Timer f counter software reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TERST</name>
|
|
<description>Timer E counter software reset</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDRST</name>
|
|
<description>Timer D counter software reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCRST</name>
|
|
<description>Timer C counter software reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBRST</name>
|
|
<description>Timer B counter software reset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TARST</name>
|
|
<description>Timer A counter software reset</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MRST</name>
|
|
<description>Master Counter software reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFSWU</name>
|
|
<description>Timer f Software Update</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TESWU</name>
|
|
<description>Timer E Software Update</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDSWU</name>
|
|
<description>Timer D Software Update</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCSWU</name>
|
|
<description>Timer C Software Update</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBSWU</name>
|
|
<description>Timer B Software Update</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TASWU</name>
|
|
<description>Timer A Software update</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSWU</name>
|
|
<description>Master Timer Software update</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt Status Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMPER</name>
|
|
<description>Burst mode Period Interrupt Flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLLRDY</name>
|
|
<description>DLL Ready Interrupt Flag</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6</name>
|
|
<description>Fault 6 Interrupt Flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSFLT</name>
|
|
<description>System Fault Interrupt Flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5</name>
|
|
<description>Fault 5 Interrupt Flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4</name>
|
|
<description>Fault 4 Interrupt Flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3</name>
|
|
<description>Fault 3 Interrupt Flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2</name>
|
|
<description>Fault 2 Interrupt Flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1</name>
|
|
<description>Fault 1 Interrupt Flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMPERC</name>
|
|
<description>Burst mode period flag Clear</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLLRDYC</name>
|
|
<description>DLL Ready Interrupt flag Clear</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6C</name>
|
|
<description>Fault 6 Interrupt Flag Clear</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSFLTC</name>
|
|
<description>System Fault Interrupt Flag Clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5C</name>
|
|
<description>Fault 5 Interrupt Flag Clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4C</name>
|
|
<description>Fault 4 Interrupt Flag Clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3C</name>
|
|
<description>Fault 3 Interrupt Flag Clear</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2C</name>
|
|
<description>Fault 2 Interrupt Flag Clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1C</name>
|
|
<description>Fault 1 Interrupt Flag Clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMPERIE</name>
|
|
<description>Burst mode period Interrupt Enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLLRDYIE</name>
|
|
<description>DLL Ready Interrupt Enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6IE</name>
|
|
<description>Fault 6 Interrupt Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSFLTE</name>
|
|
<description>System Fault Interrupt Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5IE</name>
|
|
<description>Fault 5 Interrupt Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4IE</name>
|
|
<description>Fault 4 Interrupt Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3IE</name>
|
|
<description>Fault 3 Interrupt Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2IE</name>
|
|
<description>Fault 2 Interrupt Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1IE</name>
|
|
<description>Fault 1 Interrupt Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OENR</name>
|
|
<displayName>OENR</displayName>
|
|
<description>Output Enable Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF2ODS</name>
|
|
<description>Timer F Output 2 disable status</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1ODS</name>
|
|
<description>Timer F Output 1 disable status</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE2OEN</name>
|
|
<description>Timer E Output 2 Enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1OEN</name>
|
|
<description>Timer E Output 1 Enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD2OEN</name>
|
|
<description>Timer D Output 2 Enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1OEN</name>
|
|
<description>Timer D Output 1 Enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2OEN</name>
|
|
<description>Timer C Output 2 Enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1OEN</name>
|
|
<description>Timer C Output 1 Enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB2OEN</name>
|
|
<description>Timer B Output 2 Enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1OEN</name>
|
|
<description>Timer B Output 1 Enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA2OEN</name>
|
|
<description>Timer A Output 2 Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1OEN</name>
|
|
<description>Timer A Output 1 Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODISR</name>
|
|
<displayName>ODISR</displayName>
|
|
<description>ODISR</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF2ODIS</name>
|
|
<description>TF2ODIS</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1ODIS</name>
|
|
<description>TF1ODIS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE2ODIS</name>
|
|
<description>TE2ODIS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1ODIS</name>
|
|
<description>TE1ODIS</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD2ODIS</name>
|
|
<description>TD2ODIS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1ODIS</name>
|
|
<description>TD1ODIS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2ODIS</name>
|
|
<description>TC2ODIS</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1ODIS</name>
|
|
<description>TC1ODIS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB2ODIS</name>
|
|
<description>TB2ODIS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1ODIS</name>
|
|
<description>TB1ODIS</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA2ODIS</name>
|
|
<description>TA2ODIS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1ODIS</name>
|
|
<description>TA1ODIS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODSR</name>
|
|
<displayName>ODSR</displayName>
|
|
<description>Output Disable Status Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TF2ODS</name>
|
|
<description>TF2ODS</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TF1ODS</name>
|
|
<description>TF1ODS</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE2ODS</name>
|
|
<description>Timer E Output 2 disable status</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE1ODS</name>
|
|
<description>Timer E Output 1 disable status</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD2ODS</name>
|
|
<description>Timer D Output 2 disable status</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TD1ODS</name>
|
|
<description>Timer D Output 1 disable status</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC2ODS</name>
|
|
<description>Timer C Output 2 disable status</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC1ODS</name>
|
|
<description>Timer C Output 1 disable status</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB2ODS</name>
|
|
<description>Timer B Output 2 disable status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TB1ODS</name>
|
|
<description>Timer B Output 1 disable status</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA2ODS</name>
|
|
<description>Timer A Output 2 disable status</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TA1ODS</name>
|
|
<description>Timer A Output 1 disable status</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMCR</name>
|
|
<displayName>BMCR</displayName>
|
|
<description>Burst Mode Control Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMSTAT</name>
|
|
<description>Burst Mode Status</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFBM</name>
|
|
<description>Timer f Burst Mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEBM</name>
|
|
<description>Timer E Burst Mode</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDBM</name>
|
|
<description>Timer D Burst Mode</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCBM</name>
|
|
<description>Timer C Burst Mode</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBBM</name>
|
|
<description>Timer B Burst Mode</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TABM</name>
|
|
<description>Timer A Burst Mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MTBM</name>
|
|
<description>Master Timer Burst Mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMPREN</name>
|
|
<description>Burst Mode Preload Enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMPRSC</name>
|
|
<description>Burst Mode Prescaler</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMCLK</name>
|
|
<description>Burst Mode Clock source</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BMOM</name>
|
|
<description>Burst Mode operating mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BME</name>
|
|
<description>Burst Mode enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMTRG</name>
|
|
<displayName>BMTRG</displayName>
|
|
<description>BMTRG</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OCHPEV</name>
|
|
<description>OCHPEV</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEV8</name>
|
|
<description>EEV8</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEV7</name>
|
|
<description>EEV7</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDEEV8</name>
|
|
<description>TDEEV8</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDEEV7</name>
|
|
<description>TDEEV7</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP2</name>
|
|
<description>TECMP2</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TECMP1</name>
|
|
<description>TECMP1</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEREP</name>
|
|
<description>TEREP</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TERST</name>
|
|
<description>TERST</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP2</name>
|
|
<description>TDCMP2</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCMP1</name>
|
|
<description>TDCMP1</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDREP</name>
|
|
<description>TDREP</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDRST</name>
|
|
<description>TDRST</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP2</name>
|
|
<description>TCCMP2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCCMP1</name>
|
|
<description>TCCMP1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCREP</name>
|
|
<description>TCREP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCRST</name>
|
|
<description>TCRST</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP2</name>
|
|
<description>TBCMP2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBCMP1</name>
|
|
<description>TBCMP1</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBREP</name>
|
|
<description>TBREP</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TBRST</name>
|
|
<description>TBRST</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP2</name>
|
|
<description>TACMP2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TACMP1</name>
|
|
<description>TACMP1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAREP</name>
|
|
<description>TAREP</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TARST</name>
|
|
<description>TARST</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP4</name>
|
|
<description>MSTCMP4</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP3</name>
|
|
<description>MSTCMP3</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP2</name>
|
|
<description>MSTCMP2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTCMP1</name>
|
|
<description>MSTCMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTREP</name>
|
|
<description>MSTREP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTRST</name>
|
|
<description>MSTRST</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>SW</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMCMPR</name>
|
|
<displayName>BMCMPR</displayName>
|
|
<description>BMCMPR</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMCMP</name>
|
|
<description>BMCMP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BMPER</name>
|
|
<displayName>BMPER</displayName>
|
|
<description>Burst Mode Period Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BMPER</name>
|
|
<description>Burst mode Period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EECR1</name>
|
|
<displayName>EECR1</displayName>
|
|
<description>Timer External Event Control Register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE5FAST</name>
|
|
<description>External Event 5 Fast mode</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5SNS</name>
|
|
<description>External Event 5 Sensitivity</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5POL</name>
|
|
<description>External Event 5 Polarity</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE5SRC</name>
|
|
<description>External Event 5 Source</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4FAST</name>
|
|
<description>External Event 4 Fast mode</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4SNS</name>
|
|
<description>External Event 4 Sensitivity</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4POL</name>
|
|
<description>External Event 4 Polarity</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE4SRC</name>
|
|
<description>External Event 4 Source</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3FAST</name>
|
|
<description>External Event 3 Fast mode</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3SNS</name>
|
|
<description>External Event 3 Sensitivity</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3POL</name>
|
|
<description>External Event 3 Polarity</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE3SRC</name>
|
|
<description>External Event 3 Source</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2FAST</name>
|
|
<description>External Event 2 Fast mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2SNS</name>
|
|
<description>External Event 2 Sensitivity</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2POL</name>
|
|
<description>External Event 2 Polarity</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE2SRC</name>
|
|
<description>External Event 2 Source</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1FAST</name>
|
|
<description>External Event 1 Fast mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1SNS</name>
|
|
<description>External Event 1 Sensitivity</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1POL</name>
|
|
<description>External Event 1 Polarity</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE1SRC</name>
|
|
<description>External Event 1 Source</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EECR2</name>
|
|
<displayName>EECR2</displayName>
|
|
<description>Timer External Event Control Register 2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE6SRC</name>
|
|
<description>EE6SRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6POL</name>
|
|
<description>EE6POL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE6SNS</name>
|
|
<description>EE6SNS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7SRC</name>
|
|
<description>EE7SRC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7POL</name>
|
|
<description>EE7POL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7SNS</name>
|
|
<description>EE7SNS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8SRC</name>
|
|
<description>EE8SRC</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8POL</name>
|
|
<description>EE8POL</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8SNS</name>
|
|
<description>EE8SNS</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9SRC</name>
|
|
<description>EE9SRC</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9POL</name>
|
|
<description>EE9POL</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9SNS</name>
|
|
<description>EE9SNS</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10SRC</name>
|
|
<description>EE10SRC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10POL</name>
|
|
<description>EE10POL</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10SNS</name>
|
|
<description>EE10SNS</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EECR3</name>
|
|
<displayName>EECR3</displayName>
|
|
<description>Timer External Event Control Register 3</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EE6F</name>
|
|
<description>EE6F</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE7F</name>
|
|
<description>EE7F</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE8F</name>
|
|
<description>EE8F</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE9F</name>
|
|
<description>EE9F</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EE10F</name>
|
|
<description>EE10F</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EEVSD</name>
|
|
<description>EEVSD</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC1R</name>
|
|
<displayName>ADC1R</displayName>
|
|
<description>ADC Trigger 1 Register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AD1TEPER</name>
|
|
<description>ADC trigger 1 on Timer E Period</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TEC4</name>
|
|
<description>ADC trigger 1 on Timer E compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TEC3</name>
|
|
<description>ADC trigger 1 on Timer E compare 3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TEC2</name>
|
|
<description>ADC trigger 1 on Timer E compare 2</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDPER</name>
|
|
<description>ADC trigger 1 on Timer D Period</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDC4</name>
|
|
<description>ADC trigger 1 on Timer D compare 4</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDC3</name>
|
|
<description>ADC trigger 1 on Timer D compare 3</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDC2</name>
|
|
<description>ADC trigger 1 on Timer D compare 2</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCPER</name>
|
|
<description>ADC trigger 1 on Timer C Period</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCC4</name>
|
|
<description>ADC trigger 1 on Timer C compare 4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCC3</name>
|
|
<description>ADC trigger 1 on Timer C compare 3</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCC2</name>
|
|
<description>ADC trigger 1 on Timer C compare 2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBRST</name>
|
|
<description>ADC trigger 1 on Timer B Reset</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBPER</name>
|
|
<description>ADC trigger 1 on Timer B Period</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBC4</name>
|
|
<description>ADC trigger 1 on Timer B compare 4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBC3</name>
|
|
<description>ADC trigger 1 on Timer B compare 3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBC2</name>
|
|
<description>ADC trigger 1 on Timer B compare 2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TARST</name>
|
|
<description>ADC trigger 1 on Timer A Reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAPER</name>
|
|
<description>ADC trigger 1 on Timer A Period</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAC4</name>
|
|
<description>ADC trigger 1 on Timer A compare 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAC3</name>
|
|
<description>ADC trigger 1 on Timer A compare 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAC2</name>
|
|
<description>ADC trigger 1 on Timer A compare 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV5</name>
|
|
<description>ADC trigger 1 on External Event 5</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV4</name>
|
|
<description>ADC trigger 1 on External Event 4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV3</name>
|
|
<description>ADC trigger 1 on External Event 3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV2</name>
|
|
<description>ADC trigger 1 on External Event 2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV1</name>
|
|
<description>ADC trigger 1 on External Event 1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MPER</name>
|
|
<description>ADC trigger 1 on Master Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC4</name>
|
|
<description>ADC trigger 1 on Master Compare 4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC3</name>
|
|
<description>ADC trigger 1 on Master Compare 3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC2</name>
|
|
<description>ADC trigger 1 on Master Compare 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC1</name>
|
|
<description>ADC trigger 1 on Master Compare 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC2R</name>
|
|
<displayName>ADC2R</displayName>
|
|
<description>ADC Trigger 2 Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AD2TERST</name>
|
|
<description>ADC trigger 2 on Timer E Reset</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TEC4</name>
|
|
<description>ADC trigger 2 on Timer E compare 4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TEC3</name>
|
|
<description>ADC trigger 2 on Timer E compare 3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TEC2</name>
|
|
<description>ADC trigger 2 on Timer E compare 2</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDRST</name>
|
|
<description>ADC trigger 2 on Timer D Reset</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDPER</name>
|
|
<description>ADC trigger 2 on Timer D Period</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDC4</name>
|
|
<description>ADC trigger 2 on Timer D compare 4</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDC3</name>
|
|
<description>ADC trigger 2 on Timer D compare 3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDC2</name>
|
|
<description>ADC trigger 2 on Timer D compare 2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCRST</name>
|
|
<description>ADC trigger 2 on Timer C Reset</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCPER</name>
|
|
<description>ADC trigger 2 on Timer C Period</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCC4</name>
|
|
<description>ADC trigger 2 on Timer C compare 4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCC3</name>
|
|
<description>ADC trigger 2 on Timer C compare 3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCC2</name>
|
|
<description>ADC trigger 2 on Timer C compare 2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBPER</name>
|
|
<description>ADC trigger 2 on Timer B Period</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBC4</name>
|
|
<description>ADC trigger 2 on Timer B compare 4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBC3</name>
|
|
<description>ADC trigger 2 on Timer B compare 3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBC2</name>
|
|
<description>ADC trigger 2 on Timer B compare 2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAPER</name>
|
|
<description>ADC trigger 2 on Timer A Period</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAC4</name>
|
|
<description>ADC trigger 2 on Timer A compare 4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAC3</name>
|
|
<description>ADC trigger 2 on Timer A compare 3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAC2</name>
|
|
<description>ADC trigger 2 on Timer A compare 2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV10</name>
|
|
<description>ADC trigger 2 on External Event 10</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV9</name>
|
|
<description>ADC trigger 2 on External Event 9</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV8</name>
|
|
<description>ADC trigger 2 on External Event 8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV7</name>
|
|
<description>ADC trigger 2 on External Event 7</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV6</name>
|
|
<description>ADC trigger 2 on External Event 6</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MPER</name>
|
|
<description>ADC trigger 2 on Master Period</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC4</name>
|
|
<description>ADC trigger 2 on Master Compare 4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC3</name>
|
|
<description>ADC trigger 2 on Master Compare 3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC2</name>
|
|
<description>ADC trigger 2 on Master Compare 2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC1</name>
|
|
<description>ADC trigger 2 on Master Compare 1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC3R</name>
|
|
<displayName>ADC3R</displayName>
|
|
<description>ADC Trigger 3 Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AD1TEPER</name>
|
|
<description>AD1TEPER</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TEC4</name>
|
|
<description>AD1TEC4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TEC3</name>
|
|
<description>AD1TEC3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TEC2</name>
|
|
<description>AD1TEC2</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDPER</name>
|
|
<description>AD1TDPER</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDC4</name>
|
|
<description>AD1TDC4</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDC3</name>
|
|
<description>AD1TDC3</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TDC2</name>
|
|
<description>AD1TDC2</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCPER</name>
|
|
<description>AD1TCPER</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCC4</name>
|
|
<description>AD1TCC4</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCC3</name>
|
|
<description>AD1TCC3</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TCC2</name>
|
|
<description>AD1TCC2</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBRST</name>
|
|
<description>AD1TBRST</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBPER</name>
|
|
<description>AD1TBPER</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBC4</name>
|
|
<description>AD1TBC4</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBC3</name>
|
|
<description>AD1TBC3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TBC2</name>
|
|
<description>AD1TBC2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TARST</name>
|
|
<description>AD1TARST</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAPER</name>
|
|
<description>AD1TAPER</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAC4</name>
|
|
<description>AD1TAC4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAC3</name>
|
|
<description>AD1TAC3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1TAC2</name>
|
|
<description>AD1TAC2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV5</name>
|
|
<description>AD1EEV5</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV4</name>
|
|
<description>AD1EEV4</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV3</name>
|
|
<description>AD1EEV3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV2</name>
|
|
<description>AD1EEV2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1EEV1</name>
|
|
<description>AD1EEV1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MPER</name>
|
|
<description>AD1MPER</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC4</name>
|
|
<description>AD1MC4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC3</name>
|
|
<description>AD1MC3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC2</name>
|
|
<description>AD1MC2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD1MC1</name>
|
|
<description>AD1MC1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADC4R</name>
|
|
<displayName>ADC4R</displayName>
|
|
<description>ADC Trigger 4 Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AD2TERST</name>
|
|
<description>AD2TERST</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TEC4</name>
|
|
<description>AD2TEC4</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TEC3</name>
|
|
<description>AD2TEC3</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TEC2</name>
|
|
<description>AD2TEC2</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDRST</name>
|
|
<description>AD2TDRST</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDPER</name>
|
|
<description>AD2TDPER</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDC4</name>
|
|
<description>AD2TDC4</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDC3</name>
|
|
<description>AD2TDC3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TDC2</name>
|
|
<description>AD2TDC2</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCRST</name>
|
|
<description>AD2TCRST</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCPER</name>
|
|
<description>AD2TCPER</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCC4</name>
|
|
<description>AD2TCC4</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCC3</name>
|
|
<description>AD2TCC3</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TCC2</name>
|
|
<description>AD2TCC2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBPER</name>
|
|
<description>AD2TBPER</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBC4</name>
|
|
<description>AD2TBC4</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBC3</name>
|
|
<description>AD2TBC3</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TBC2</name>
|
|
<description>AD2TBC2</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAPER</name>
|
|
<description>AD2TAPER</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAC4</name>
|
|
<description>AD2TAC4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAC3</name>
|
|
<description>AD2TAC3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2TAC2</name>
|
|
<description>AD2TAC2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV10</name>
|
|
<description>AD2EEV10</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV9</name>
|
|
<description>AD2EEV9</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV8</name>
|
|
<description>AD2EEV8</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV7</name>
|
|
<description>AD2EEV7</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2EEV6</name>
|
|
<description>AD2EEV6</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MPER</name>
|
|
<description>AD2MPER</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC4</name>
|
|
<description>AD2MC4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC3</name>
|
|
<description>AD2MC3</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC2</name>
|
|
<description>AD2MC2</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD2MC1</name>
|
|
<description>AD2MC1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLLCR</name>
|
|
<displayName>DLLCR</displayName>
|
|
<description>DLL Control Register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALRTE</name>
|
|
<description>DLL Calibration rate</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALEN</name>
|
|
<description>DLL Calibration Enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>DLL Calibration Start</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTINR1</name>
|
|
<displayName>FLTINR1</displayName>
|
|
<description>HRTIM Fault Input Register 1</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLT4LCK</name>
|
|
<description>FLT4LCK</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4F</name>
|
|
<description>FLT4F</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4SRC</name>
|
|
<description>FLT4SRC</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4P</name>
|
|
<description>FLT4P</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4E</name>
|
|
<description>FLT4E</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3LCK</name>
|
|
<description>FLT3LCK</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3F</name>
|
|
<description>FLT3F</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3SRC</name>
|
|
<description>FLT3SRC</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3P</name>
|
|
<description>FLT3P</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3E</name>
|
|
<description>FLT3E</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2LCK</name>
|
|
<description>FLT2LCK</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2F</name>
|
|
<description>FLT2F</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2SRC</name>
|
|
<description>FLT2SRC</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2P</name>
|
|
<description>FLT2P</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2E</name>
|
|
<description>FLT2E</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1LCK</name>
|
|
<description>FLT1LCK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1F</name>
|
|
<description>FLT1F</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1SRC</name>
|
|
<description>FLT1SRC</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1P</name>
|
|
<description>FLT1P</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1E</name>
|
|
<description>FLT1E</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTINR2</name>
|
|
<displayName>FLTINR2</displayName>
|
|
<description>HRTIM Fault Input Register 2</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTSD</name>
|
|
<description>FLTSD</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6SRC_1</name>
|
|
<description>FLT6SRC</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5SRC_1</name>
|
|
<description>FLT5SRC_1</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4SRC_1</name>
|
|
<description>FLT4SRC_1</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3SRC_1</name>
|
|
<description>FLT3SRC_1</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2SRC_1</name>
|
|
<description>FLT2SRC_1</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1SRC_1</name>
|
|
<description>FLT1SRC_1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6LCK</name>
|
|
<description>FLT6LCK</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6F</name>
|
|
<description>FLT6F</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6SRC_0</name>
|
|
<description>FLT6F</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6P</name>
|
|
<description>FLT6P</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6E</name>
|
|
<description>FLT6E</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5LCK</name>
|
|
<description>FLT5LCK</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5F</name>
|
|
<description>FLT5F</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5SRC</name>
|
|
<description>FLT5SRC</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5P</name>
|
|
<description>FLT5P</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5E</name>
|
|
<description>FLT5E</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDMUPDR</name>
|
|
<displayName>BDMUPDR</displayName>
|
|
<description>BDMUPDR</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCMP4</name>
|
|
<description>MCMP4</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP3</name>
|
|
<description>MCMP3</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP2</name>
|
|
<description>MCMP2</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCMP1</name>
|
|
<description>MCMP1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MREP</name>
|
|
<description>MREP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MPER</name>
|
|
<description>MPER</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCNT</name>
|
|
<description>MCNT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDIER</name>
|
|
<description>MDIER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MICR</name>
|
|
<description>MICR</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCR</name>
|
|
<description>MCR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTAUPR</name>
|
|
<displayName>BDTAUPR</displayName>
|
|
<description>Burst DMA Timerx update Register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMxEEFR3</name>
|
|
<description>TIMxEEFR3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR2</name>
|
|
<description>TIMxCR2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxFLTR</name>
|
|
<description>HRTIM_FLTxR register update enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxOUTR</name>
|
|
<description>HRTIM_OUTxR register update enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCHPR</name>
|
|
<description>HRTIM_CHPxR register update enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRSTR</name>
|
|
<description>HRTIM_RSTxR register update enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR2</name>
|
|
<description>HRTIM_EEFxR2 register update enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR1</name>
|
|
<description>HRTIM_EEFxR1 register update enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST2R</name>
|
|
<description>HRTIM_RST2xR register update enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET2R</name>
|
|
<description>HRTIM_SET2xR register update enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST1R</name>
|
|
<description>HRTIM_RST1xR register update enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET1R</name>
|
|
<description>HRTIM_SET1xR register update enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMx_DTxR</name>
|
|
<description>HRTIM_DTxR register update enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP4</name>
|
|
<description>HRTIM_CMP4xR register update enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP3</name>
|
|
<description>HRTIM_CMP3xR register update enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP2</name>
|
|
<description>HRTIM_CMP2xR register update enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP1</name>
|
|
<description>HRTIM_CMP1xR register update enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxREP</name>
|
|
<description>HRTIM_REPxR register update enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxPER</name>
|
|
<description>HRTIM_PERxR register update enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCNT</name>
|
|
<description>HRTIM_CNTxR register update enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxDIER</name>
|
|
<description>HRTIM_TIMxDIER register update enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxICR</name>
|
|
<description>HRTIM_TIMxICR register update enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR</name>
|
|
<description>HRTIM_TIMxCR register update enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTBUPR</name>
|
|
<displayName>BDTBUPR</displayName>
|
|
<description>Burst DMA Timerx update Register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMxEEFR3</name>
|
|
<description>TIMxEEFR3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR2</name>
|
|
<description>TIMxCR2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxFLTR</name>
|
|
<description>HRTIM_FLTxR register update enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxOUTR</name>
|
|
<description>HRTIM_OUTxR register update enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCHPR</name>
|
|
<description>HRTIM_CHPxR register update enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRSTR</name>
|
|
<description>HRTIM_RSTxR register update enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR2</name>
|
|
<description>HRTIM_EEFxR2 register update enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR1</name>
|
|
<description>HRTIM_EEFxR1 register update enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST2R</name>
|
|
<description>HRTIM_RST2xR register update enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET2R</name>
|
|
<description>HRTIM_SET2xR register update enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST1R</name>
|
|
<description>HRTIM_RST1xR register update enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET1R</name>
|
|
<description>HRTIM_SET1xR register update enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMx_DTxR</name>
|
|
<description>HRTIM_DTxR register update enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP4</name>
|
|
<description>HRTIM_CMP4xR register update enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP3</name>
|
|
<description>HRTIM_CMP3xR register update enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP2</name>
|
|
<description>HRTIM_CMP2xR register update enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP1</name>
|
|
<description>HRTIM_CMP1xR register update enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxREP</name>
|
|
<description>HRTIM_REPxR register update enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxPER</name>
|
|
<description>HRTIM_PERxR register update enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCNT</name>
|
|
<description>HRTIM_CNTxR register update enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxDIER</name>
|
|
<description>HRTIM_TIMxDIER register update enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxICR</name>
|
|
<description>HRTIM_TIMxICR register update enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR</name>
|
|
<description>HRTIM_TIMxCR register update enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTCUPR</name>
|
|
<displayName>BDTCUPR</displayName>
|
|
<description>Burst DMA Timerx update Register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMxEEFR3</name>
|
|
<description>TIMxEEFR3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR2</name>
|
|
<description>TIMxCR2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxFLTR</name>
|
|
<description>HRTIM_FLTxR register update enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxOUTR</name>
|
|
<description>HRTIM_OUTxR register update enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCHPR</name>
|
|
<description>HRTIM_CHPxR register update enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRSTR</name>
|
|
<description>HRTIM_RSTxR register update enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR2</name>
|
|
<description>HRTIM_EEFxR2 register update enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR1</name>
|
|
<description>HRTIM_EEFxR1 register update enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST2R</name>
|
|
<description>HRTIM_RST2xR register update enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET2R</name>
|
|
<description>HRTIM_SET2xR register update enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST1R</name>
|
|
<description>HRTIM_RST1xR register update enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET1R</name>
|
|
<description>HRTIM_SET1xR register update enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMx_DTxR</name>
|
|
<description>HRTIM_DTxR register update enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP4</name>
|
|
<description>HRTIM_CMP4xR register update enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP3</name>
|
|
<description>HRTIM_CMP3xR register update enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP2</name>
|
|
<description>HRTIM_CMP2xR register update enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP1</name>
|
|
<description>HRTIM_CMP1xR register update enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxREP</name>
|
|
<description>HRTIM_REPxR register update enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxPER</name>
|
|
<description>HRTIM_PERxR register update enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCNT</name>
|
|
<description>HRTIM_CNTxR register update enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxDIER</name>
|
|
<description>HRTIM_TIMxDIER register update enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxICR</name>
|
|
<description>HRTIM_TIMxICR register update enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR</name>
|
|
<description>HRTIM_TIMxCR register update enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTDUPR</name>
|
|
<displayName>BDTDUPR</displayName>
|
|
<description>Burst DMA Timerx update Register</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMxEEFR3</name>
|
|
<description>TIMxEEFR3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR2</name>
|
|
<description>TIMxCR2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxFLTR</name>
|
|
<description>HRTIM_FLTxR register update enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxOUTR</name>
|
|
<description>HRTIM_OUTxR register update enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCHPR</name>
|
|
<description>HRTIM_CHPxR register update enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRSTR</name>
|
|
<description>HRTIM_RSTxR register update enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR2</name>
|
|
<description>HRTIM_EEFxR2 register update enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR1</name>
|
|
<description>HRTIM_EEFxR1 register update enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST2R</name>
|
|
<description>HRTIM_RST2xR register update enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET2R</name>
|
|
<description>HRTIM_SET2xR register update enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST1R</name>
|
|
<description>HRTIM_RST1xR register update enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET1R</name>
|
|
<description>HRTIM_SET1xR register update enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMx_DTxR</name>
|
|
<description>HRTIM_DTxR register update enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP4</name>
|
|
<description>HRTIM_CMP4xR register update enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP3</name>
|
|
<description>HRTIM_CMP3xR register update enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP2</name>
|
|
<description>HRTIM_CMP2xR register update enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP1</name>
|
|
<description>HRTIM_CMP1xR register update enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxREP</name>
|
|
<description>HRTIM_REPxR register update enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxPER</name>
|
|
<description>HRTIM_PERxR register update enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCNT</name>
|
|
<description>HRTIM_CNTxR register update enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxDIER</name>
|
|
<description>HRTIM_TIMxDIER register update enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxICR</name>
|
|
<description>HRTIM_TIMxICR register update enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR</name>
|
|
<description>HRTIM_TIMxCR register update enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTEUPR</name>
|
|
<displayName>BDTEUPR</displayName>
|
|
<description>Burst DMA Timerx update Register</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMxEEFR3</name>
|
|
<description>TIMxEEFR3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR2</name>
|
|
<description>TIMxCR2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxFLTR</name>
|
|
<description>HRTIM_FLTxR register update enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxOUTR</name>
|
|
<description>HRTIM_OUTxR register update enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCHPR</name>
|
|
<description>HRTIM_CHPxR register update enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRSTR</name>
|
|
<description>HRTIM_RSTxR register update enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR2</name>
|
|
<description>HRTIM_EEFxR2 register update enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR1</name>
|
|
<description>HRTIM_EEFxR1 register update enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST2R</name>
|
|
<description>HRTIM_RST2xR register update enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET2R</name>
|
|
<description>HRTIM_SET2xR register update enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST1R</name>
|
|
<description>HRTIM_RST1xR register update enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET1R</name>
|
|
<description>HRTIM_SET1xR register update enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMx_DTxR</name>
|
|
<description>HRTIM_DTxR register update enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP4</name>
|
|
<description>HRTIM_CMP4xR register update enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP3</name>
|
|
<description>HRTIM_CMP3xR register update enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP2</name>
|
|
<description>HRTIM_CMP2xR register update enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP1</name>
|
|
<description>HRTIM_CMP1xR register update enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxREP</name>
|
|
<description>HRTIM_REPxR register update enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxPER</name>
|
|
<description>HRTIM_PERxR register update enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCNT</name>
|
|
<description>HRTIM_CNTxR register update enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxDIER</name>
|
|
<description>HRTIM_TIMxDIER register update enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxICR</name>
|
|
<description>HRTIM_TIMxICR register update enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR</name>
|
|
<description>HRTIM_TIMxCR register update enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTFUPR</name>
|
|
<displayName>BDTFUPR</displayName>
|
|
<description>Burst DMA Timerx update Register</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMxEEFR3</name>
|
|
<description>TIMxEEFR3</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR2</name>
|
|
<description>TIMxCR2</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxFLTR</name>
|
|
<description>HRTIM_FLTxR register update enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxOUTR</name>
|
|
<description>HRTIM_OUTxR register update enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCHPR</name>
|
|
<description>HRTIM_CHPxR register update enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRSTR</name>
|
|
<description>HRTIM_RSTxR register update enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR2</name>
|
|
<description>HRTIM_EEFxR2 register update enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxEEFR1</name>
|
|
<description>HRTIM_EEFxR1 register update enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST2R</name>
|
|
<description>HRTIM_RST2xR register update enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET2R</name>
|
|
<description>HRTIM_SET2xR register update enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxRST1R</name>
|
|
<description>HRTIM_RST1xR register update enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxSET1R</name>
|
|
<description>HRTIM_SET1xR register update enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMx_DTxR</name>
|
|
<description>HRTIM_DTxR register update enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP4</name>
|
|
<description>HRTIM_CMP4xR register update enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP3</name>
|
|
<description>HRTIM_CMP3xR register update enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP2</name>
|
|
<description>HRTIM_CMP2xR register update enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCMP1</name>
|
|
<description>HRTIM_CMP1xR register update enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxREP</name>
|
|
<description>HRTIM_REPxR register update enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxPER</name>
|
|
<description>HRTIM_PERxR register update enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCNT</name>
|
|
<description>HRTIM_CNTxR register update enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxDIER</name>
|
|
<description>HRTIM_TIMxDIER register update enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxICR</name>
|
|
<description>HRTIM_TIMxICR register update enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIMxCR</name>
|
|
<description>HRTIM_TIMxCR register update enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDMADR</name>
|
|
<displayName>BDMADR</displayName>
|
|
<description>Burst DMA Data Register</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BDMADR</name>
|
|
<description>Burst DMA Data register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCER</name>
|
|
<displayName>ADCER</displayName>
|
|
<description>HRTIM ADC Extended Trigger Register</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADC10TRG</name>
|
|
<description>ADC10TRG</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC9TRG</name>
|
|
<description>ADC9TRG</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC8TRG</name>
|
|
<description>ADC8TRG</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC7TRG</name>
|
|
<description>ADC7TRG</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC6TRG</name>
|
|
<description>ADC6TRG</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC5TRG</name>
|
|
<description>ADC5TRG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCUR</name>
|
|
<displayName>ADCUR</displayName>
|
|
<description>HRTIM ADC Trigger Update Register</description>
|
|
<addressOffset>0x7C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AD10USRC</name>
|
|
<description>AD10USRC</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD9USRC</name>
|
|
<description>AD9USRC</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD8USRC</name>
|
|
<description>AD8USRC</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD7USRC</name>
|
|
<description>AD7USRC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD6USRC</name>
|
|
<description>AD6USRC</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AD5USRC</name>
|
|
<description>AD5USRC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCPS1</name>
|
|
<displayName>ADCPS1</displayName>
|
|
<description>HRTIM ADC Post Scaler Register 1</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADC5PSC</name>
|
|
<description>ADC5PSC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC4PSC</name>
|
|
<description>ADC4PSC</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC3PSC</name>
|
|
<description>ADC3PSC</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC2PSC</name>
|
|
<description>ADC2PSC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC1PSC</name>
|
|
<description>ADC1PSC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADCPS2</name>
|
|
<displayName>ADCPS2</displayName>
|
|
<description>HRTIM ADC Post Scaler Register 2</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADC10PSC</name>
|
|
<description>ADC10PSC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC9PSC</name>
|
|
<description>ADC9PSC</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC8PSC</name>
|
|
<description>ADC8PSC</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC7PSC</name>
|
|
<description>ADC7PSC</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC6PSC</name>
|
|
<description>ADC6PSC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTINR3</name>
|
|
<displayName>FLTINR3</displayName>
|
|
<description>HRTIM Fault Input Register 3</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLT4RSTM</name>
|
|
<description>FLT4RSTM</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4CRES</name>
|
|
<description>FLT4CRES</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4CNT</name>
|
|
<description>FLT4CNT</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4BLKS</name>
|
|
<description>FLT4BLKS</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT4BLKE</name>
|
|
<description>FLT4BLKE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3RSTM</name>
|
|
<description>FLT3RSTM</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3CRES</name>
|
|
<description>FLT3CRES</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3CNT</name>
|
|
<description>FLT3CNT</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3BLKS</name>
|
|
<description>FLT3BLKS</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT3BLKE</name>
|
|
<description>FLT3BLKE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2RSTM</name>
|
|
<description>FLT2RSTM</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2CRES</name>
|
|
<description>FLT2CRES</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2CNT</name>
|
|
<description>FLT2CNT</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2BLKS</name>
|
|
<description>FLT2BLKS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT2BLKE</name>
|
|
<description>FLT2BLKE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1RSTM</name>
|
|
<description>FLT1RSTM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1CRES</name>
|
|
<description>FLT1CRES</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1CNT</name>
|
|
<description>FLT1CNT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1BLKS</name>
|
|
<description>FLT1BLKS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT1BLKE</name>
|
|
<description>FLT1BLKE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTINR4</name>
|
|
<displayName>FLTINR4</displayName>
|
|
<description>HRTIM Fault Input Register 4</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLT6RSTM</name>
|
|
<description>FLT6RSTM</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6CRES</name>
|
|
<description>FLT6CRES</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6CNT</name>
|
|
<description>FLT6CNT</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6BLKS</name>
|
|
<description>FLT6BLKS</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT6BLKE</name>
|
|
<description>FLT6BLKE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5RSTM</name>
|
|
<description>FLT5RSTM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5CRES</name>
|
|
<description>FLT5CRES</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5CNT</name>
|
|
<description>FLT5CNT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5BLKS</name>
|
|
<description>FLT5BLKS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLT5BLKE</name>
|
|
<description>FLT5BLKE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>QUADSPI</name>
|
|
<description>QuadSPI interface</description>
|
|
<groupName>QUADSPI</groupName>
|
|
<baseAddress>0xA0001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>QUADSPI</name>
|
|
<description>QUADSPI</description>
|
|
<value>95</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESCALER</name>
|
|
<description>Clock prescaler</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMM</name>
|
|
<description>Polling match mode</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>APMS</name>
|
|
<description>Automatic poll mode stop</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TOIE</name>
|
|
<description>TimeOut interrupt enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMIE</name>
|
|
<description>Status match interrupt enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTIE</name>
|
|
<description>FIFO threshold interrupt enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transfer complete interrupt enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>Transfer error interrupt enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTHRES</name>
|
|
<description>IFO threshold level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSEL</name>
|
|
<description>FSEL</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DFM</name>
|
|
<description>DFM</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SSHIFT</name>
|
|
<description>Sample shift</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCEN</name>
|
|
<description>Timeout counter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABORT</name>
|
|
<description>Abort request</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<displayName>DCR</displayName>
|
|
<description>device configuration register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSIZE</name>
|
|
<description>FLASH memory size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSHT</name>
|
|
<description>Chip select high time</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKMODE</name>
|
|
<description>Mode 0 / mode 3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLEVEL</name>
|
|
<description>FIFO level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TOF</name>
|
|
<description>Timeout flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMF</name>
|
|
<description>Status match flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTF</name>
|
|
<description>FIFO threshold flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>Transfer complete flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEF</name>
|
|
<description>Transfer error flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FCR</name>
|
|
<displayName>FCR</displayName>
|
|
<description>flag clear register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTOF</name>
|
|
<description>Clear timeout flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSMF</name>
|
|
<description>Clear status match flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCF</name>
|
|
<description>Clear transfer complete flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTEF</name>
|
|
<description>Clear transfer error flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DLR</name>
|
|
<displayName>DLR</displayName>
|
|
<description>data length register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DL</name>
|
|
<description>Data length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<displayName>CCR</displayName>
|
|
<description>communication configuration register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DDRM</name>
|
|
<description>Double data rate mode</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIOO</name>
|
|
<description>Send instruction only once mode</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FMODE</name>
|
|
<description>Functional mode</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMODE</name>
|
|
<description>Data mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DCYC</name>
|
|
<description>Number of dummy cycles</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABSIZE</name>
|
|
<description>Alternate bytes size</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABMODE</name>
|
|
<description>Alternate bytes mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADSIZE</name>
|
|
<description>Address size</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADMODE</name>
|
|
<description>Address mode</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IMODE</name>
|
|
<description>Instruction mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INSTRUCTION</name>
|
|
<description>Instruction</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AR</name>
|
|
<displayName>AR</displayName>
|
|
<description>address register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ABR</name>
|
|
<displayName>ABR</displayName>
|
|
<description>ABR</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ALTERNATE</name>
|
|
<description>ALTERNATE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>data register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSMKR</name>
|
|
<displayName>PSMKR</displayName>
|
|
<description>polling status mask register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MASK</name>
|
|
<description>Status mask</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSMAR</name>
|
|
<displayName>PSMAR</displayName>
|
|
<description>polling status match register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MATCH</name>
|
|
<description>Status match</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PIR</name>
|
|
<displayName>PIR</displayName>
|
|
<description>polling interval register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTERVAL</name>
|
|
<description>Polling interval</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LPTR</name>
|
|
<displayName>LPTR</displayName>
|
|
<description>low-power timeout register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>Timeout period</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC1</name>
|
|
<description>Digital-to-analog converter</description>
|
|
<groupName>DAC</groupName>
|
|
<baseAddress>0x50000800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DAC_CR</name>
|
|
<displayName>DAC_CR</displayName>
|
|
<description>DAC control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN1</name>
|
|
<description>DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN1</name>
|
|
<description>DAC channel1 trigger enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEL1</name>
|
|
<description>DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAVE1</name>
|
|
<description>DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAMP1</name>
|
|
<description>DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN1</name>
|
|
<description>DAC channel1 DMA enable This bit is set and cleared by software.</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDRIE1</name>
|
|
<description>DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN1</name>
|
|
<description>DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN2</name>
|
|
<description>DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEN2</name>
|
|
<description>DAC channel2 trigger enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSEL2</name>
|
|
<description>DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAVE2</name>
|
|
<description>DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MAMP2</name>
|
|
<description>DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN2</name>
|
|
<description>DAC channel2 DMA enable This bit is set and cleared by software.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDRIE2</name>
|
|
<description>DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEN2</name>
|
|
<description>DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_SWTRGR</name>
|
|
<displayName>DAC_SWTRGR</displayName>
|
|
<description>DAC software trigger register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWTRIG1</name>
|
|
<description>DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG2</name>
|
|
<description>DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIGB1</name>
|
|
<description>DAC channel1 software trigger B</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIGB2</name>
|
|
<description>DAC channel2 software trigger B</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR12R1</name>
|
|
<displayName>DAC_DHR12R1</displayName>
|
|
<description>DAC channel1 12-bit right-aligned data holding register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC1DHRB</name>
|
|
<description>DAC channel1 12-bit right-aligned data B</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR12L1</name>
|
|
<displayName>DAC_DHR12L1</displayName>
|
|
<description>DAC channel1 12-bit left aligned data holding register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC1DHRB</name>
|
|
<description>DAC channel1 12-bit left-aligned data B</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR8R1</name>
|
|
<displayName>DAC_DHR8R1</displayName>
|
|
<description>DAC channel1 8-bit right aligned data holding register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC1DHRB</name>
|
|
<description>DAC channel1 8-bit right-aligned data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR12R2</name>
|
|
<displayName>DAC_DHR12R2</displayName>
|
|
<description>DAC channel2 12-bit right aligned data holding register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHRB</name>
|
|
<description>DAC channel2 12-bit right-aligned data</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR12L2</name>
|
|
<displayName>DAC_DHR12L2</displayName>
|
|
<description>DAC channel2 12-bit left aligned data holding register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHRB</name>
|
|
<description>DAC channel2 12-bit left-aligned data B</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR8R2</name>
|
|
<displayName>DAC_DHR8R2</displayName>
|
|
<description>DAC channel2 8-bit right-aligned data holding register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHRB</name>
|
|
<description>DAC channel2 8-bit right-aligned data</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR12RD</name>
|
|
<displayName>DAC_DHR12RD</displayName>
|
|
<description>Dual DAC 12-bit right-aligned data holding register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR12LD</name>
|
|
<displayName>DAC_DHR12LD</displayName>
|
|
<description>DUAL DAC 12-bit left aligned data holding register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DHR8RD</name>
|
|
<displayName>DAC_DHR8RD</displayName>
|
|
<description>DUAL DAC 8-bit right aligned data holding register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DOR1</name>
|
|
<displayName>DAC_DOR1</displayName>
|
|
<description>DAC channel1 data output register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DOR</name>
|
|
<description>DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC1DORB</name>
|
|
<description>DAC channel1 data output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_DOR2</name>
|
|
<displayName>DAC_DOR2</displayName>
|
|
<description>DAC channel2 data output register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DOR</name>
|
|
<description>DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DORB</name>
|
|
<description>DAC channel2 data output</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_SR</name>
|
|
<displayName>DAC_SR</displayName>
|
|
<description>DAC status register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC1RDY</name>
|
|
<description>DAC channel1 ready status bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DORSTAT1</name>
|
|
<description>DAC channel1 output register status bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDR1</name>
|
|
<description>DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAL_FLAG1</name>
|
|
<description>DAC Channel 1 calibration offset status This bit is set and cleared by hardware</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BWST1</name>
|
|
<description>DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DAC2RDY</name>
|
|
<description>DAC channel 2 ready status bit</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DORSTAT2</name>
|
|
<description>DAC channel 2 output register status bit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDR2</name>
|
|
<description>DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CAL_FLAG2</name>
|
|
<description>DAC Channel 2 calibration offset status This bit is set and cleared by hardware</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BWST2</name>
|
|
<description>DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_CCR</name>
|
|
<displayName>DAC_CCR</displayName>
|
|
<description>DAC calibration control register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OTRIM1</name>
|
|
<description>DAC Channel 1 offset trimming value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OTRIM2</name>
|
|
<description>DAC Channel 2 offset trimming value</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_MCR</name>
|
|
<displayName>DAC_MCR</displayName>
|
|
<description>DAC mode control register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMADOUBLE1</name>
|
|
<description>DAC Channel1 DMA double data mode</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINFORMAT1</name>
|
|
<description>Enable signed format for DAC channel1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HFSEL</name>
|
|
<description>High frequency interface mode selection</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMADOUBLE2</name>
|
|
<description>DAC Channel2 DMA double data mode</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SINFORMAT2</name>
|
|
<description>Enable signed format for DAC channel2</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_SHSR1</name>
|
|
<displayName>DAC_SHSR1</displayName>
|
|
<description>DAC Sample and Hold sample time register 1</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSAMPLE1</name>
|
|
<description>DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_SHSR2</name>
|
|
<displayName>DAC_SHSR2</displayName>
|
|
<description>DAC Sample and Hold sample time register 2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSAMPLE2</name>
|
|
<description>DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_SHHR</name>
|
|
<displayName>DAC_SHHR</displayName>
|
|
<description>DAC Sample and Hold hold time register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>THOLD1</name>
|
|
<description>DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>THOLD2</name>
|
|
<description>DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_SHRR</name>
|
|
<displayName>DAC_SHRR</displayName>
|
|
<description>DAC Sample and Hold refresh time register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00010001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TREFRESH1</name>
|
|
<description>DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TREFRESH2</name>
|
|
<description>DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_STR1</name>
|
|
<displayName>DAC_STR1</displayName>
|
|
<description>Sawtooth register</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRSTDATA1</name>
|
|
<description>DAC Channel 1 Sawtooth reset value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STDIR1</name>
|
|
<description>DAC Channel1 Sawtooth direction setting</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STINCDATA1</name>
|
|
<description>DAC CH1 Sawtooth increment value (12.4 bit format)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_STR2</name>
|
|
<displayName>DAC_STR2</displayName>
|
|
<description>Sawtooth register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRSTDATA2</name>
|
|
<description>DAC Channel 2 Sawtooth reset value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STDIR2</name>
|
|
<description>DAC Channel2 Sawtooth direction setting</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STINCDATA2</name>
|
|
<description>DAC CH2 Sawtooth increment value (12.4 bit format)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DAC_STMODR</name>
|
|
<displayName>DAC_STMODR</displayName>
|
|
<description>Sawtooth Mode register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STRSTTRIGSEL1</name>
|
|
<description>DAC Channel 1 Sawtooth Reset trigger selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STINCTRIGSEL1</name>
|
|
<description>DAC Channel 1 Sawtooth Increment trigger selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STRSTTRIGSEL2</name>
|
|
<description>DAC Channel 1 Sawtooth Reset trigger selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STINCTRIGSEL2</name>
|
|
<description>DAC Channel 2 Sawtooth Increment trigger selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DAC1">
|
|
<name>DAC2</name>
|
|
<baseAddress>0x50000C00</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DAC1">
|
|
<name>DAC3</name>
|
|
<baseAddress>0x50001000</baseAddress>
|
|
</peripheral>
|
|
<peripheral derivedFrom="DAC1">
|
|
<name>DAC4</name>
|
|
<baseAddress>0x50001400</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC1</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x50000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xD0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC1_2</name>
|
|
<description>ADC1 and ADC2 global interrupt</description>
|
|
<value>18</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>interrupt and status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JQOVF</name>
|
|
<description>JQOVF</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD3</name>
|
|
<description>AWD3</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD2</name>
|
|
<description>AWD2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1</name>
|
|
<description>AWD1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOS</name>
|
|
<description>JEOS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOC</name>
|
|
<description>JEOC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>OVR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOS</name>
|
|
<description>EOS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC</name>
|
|
<description>EOC</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSMP</name>
|
|
<description>EOSMP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADRDY</name>
|
|
<description>ADRDY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>interrupt enable register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JQOVFIE</name>
|
|
<description>JQOVFIE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD3IE</name>
|
|
<description>AWD3IE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD2IE</name>
|
|
<description>AWD2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1IE</name>
|
|
<description>AWD1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOSIE</name>
|
|
<description>JEOSIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOCIE</name>
|
|
<description>JEOCIE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRIE</name>
|
|
<description>OVRIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSIE</name>
|
|
<description>EOSIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOCIE</name>
|
|
<description>EOCIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSMPIE</name>
|
|
<description>EOSMPIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADRDYIE</name>
|
|
<description>ADRDYIE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADCAL</name>
|
|
<description>ADCAL</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADCALDIF</name>
|
|
<description>ADCALDIF</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEEPPWD</name>
|
|
<description>DEEPPWD</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADVREGEN</name>
|
|
<description>ADVREGEN</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JADSTP</name>
|
|
<description>JADSTP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADSTP</name>
|
|
<description>ADSTP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JADSTART</name>
|
|
<description>JADSTART</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADSTART</name>
|
|
<description>ADSTART</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDIS</name>
|
|
<description>ADDIS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADEN</name>
|
|
<description>ADEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JQDIS</name>
|
|
<description>Injected Queue disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1CH</name>
|
|
<description>Analog watchdog 1 channel selection</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JAUTO</name>
|
|
<description>JAUTO</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JAWD1EN</name>
|
|
<description>JAWD1EN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1EN</name>
|
|
<description>AWD1EN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1SGL</name>
|
|
<description>AWD1SGL</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JQM</name>
|
|
<description>JQM</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JDISCEN</name>
|
|
<description>JDISCEN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISCNUM</name>
|
|
<description>DISCNUM</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISCEN</name>
|
|
<description>DISCEN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALIGN</name>
|
|
<description>ALIGN</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AUTDLY</name>
|
|
<description>AUTDLY</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>CONT</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRMOD</name>
|
|
<description>OVRMOD</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEN</name>
|
|
<description>EXTEN</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTSEL</name>
|
|
<description>External trigger selection for regular group</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES</name>
|
|
<description>RES</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMACFG</name>
|
|
<description>DMACFG</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMAEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR2</name>
|
|
<displayName>CFGR2</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMPTRIG</name>
|
|
<description>SMPTRIG</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BULB</name>
|
|
<description>BULB</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG</name>
|
|
<description>SWTRIG</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCOMP</name>
|
|
<description>GCOMP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROVSM</name>
|
|
<description>EXTEN</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TROVS</name>
|
|
<description>Triggered Regular Oversampling</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVSS</name>
|
|
<description>ALIGN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVSR</name>
|
|
<description>RES</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JOVSE</name>
|
|
<description>DMACFG</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROVSE</name>
|
|
<description>DMAEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPR1</name>
|
|
<displayName>SMPR1</displayName>
|
|
<description>sample time register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMP9</name>
|
|
<description>SMP9</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP8</name>
|
|
<description>SMP8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP7</name>
|
|
<description>SMP7</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP6</name>
|
|
<description>SMP6</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP5</name>
|
|
<description>SMP5</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP4</name>
|
|
<description>SMP4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP3</name>
|
|
<description>SMP3</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP2</name>
|
|
<description>SMP2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP1</name>
|
|
<description>SMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMPPLUS</name>
|
|
<description>Addition of one clock cycle to the sampling time</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP0</name>
|
|
<description>SMP0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPR2</name>
|
|
<displayName>SMPR2</displayName>
|
|
<description>sample time register 2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMP18</name>
|
|
<description>SMP18</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP17</name>
|
|
<description>SMP17</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP16</name>
|
|
<description>SMP16</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP15</name>
|
|
<description>SMP15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP14</name>
|
|
<description>SMP14</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP13</name>
|
|
<description>SMP13</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP12</name>
|
|
<description>SMP12</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP11</name>
|
|
<description>SMP11</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP10</name>
|
|
<description>SMP10</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TR1</name>
|
|
<displayName>TR1</displayName>
|
|
<description>watchdog threshold register 1</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HT1</name>
|
|
<description>HT1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWDFILT</name>
|
|
<description>AWDFILT</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LT1</name>
|
|
<description>LT1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TR2</name>
|
|
<displayName>TR2</displayName>
|
|
<description>watchdog threshold register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00FF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HT2</name>
|
|
<description>HT2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LT2</name>
|
|
<description>LT2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TR3</name>
|
|
<displayName>TR3</displayName>
|
|
<description>watchdog threshold register 3</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00FF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HT3</name>
|
|
<description>HT3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LT3</name>
|
|
<description>LT3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR1</name>
|
|
<displayName>SQR1</displayName>
|
|
<description>regular sequence register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ4</name>
|
|
<description>SQ4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ3</name>
|
|
<description>SQ3</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ2</name>
|
|
<description>SQ2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ1</name>
|
|
<description>SQ1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>L</name>
|
|
<description>Regular channel sequence length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR2</name>
|
|
<displayName>SQR2</displayName>
|
|
<description>regular sequence register 2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ9</name>
|
|
<description>SQ9</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ8</name>
|
|
<description>SQ8</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ7</name>
|
|
<description>SQ7</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ6</name>
|
|
<description>SQ6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ5</name>
|
|
<description>SQ5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR3</name>
|
|
<displayName>SQR3</displayName>
|
|
<description>regular sequence register 3</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ14</name>
|
|
<description>SQ14</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ13</name>
|
|
<description>SQ13</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ12</name>
|
|
<description>SQ12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ11</name>
|
|
<description>SQ11</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ10</name>
|
|
<description>SQ10</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR4</name>
|
|
<displayName>SQR4</displayName>
|
|
<description>regular sequence register 4</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ16</name>
|
|
<description>SQ16</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ15</name>
|
|
<description>SQ15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>regular Data Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>Regular Data converted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JSQR</name>
|
|
<displayName>JSQR</displayName>
|
|
<description>injected sequence register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JSQ4</name>
|
|
<description>JSQ4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JSQ3</name>
|
|
<description>JSQ3</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JSQ2</name>
|
|
<description>JSQ2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JSQ1</name>
|
|
<description>JSQ1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEXTEN</name>
|
|
<description>JEXTEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEXTSEL</name>
|
|
<description>JEXTSEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JL</name>
|
|
<description>JL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR1</name>
|
|
<displayName>OFR1</displayName>
|
|
<description>offset register 1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR2</name>
|
|
<displayName>OFR2</displayName>
|
|
<description>offset register 2</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR3</name>
|
|
<displayName>OFR3</displayName>
|
|
<description>offset register 3</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR4</name>
|
|
<displayName>OFR4</displayName>
|
|
<description>offset register 4</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR1</name>
|
|
<displayName>JDR1</displayName>
|
|
<description>injected data register 1</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA1</name>
|
|
<description>JDATA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR2</name>
|
|
<displayName>JDR2</displayName>
|
|
<description>injected data register 2</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA2</name>
|
|
<description>JDATA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR3</name>
|
|
<displayName>JDR3</displayName>
|
|
<description>injected data register 3</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA3</name>
|
|
<description>JDATA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR4</name>
|
|
<displayName>JDR4</displayName>
|
|
<description>injected data register 4</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA4</name>
|
|
<description>JDATA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AWD2CR</name>
|
|
<displayName>AWD2CR</displayName>
|
|
<description>Analog Watchdog 2 Configuration Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AWD2CH</name>
|
|
<description>AWD2CH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AWD3CR</name>
|
|
<displayName>AWD3CR</displayName>
|
|
<description>Analog Watchdog 3 Configuration Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AWD3CH</name>
|
|
<description>AWD3CH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIFSEL</name>
|
|
<displayName>DIFSEL</displayName>
|
|
<description>Differential Mode Selection Register 2</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIFSEL_0</name>
|
|
<description>Differential mode for channels 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFSEL_1_18</name>
|
|
<description>Differential mode for channels 15 to 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALFACT</name>
|
|
<displayName>CALFACT</displayName>
|
|
<description>Calibration Factors</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALFACT_D</name>
|
|
<description>CALFACT_D</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALFACT_S</name>
|
|
<description>CALFACT_S</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GCOMP</name>
|
|
<displayName>GCOMP</displayName>
|
|
<description>Gain compensation Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GCOMPCOEFF</name>
|
|
<description>GCOMPCOEFF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC1">
|
|
<name>ADC2</name>
|
|
<baseAddress>0x50000100</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC3</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x50000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xD0</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC3</name>
|
|
<description>ADC3</description>
|
|
<value>47</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>interrupt and status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JQOVF</name>
|
|
<description>JQOVF</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD3</name>
|
|
<description>AWD3</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD2</name>
|
|
<description>AWD2</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1</name>
|
|
<description>AWD1</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOS</name>
|
|
<description>JEOS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOC</name>
|
|
<description>JEOC</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>OVR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOS</name>
|
|
<description>EOS</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC</name>
|
|
<description>EOC</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSMP</name>
|
|
<description>EOSMP</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADRDY</name>
|
|
<description>ADRDY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>interrupt enable register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JQOVFIE</name>
|
|
<description>JQOVFIE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD3IE</name>
|
|
<description>AWD3IE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD2IE</name>
|
|
<description>AWD2IE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1IE</name>
|
|
<description>AWD1IE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOSIE</name>
|
|
<description>JEOSIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOCIE</name>
|
|
<description>JEOCIE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRIE</name>
|
|
<description>OVRIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSIE</name>
|
|
<description>EOSIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOCIE</name>
|
|
<description>EOCIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSMPIE</name>
|
|
<description>EOSMPIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADRDYIE</name>
|
|
<description>ADRDYIE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20002000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADCAL</name>
|
|
<description>ADCAL</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADCALDIF</name>
|
|
<description>ADCALDIF</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEEPPWD</name>
|
|
<description>DEEPPWD</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADVREGEN</name>
|
|
<description>ADVREGEN</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JADSTP</name>
|
|
<description>JADSTP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADSTP</name>
|
|
<description>ADSTP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JADSTART</name>
|
|
<description>JADSTART</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADSTART</name>
|
|
<description>ADSTART</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDIS</name>
|
|
<description>ADDIS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADEN</name>
|
|
<description>ADEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x80000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JQDIS</name>
|
|
<description>Injected Queue disable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWDCH1CH</name>
|
|
<description>AWDCH1CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JAUTO</name>
|
|
<description>JAUTO</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JAWD1EN</name>
|
|
<description>JAWD1EN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1EN</name>
|
|
<description>AWD1EN</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1SGL</name>
|
|
<description>AWD1SGL</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JQM</name>
|
|
<description>JQM</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JDISCEN</name>
|
|
<description>JDISCEN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISCNUM</name>
|
|
<description>DISCNUM</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISCEN</name>
|
|
<description>DISCEN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALIGN</name>
|
|
<description>ALIGN</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AUTDLY</name>
|
|
<description>AUTDLY</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONT</name>
|
|
<description>CONT</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRMOD</name>
|
|
<description>OVRMOD</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTEN</name>
|
|
<description>EXTEN</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTSEL</name>
|
|
<description>EXTSEL</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ALIGN_5</name>
|
|
<description>ALIGN_5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RES</name>
|
|
<description>RES</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMACFG</name>
|
|
<description>DMACFG</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMAEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR2</name>
|
|
<displayName>CFGR2</displayName>
|
|
<description>configuration register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMPTRIG</name>
|
|
<description>SMPTRIG</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BULB</name>
|
|
<description>BULB</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG</name>
|
|
<description>SWTRIG</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GCOMP</name>
|
|
<description>GCOMP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROVSM</name>
|
|
<description>EXTEN</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TROVS</name>
|
|
<description>Triggered Regular Oversampling</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVSS</name>
|
|
<description>ALIGN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVSR</name>
|
|
<description>RES</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JOVSE</name>
|
|
<description>DMACFG</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ROVSE</name>
|
|
<description>DMAEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPR1</name>
|
|
<displayName>SMPR1</displayName>
|
|
<description>sample time register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMP9</name>
|
|
<description>SMP9</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP8</name>
|
|
<description>SMP8</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP7</name>
|
|
<description>SMP7</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP6</name>
|
|
<description>SMP6</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP5</name>
|
|
<description>SMP5</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP4</name>
|
|
<description>SMP4</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP3</name>
|
|
<description>SMP3</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP2</name>
|
|
<description>SMP2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP1</name>
|
|
<description>SMP1</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMPPLUS</name>
|
|
<description>Addition of one clock cycle to the sampling time</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP0</name>
|
|
<description>SMP0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMPR2</name>
|
|
<displayName>SMPR2</displayName>
|
|
<description>sample time register 2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMP18</name>
|
|
<description>SMP18</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP17</name>
|
|
<description>SMP17</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP16</name>
|
|
<description>SMP16</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP15</name>
|
|
<description>SMP15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP14</name>
|
|
<description>SMP14</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP13</name>
|
|
<description>SMP13</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP12</name>
|
|
<description>SMP12</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP11</name>
|
|
<description>SMP11</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMP10</name>
|
|
<description>SMP10</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TR1</name>
|
|
<displayName>TR1</displayName>
|
|
<description>watchdog threshold register 1</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0FFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HT1</name>
|
|
<description>HT1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWDFILT</name>
|
|
<description>AWDFILT</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LT1</name>
|
|
<description>LT1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TR2</name>
|
|
<displayName>TR2</displayName>
|
|
<description>watchdog threshold register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00FF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HT2</name>
|
|
<description>HT2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LT2</name>
|
|
<description>LT2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TR3</name>
|
|
<displayName>TR3</displayName>
|
|
<description>watchdog threshold register 3</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00FF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HT3</name>
|
|
<description>HT3</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LT3</name>
|
|
<description>LT3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR1</name>
|
|
<displayName>SQR1</displayName>
|
|
<description>regular sequence register 1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ4</name>
|
|
<description>SQ4</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ3</name>
|
|
<description>SQ3</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ2</name>
|
|
<description>SQ2</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ1</name>
|
|
<description>SQ1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>L</name>
|
|
<description>Regular channel sequence length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR2</name>
|
|
<displayName>SQR2</displayName>
|
|
<description>regular sequence register 2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ9</name>
|
|
<description>SQ9</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ8</name>
|
|
<description>SQ8</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ7</name>
|
|
<description>SQ7</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ6</name>
|
|
<description>SQ6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ5</name>
|
|
<description>SQ5</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR3</name>
|
|
<displayName>SQR3</displayName>
|
|
<description>regular sequence register 3</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ14</name>
|
|
<description>SQ14</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ13</name>
|
|
<description>SQ13</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ12</name>
|
|
<description>SQ12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ11</name>
|
|
<description>SQ11</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ10</name>
|
|
<description>SQ10</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR4</name>
|
|
<displayName>SQR4</displayName>
|
|
<description>regular sequence register 4</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ16</name>
|
|
<description>SQ16</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SQ15</name>
|
|
<description>SQ15</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>regular Data Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>Regular Data converted</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JSQR</name>
|
|
<displayName>JSQR</displayName>
|
|
<description>injected sequence register</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JSQ4</name>
|
|
<description>JSQ4</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JSQ3</name>
|
|
<description>JSQ3</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JSQ2</name>
|
|
<description>JSQ2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JSQ1</name>
|
|
<description>JSQ1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEXTEN</name>
|
|
<description>JEXTEN</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEXTSEL</name>
|
|
<description>JEXTSEL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JL</name>
|
|
<description>JL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR1</name>
|
|
<displayName>OFR1</displayName>
|
|
<description>offset register 1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR2</name>
|
|
<displayName>OFR2</displayName>
|
|
<description>offset register 2</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR3</name>
|
|
<displayName>OFR3</displayName>
|
|
<description>offset register 3</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OFR4</name>
|
|
<displayName>OFR4</displayName>
|
|
<description>offset register 4</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OFFSET1_EN</name>
|
|
<description>OFFSET1_EN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1_CH</name>
|
|
<description>OFFSET1_CH</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATEN</name>
|
|
<description>SATEN</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSETPOS</name>
|
|
<description>OFFSETPOS</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFFSET1</name>
|
|
<description>OFFSET1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR1</name>
|
|
<displayName>JDR1</displayName>
|
|
<description>injected data register 1</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA1</name>
|
|
<description>JDATA1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR2</name>
|
|
<displayName>JDR2</displayName>
|
|
<description>injected data register 2</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA2</name>
|
|
<description>JDATA2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR3</name>
|
|
<displayName>JDR3</displayName>
|
|
<description>injected data register 3</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA3</name>
|
|
<description>JDATA3</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR4</name>
|
|
<displayName>JDR4</displayName>
|
|
<description>injected data register 4</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDATA4</name>
|
|
<description>JDATA4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AWD2CR</name>
|
|
<displayName>AWD2CR</displayName>
|
|
<description>Analog Watchdog 2 Configuration Register</description>
|
|
<addressOffset>0xA0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AWD2CH</name>
|
|
<description>AWD2CH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AWD3CR</name>
|
|
<displayName>AWD3CR</displayName>
|
|
<description>Analog Watchdog 3 Configuration Register</description>
|
|
<addressOffset>0xA4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AWD3CH</name>
|
|
<description>AWD3CH</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>19</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIFSEL</name>
|
|
<displayName>DIFSEL</displayName>
|
|
<description>Differential Mode Selection Register 2</description>
|
|
<addressOffset>0xB0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIFSEL_0</name>
|
|
<description>Differential mode for channels 0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DIFSEL_1_18</name>
|
|
<description>Differential mode for channels 15 to 1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>18</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALFACT</name>
|
|
<displayName>CALFACT</displayName>
|
|
<description>Calibration Factors</description>
|
|
<addressOffset>0xB4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALFACT_D</name>
|
|
<description>CALFACT_D</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALFACT_S</name>
|
|
<description>CALFACT_S</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GCOMP</name>
|
|
<displayName>GCOMP</displayName>
|
|
<description>Gain compensation Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GCOMPCOEFF</name>
|
|
<description>GCOMPCOEFF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>14</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC1">
|
|
<name>ADC4</name>
|
|
<baseAddress>0x50000500</baseAddress>
|
|
<interrupt>
|
|
<name>ADC4</name>
|
|
<description>ADC4</description>
|
|
<value>61</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC3">
|
|
<name>ADC5</name>
|
|
<baseAddress>0x50000600</baseAddress>
|
|
<interrupt>
|
|
<name>ADC5</name>
|
|
<description>ADC5</description>
|
|
<value>62</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>ADC12_Common</name>
|
|
<description>Analog-to-Digital Converter</description>
|
|
<groupName>ADC</groupName>
|
|
<baseAddress>0x50000300</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x11</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>ADC Common status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRDY_MST</name>
|
|
<description>ADDRDY_MST</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSMP_MST</name>
|
|
<description>EOSMP_MST</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC_MST</name>
|
|
<description>EOC_MST</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOS_MST</name>
|
|
<description>EOS_MST</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVR_MST</name>
|
|
<description>OVR_MST</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOC_MST</name>
|
|
<description>JEOC_MST</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOS_MST</name>
|
|
<description>JEOS_MST</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1_MST</name>
|
|
<description>AWD1_MST</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD2_MST</name>
|
|
<description>AWD2_MST</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD3_MST</name>
|
|
<description>AWD3_MST</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JQOVF_MST</name>
|
|
<description>JQOVF_MST</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADRDY_SLV</name>
|
|
<description>ADRDY_SLV</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOSMP_SLV</name>
|
|
<description>EOSMP_SLV</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOC_SLV</name>
|
|
<description>End of regular conversion of the slave ADC</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOS_SLV</name>
|
|
<description>End of regular sequence flag of the slave ADC</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVR_SLV</name>
|
|
<description>Overrun flag of the slave ADC</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOC_SLV</name>
|
|
<description>End of injected conversion flag of the slave ADC</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JEOS_SLV</name>
|
|
<description>End of injected sequence flag of the slave ADC</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD1_SLV</name>
|
|
<description>Analog watchdog 1 flag of the slave ADC</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD2_SLV</name>
|
|
<description>Analog watchdog 2 flag of the slave ADC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AWD3_SLV</name>
|
|
<description>Analog watchdog 3 flag of the slave ADC</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>JQOVF_SLV</name>
|
|
<description>Injected Context Queue Overflow flag of the slave ADC</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<displayName>CCR</displayName>
|
|
<description>ADC common control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DUAL</name>
|
|
<description>Dual ADC mode selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DELAY</name>
|
|
<description>Delay between 2 sampling phases</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMACFG</name>
|
|
<description>DMA configuration (for multi-ADC mode)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MDMA</name>
|
|
<description>Direct memory access mode for multi ADC mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKMODE</name>
|
|
<description>ADC clock mode</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREFEN</name>
|
|
<description>VREFINT enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VSENSESEL</name>
|
|
<description> VTS selection</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VBATSEL</name>
|
|
<description>VBAT selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>ADC prescaler</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CDR</name>
|
|
<displayName>CDR</displayName>
|
|
<description>ADC common regular data register for dual and triple modes</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA_SLV</name>
|
|
<description>Regular data of the slave ADC</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDATA_MST</name>
|
|
<description>Regular data of the master ADC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="ADC12_Common">
|
|
<name>ADC345_Common</name>
|
|
<baseAddress>0x50000700</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FMAC</name>
|
|
<description>Filter Math Accelerator</description>
|
|
<groupName>FMAC</groupName>
|
|
<baseAddress>0x40021400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xC00</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FMAC</name>
|
|
<description>FMAC</description>
|
|
<value>101</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>X1BUFCFG</name>
|
|
<displayName>X1BUFCFG</displayName>
|
|
<description>FMAC X1 Buffer Configuration register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>X1_BASE</name>
|
|
<description>X1_BASE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>X1_BUF_SIZE</name>
|
|
<description>X1_BUF_SIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FULL_WM</name>
|
|
<description>FULL_WM</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>X2BUFCFG</name>
|
|
<displayName>X2BUFCFG</displayName>
|
|
<description>FMAC X2 Buffer Configuration register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>X2_BASE</name>
|
|
<description>X1_BASE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>X2_BUF_SIZE</name>
|
|
<description>X1_BUF_SIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>YBUFCFG</name>
|
|
<displayName>YBUFCFG</displayName>
|
|
<description>FMAC Y Buffer Configuration register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>Y_BASE</name>
|
|
<description>X1_BASE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Y_BUF_SIZE</name>
|
|
<description>X1_BUF_SIZE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EMPTY_WM</name>
|
|
<description>EMPTY_WM</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PARAM</name>
|
|
<displayName>PARAM</displayName>
|
|
<description>FMAC Parameter register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>START</name>
|
|
<description>START</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>FUNC</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>R</name>
|
|
<description>R</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Q</name>
|
|
<description>Q</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>P</name>
|
|
<description>P</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>FMAC Control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>RESET</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLIPEN</name>
|
|
<description>CLIPEN</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAWEN</name>
|
|
<description>DMAWEN</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAREN</name>
|
|
<description>DMAREN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SATIEN</name>
|
|
<description>SATIEN</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNFLIEN</name>
|
|
<description>UNFLIEN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFLIEN</name>
|
|
<description>OVFLIEN</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WIEN</name>
|
|
<description>WIEN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RIEN</name>
|
|
<description>RIEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>FMAC Status register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>YEMPTY</name>
|
|
<description>YEMPTY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>X1FULL</name>
|
|
<description>X1FULL</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVFL</name>
|
|
<description>OVFL</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNFL</name>
|
|
<description>UNFL</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAT</name>
|
|
<description>SAT</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDATA</name>
|
|
<displayName>WDATA</displayName>
|
|
<description>FMAC Write Data register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDATA</name>
|
|
<description>WDATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDATA</name>
|
|
<displayName>RDATA</displayName>
|
|
<description>FMAC Read Data register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDATA</name>
|
|
<description>RDATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CORDIC</name>
|
|
<description>CORDIC Co-processor</description>
|
|
<groupName>CORDIC</groupName>
|
|
<baseAddress>0x40020C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>Cordic</name>
|
|
<description>Cordic</description>
|
|
<value>100</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>CORDIC Control Status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FUNC</name>
|
|
<description>FUNC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRECISION</name>
|
|
<description>PRECISION</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SCALE</name>
|
|
<description>SCALE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IEN</name>
|
|
<description>IEN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAREN</name>
|
|
<description>DMAREN</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAWEN</name>
|
|
<description>DMAWEN</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRES</name>
|
|
<description>NRES</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NARGS</name>
|
|
<description>NARGS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESSIZE</name>
|
|
<description>RESSIZE</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARGSIZE</name>
|
|
<description>ARGSIZE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RRDY</name>
|
|
<description>RRDY</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WDATA</name>
|
|
<displayName>WDATA</displayName>
|
|
<description>FMAC Write Data register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARG</name>
|
|
<description>ARG</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RDATA</name>
|
|
<displayName>RDATA</displayName>
|
|
<description>FMAC Read Data register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RES</name>
|
|
<description>RES</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SAI</name>
|
|
<description>Serial audio interface</description>
|
|
<groupName>SAI</groupName>
|
|
<baseAddress>0x40015400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SAI</name>
|
|
<description>SAI</description>
|
|
<value>76</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>BCR1</name>
|
|
<displayName>BCR1</displayName>
|
|
<description>BConfiguration register 1</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCKEN</name>
|
|
<description>MCKEN</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>OSR</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCJDIV</name>
|
|
<description>Master clock divider</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NODIV</name>
|
|
<description>No divider</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAIBEN</name>
|
|
<description>Audio block B enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OutDri</name>
|
|
<description>Output drive</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>Mono mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN</name>
|
|
<description>Synchronization enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKSTR</name>
|
|
<description>Clock strobing edge</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSBFIRST</name>
|
|
<description>Least significant bit first</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>Data size</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRTCFG</name>
|
|
<description>Protocol configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Audio block mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCR2</name>
|
|
<displayName>BCR2</displayName>
|
|
<description>BConfiguration register 2</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Companding mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPL</name>
|
|
<description>Complement bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTECN</name>
|
|
<description>Mute counter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEVAL</name>
|
|
<description>Mute value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTE</name>
|
|
<description>Mute</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIS</name>
|
|
<description>Tristate management on data line</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FFLUS</name>
|
|
<description>FIFO flush</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTH</name>
|
|
<description>FIFO threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BFRCR</name>
|
|
<displayName>BFRCR</displayName>
|
|
<description>BFRCR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSOFF</name>
|
|
<description>Frame synchronization offset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSPOL</name>
|
|
<description>Frame synchronization polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSDEF</name>
|
|
<description>Frame synchronization definition</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSALL</name>
|
|
<description>Frame synchronization active level length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRL</name>
|
|
<description>Frame length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSLOTR</name>
|
|
<displayName>BSLOTR</displayName>
|
|
<description>BSlot register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLOTEN</name>
|
|
<description>Slot enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBSLOT</name>
|
|
<description>Number of slots in an audio frame</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTSZ</name>
|
|
<description>Slot size</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FBOFF</name>
|
|
<description>First bit offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BIM</name>
|
|
<displayName>BIM</displayName>
|
|
<description>BInterrupt mask register2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LFSDETIE</name>
|
|
<description>Late frame synchronization detection interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSDETIE</name>
|
|
<description>Anticipated frame synchronization detection interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNRDYIE</name>
|
|
<description>Codec not ready interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQIE</name>
|
|
<description>FIFO request interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCKCFG</name>
|
|
<description>Wrong clock configuration interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEDET</name>
|
|
<description>Mute detection interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRUDRIE</name>
|
|
<description>Overrun/underrun interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSR</name>
|
|
<displayName>BSR</displayName>
|
|
<description>BStatus register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLVL</name>
|
|
<description>FIFO level threshold</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LFSDET</name>
|
|
<description>Late frame synchronization detection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSDET</name>
|
|
<description>Anticipated frame synchronization detection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNRDY</name>
|
|
<description>Codec not ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQ</name>
|
|
<description>FIFO request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCKCFG</name>
|
|
<description>Wrong clock configuration flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEDET</name>
|
|
<description>Mute detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRUDR</name>
|
|
<description>Overrun / underrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BCLRFR</name>
|
|
<displayName>BCLRFR</displayName>
|
|
<description>BClear flag register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LFSDET</name>
|
|
<description>Clear late frame synchronization detection flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAFSDET</name>
|
|
<description>Clear anticipated frame synchronization detection flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNRDY</name>
|
|
<description>Clear codec not ready flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCKCFG</name>
|
|
<description>Clear wrong clock configuration flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEDET</name>
|
|
<description>Mute detection flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRUDR</name>
|
|
<description>Clear overrun / underrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDR</name>
|
|
<displayName>BDR</displayName>
|
|
<description>BData register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR1</name>
|
|
<displayName>ACR1</displayName>
|
|
<description>AConfiguration register 1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000040</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCKEN</name>
|
|
<description>MCKEN</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSR</name>
|
|
<description>OSR</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MCJDIV</name>
|
|
<description>Master clock divider</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NODIV</name>
|
|
<description>No divider</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SAIAEN</name>
|
|
<description>Audio block A enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OutDri</name>
|
|
<description>Output drive</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONO</name>
|
|
<description>Mono mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCEN</name>
|
|
<description>Synchronization enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKSTR</name>
|
|
<description>Clock strobing edge</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSBFIRST</name>
|
|
<description>Least significant bit first</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DS</name>
|
|
<description>Data size</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRTCFG</name>
|
|
<description>Protocol configuration</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>Audio block mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACR2</name>
|
|
<displayName>ACR2</displayName>
|
|
<description>AConfiguration register 2</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP</name>
|
|
<description>Companding mode</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPL</name>
|
|
<description>Complement bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTECN</name>
|
|
<description>Mute counter</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEVAL</name>
|
|
<description>Mute value</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTE</name>
|
|
<description>Mute</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIS</name>
|
|
<description>Tristate management on data line</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FFLUS</name>
|
|
<description>FIFO flush</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FTH</name>
|
|
<description>FIFO threshold</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRCR</name>
|
|
<displayName>AFRCR</displayName>
|
|
<description>AFRCR</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000007</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FSOFF</name>
|
|
<description>Frame synchronization offset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSPOL</name>
|
|
<description>Frame synchronization polarity</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSDEF</name>
|
|
<description>Frame synchronization definition</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSALL</name>
|
|
<description>Frame synchronization active level length</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRL</name>
|
|
<description>Frame length</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASLOTR</name>
|
|
<displayName>ASLOTR</displayName>
|
|
<description>ASlot register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLOTEN</name>
|
|
<description>Slot enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBSLOT</name>
|
|
<description>Number of slots in an audio frame</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLOTSZ</name>
|
|
<description>Slot size</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FBOFF</name>
|
|
<description>First bit offset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIM</name>
|
|
<displayName>AIM</displayName>
|
|
<description>AInterrupt mask register2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LFSDET</name>
|
|
<description>Late frame synchronization detection interrupt enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSDETIE</name>
|
|
<description>Anticipated frame synchronization detection interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNRDYIE</name>
|
|
<description>Codec not ready interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQIE</name>
|
|
<description>FIFO request interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCKCFG</name>
|
|
<description>Wrong clock configuration interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEDET</name>
|
|
<description>Mute detection interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRUDRIE</name>
|
|
<description>Overrun/underrun interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ASR</name>
|
|
<displayName>ASR</displayName>
|
|
<description>AStatus register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLVL</name>
|
|
<description>FIFO level threshold</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LFSDET</name>
|
|
<description>Late frame synchronization detection</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSDET</name>
|
|
<description>Anticipated frame synchronization detection</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNRDY</name>
|
|
<description>Codec not ready</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQ</name>
|
|
<description>FIFO request</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCKCFG</name>
|
|
<description>Wrong clock configuration flag. This bit is read only</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEDET</name>
|
|
<description>Mute detection</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRUDR</name>
|
|
<description>Overrun / underrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACLRFR</name>
|
|
<displayName>ACLRFR</displayName>
|
|
<description>AClear flag register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LFSDET</name>
|
|
<description>Clear late frame synchronization detection flag</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CAFSDET</name>
|
|
<description>Clear anticipated frame synchronization detection flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNRDY</name>
|
|
<description>Clear codec not ready flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WCKCFG</name>
|
|
<description>Clear wrong clock configuration flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUTEDET</name>
|
|
<description>Mute detection flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVRUDR</name>
|
|
<description>Clear overrun / underrun</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ADR</name>
|
|
<displayName>ADR</displayName>
|
|
<description>AData register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>Data</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDMCR</name>
|
|
<displayName>PDMCR</displayName>
|
|
<description>PDM control register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PDMEN</name>
|
|
<description>PDMEN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MICNBR</name>
|
|
<description>MICNBR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN1</name>
|
|
<description>CKEN1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN2</name>
|
|
<description>CKEN2</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN3</name>
|
|
<description>CKEN3</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CKEN4</name>
|
|
<description>CKEN4</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PDMDLY</name>
|
|
<displayName>PDMDLY</displayName>
|
|
<description>PDM delay register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DLYM1L</name>
|
|
<description>DLYM1L</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYM1R</name>
|
|
<description>DLYM1R</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYM2L</name>
|
|
<description>DLYM2L</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYM2R</name>
|
|
<description>DLYM2R</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYM3L</name>
|
|
<description>DLYM3L</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYM3R</name>
|
|
<description>DLYM3R</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYM4L</name>
|
|
<description>DLYM4L</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DLYM4R</name>
|
|
<description>DLYM4R</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TAMP</name>
|
|
<description>Tamper and backup registers</description>
|
|
<groupName>TAMP</groupName>
|
|
<baseAddress>0x40002400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMP1E</name>
|
|
<description>TAMP1E</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP2E</name>
|
|
<description>TAMP2E</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP3E</name>
|
|
<description>TAMP2E</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP3E</name>
|
|
<description>ITAMP3E</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP4E</name>
|
|
<description>ITAMP4E</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP5E</name>
|
|
<description>ITAMP5E</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP6E</name>
|
|
<description>ITAMP6E</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMP1NOER</name>
|
|
<description>TAMP1NOER</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP2NOER</name>
|
|
<description>TAMP2NOER</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP3NOER</name>
|
|
<description>TAMP3NOER</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP1MSK</name>
|
|
<description>TAMP1MSK</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP2MSK</name>
|
|
<description>TAMP2MSK</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP3MSK</name>
|
|
<description>TAMP3MSK</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP1TRG</name>
|
|
<description>TAMP1TRG</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP2TRG</name>
|
|
<description>TAMP2TRG</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP3TRG</name>
|
|
<description>TAMP3TRG</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FLTCR</name>
|
|
<displayName>FLTCR</displayName>
|
|
<description>TAMP filter control register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMPFREQ</name>
|
|
<description>TAMPFREQ</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPFLT</name>
|
|
<description>TAMPFLT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPPRCH</name>
|
|
<description>TAMPPRCH</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMPPUDIS</name>
|
|
<description>TAMPPUDIS</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>TAMP interrupt enable register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMP1IE</name>
|
|
<description>TAMP1IE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP2IE</name>
|
|
<description>TAMP2IE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP3IE</name>
|
|
<description>TAMP3IE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP3IE</name>
|
|
<description>ITAMP3IE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP4IE</name>
|
|
<description>ITAMP4IE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP5IE</name>
|
|
<description>ITAMP5IE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP6IE</name>
|
|
<description>ITAMP6IE</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>TAMP status register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMP1F</name>
|
|
<description>TAMP1F</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP2F</name>
|
|
<description>TAMP2F</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP3F</name>
|
|
<description>TAMP3F</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP3F</name>
|
|
<description>ITAMP3F</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP4F</name>
|
|
<description>ITAMP4F</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP5F</name>
|
|
<description>ITAMP5F</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP6F</name>
|
|
<description>ITAMP6F</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MISR</name>
|
|
<displayName>MISR</displayName>
|
|
<description>TAMP masked interrupt status register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TAMP1MF</name>
|
|
<description>TAMP1MF:</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP2MF</name>
|
|
<description>TAMP2MF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TAMP3MF</name>
|
|
<description>TAMP3MF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP3MF</name>
|
|
<description>ITAMP3MF</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP4MF</name>
|
|
<description>ITAMP4MF</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP5MF</name>
|
|
<description>ITAMP5MF</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITAMP6MF</name>
|
|
<description>ITAMP6MF</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<displayName>SCR</displayName>
|
|
<description>TAMP status clear register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CTAMP1F</name>
|
|
<description>CTAMP1F</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTAMP2F</name>
|
|
<description>CTAMP2F</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTAMP3F</name>
|
|
<description>CTAMP3F</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITAMP3F</name>
|
|
<description>CITAMP3F</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITAMP4F</name>
|
|
<description>CITAMP4F</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITAMP5F</name>
|
|
<description>CITAMP5F</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CITAMP6F</name>
|
|
<description>CITAMP6F</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP0R</name>
|
|
<displayName>BKP0R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP1R</name>
|
|
<displayName>BKP1R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP2R</name>
|
|
<displayName>BKP2R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP3R</name>
|
|
<displayName>BKP3R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP4R</name>
|
|
<displayName>BKP4R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP5R</name>
|
|
<displayName>BKP5R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP6R</name>
|
|
<displayName>BKP6R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP7R</name>
|
|
<displayName>BKP7R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP8R</name>
|
|
<displayName>BKP8R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP9R</name>
|
|
<displayName>BKP9R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x124</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP10R</name>
|
|
<displayName>BKP10R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x128</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP11R</name>
|
|
<displayName>BKP11R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x12C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP12R</name>
|
|
<displayName>BKP12R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x130</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP13R</name>
|
|
<displayName>BKP13R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x134</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP14R</name>
|
|
<displayName>BKP14R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x138</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP15R</name>
|
|
<displayName>BKP15R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x13C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP16R</name>
|
|
<displayName>BKP16R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x140</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP17R</name>
|
|
<displayName>BKP17R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x144</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP18R</name>
|
|
<displayName>BKP18R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x148</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP19R</name>
|
|
<displayName>BKP19R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x14C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP20R</name>
|
|
<displayName>BKP20R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x150</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP21R</name>
|
|
<displayName>BKP21R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x154</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP22R</name>
|
|
<displayName>BKP22R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x158</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP23R</name>
|
|
<displayName>BKP23R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x15C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP24R</name>
|
|
<displayName>BKP24R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x160</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP25R</name>
|
|
<displayName>BKP25R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x164</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP26R</name>
|
|
<displayName>BKP26R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x168</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP27R</name>
|
|
<displayName>BKP27R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x16C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP28R</name>
|
|
<displayName>BKP28R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x170</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP29R</name>
|
|
<displayName>BKP29R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x174</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP30R</name>
|
|
<displayName>BKP30R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x178</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP31R</name>
|
|
<displayName>BKP31R</displayName>
|
|
<description>TAMP backup register</description>
|
|
<addressOffset>0x17C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>BKP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FPU</name>
|
|
<description>Floting point unit</description>
|
|
<groupName>FPU</groupName>
|
|
<baseAddress>0xE000EF34</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0xD</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FPU</name>
|
|
<description>Floating point unit interrupt</description>
|
|
<value>81</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>FPCCR</name>
|
|
<displayName>FPCCR</displayName>
|
|
<description>Floating-point context control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSPACT</name>
|
|
<description>LSPACT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USER</name>
|
|
<description>USER</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>THREAD</name>
|
|
<description>THREAD</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HFRDY</name>
|
|
<description>HFRDY</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMRDY</name>
|
|
<description>MMRDY</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFRDY</name>
|
|
<description>BFRDY</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONRDY</name>
|
|
<description>MONRDY</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSPEN</name>
|
|
<description>LSPEN</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ASPEN</name>
|
|
<description>ASPEN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPCAR</name>
|
|
<displayName>FPCAR</displayName>
|
|
<description>Floating-point context address register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADDRESS</name>
|
|
<description>Location of unpopulated floating-point</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FPSCR</name>
|
|
<displayName>FPSCR</displayName>
|
|
<description>Floating-point status control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IOC</name>
|
|
<description>Invalid operation cumulative exception bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DZC</name>
|
|
<description>Division by zero cumulative exception bit.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OFC</name>
|
|
<description>Overflow cumulative exception bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UFC</name>
|
|
<description>Underflow cumulative exception bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IXC</name>
|
|
<description>Inexact cumulative exception bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDC</name>
|
|
<description>Input denormal cumulative exception bit.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMode</name>
|
|
<description>Rounding Mode control field</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FZ</name>
|
|
<description>Flush-to-zero mode control bit:</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DN</name>
|
|
<description>Default NaN mode control bit</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AHP</name>
|
|
<description>Alternative half-precision control bit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>V</name>
|
|
<description>Overflow condition code flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C</name>
|
|
<description>Carry condition code flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Z</name>
|
|
<description>Zero condition code flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>N</name>
|
|
<description>Negative condition code flag</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>MPU</name>
|
|
<description>Memory protection unit</description>
|
|
<groupName>MPU</groupName>
|
|
<baseAddress>0xE000E084</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x15</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>TYPER</name>
|
|
<displayName>TYPER</displayName>
|
|
<description>MPU type register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0X00000800</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SEPARATE</name>
|
|
<description>Separate flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DREGION</name>
|
|
<description>Number of MPU data regions</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IREGION</name>
|
|
<description>Number of MPU instruction regions</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<displayName>CTRL</displayName>
|
|
<description>MPU control register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Enables the MPU</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HFNMIENA</name>
|
|
<description>Enables the operation of MPU during hard fault</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIVDEFENA</name>
|
|
<description>Enable priviliged software access to default memory map</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RNR</name>
|
|
<displayName>RNR</displayName>
|
|
<description>MPU region number register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>MPU region</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RBAR</name>
|
|
<displayName>RBAR</displayName>
|
|
<description>MPU region base address register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REGION</name>
|
|
<description>MPU region field</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VALID</name>
|
|
<description>MPU region number valid</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Region base address field</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>27</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RASR</name>
|
|
<displayName>RASR</displayName>
|
|
<description>MPU region attribute and size register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Region enable bit.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SIZE</name>
|
|
<description>Size of the MPU protection region</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRD</name>
|
|
<description>Subregion disable bits</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>B</name>
|
|
<description>memory attribute</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C</name>
|
|
<description>memory attribute</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S</name>
|
|
<description>Shareable memory attribute</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEX</name>
|
|
<description>memory attribute</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AP</name>
|
|
<description>Access permission</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>XN</name>
|
|
<description>Instruction access disable bit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>STK</name>
|
|
<description>SysTick timer</description>
|
|
<groupName>STK</groupName>
|
|
<baseAddress>0xE000E010</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x11</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CTRL</name>
|
|
<displayName>CTRL</displayName>
|
|
<description>SysTick control and status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>Counter enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TICKINT</name>
|
|
<description>SysTick exception request enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKSOURCE</name>
|
|
<description>Clock source selection</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNTFLAG</name>
|
|
<description>COUNTFLAG</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LOAD</name>
|
|
<displayName>LOAD</displayName>
|
|
<description>SysTick reload value register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>RELOAD value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VAL</name>
|
|
<displayName>VAL</displayName>
|
|
<description>SysTick current value register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CURRENT</name>
|
|
<description>Current counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALIB</name>
|
|
<displayName>CALIB</displayName>
|
|
<description>SysTick calibration value register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0X00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TENMS</name>
|
|
<description>Calibration value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>24</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SKEW</name>
|
|
<description>SKEW flag: Indicates whether the TENMS value is exact</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOREF</name>
|
|
<description>NOREF flag. Reads as zero</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SCB</name>
|
|
<description>System control block</description>
|
|
<groupName>SCB</groupName>
|
|
<baseAddress>0xE000ED00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x41</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CPUID</name>
|
|
<displayName>CPUID</displayName>
|
|
<description>CPUID base register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x410FC241</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>Revision</name>
|
|
<description>Revision number</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PartNo</name>
|
|
<description>Part number of the processor</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Constant</name>
|
|
<description>Reads as 0xF</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Variant</name>
|
|
<description>Variant number</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Implementer</name>
|
|
<description>Implementer code</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSR</name>
|
|
<displayName>ICSR</displayName>
|
|
<description>Interrupt control and state register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VECTACTIVE</name>
|
|
<description>Active vector</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RETTOBASE</name>
|
|
<description>Return to base level</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VECTPENDING</name>
|
|
<description>Pending vector</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISRPENDING</name>
|
|
<description>Interrupt pending flag</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTCLR</name>
|
|
<description>SysTick exception clear-pending bit</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSTSET</name>
|
|
<description>SysTick exception set-pending bit</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVCLR</name>
|
|
<description>PendSV clear-pending bit</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVSET</name>
|
|
<description>PendSV set-pending bit</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NMIPENDSET</name>
|
|
<description>NMI set-pending bit.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>VTOR</name>
|
|
<displayName>VTOR</displayName>
|
|
<description>Vector table offset register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TBLOFF</name>
|
|
<description>Vector table base offset field</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>21</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AIRCR</name>
|
|
<displayName>AIRCR</displayName>
|
|
<description>Application interrupt and reset control register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VECTRESET</name>
|
|
<description>VECTRESET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VECTCLRACTIVE</name>
|
|
<description>VECTCLRACTIVE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSRESETREQ</name>
|
|
<description>SYSRESETREQ</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRIGROUP</name>
|
|
<description>PRIGROUP</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENDIANESS</name>
|
|
<description>ENDIANESS</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VECTKEYSTAT</name>
|
|
<description>Register key</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCR</name>
|
|
<displayName>SCR</displayName>
|
|
<description>System control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEPONEXIT</name>
|
|
<description>SLEEPONEXIT</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLEEPDEEP</name>
|
|
<description>SLEEPDEEP</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SEVEONPEND</name>
|
|
<description>Send Event on Pending bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<displayName>CCR</displayName>
|
|
<description>Configuration and control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NONBASETHRDENA</name>
|
|
<description>Configures how the processor enters Thread mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USERSETMPEND</name>
|
|
<description>USERSETMPEND</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGN__TRP</name>
|
|
<description>UNALIGN_ TRP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV_0_TRP</name>
|
|
<description>DIV_0_TRP</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFHFNMIGN</name>
|
|
<description>BFHFNMIGN</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STKALIGN</name>
|
|
<description>STKALIGN</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR1</name>
|
|
<displayName>SHPR1</displayName>
|
|
<description>System handler priority registers</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_4</name>
|
|
<description>Priority of system handler 4</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_5</name>
|
|
<description>Priority of system handler 5</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_6</name>
|
|
<description>Priority of system handler 6</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR2</name>
|
|
<displayName>SHPR2</displayName>
|
|
<description>System handler priority registers</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_11</name>
|
|
<description>Priority of system handler 11</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHPR3</name>
|
|
<displayName>SHPR3</displayName>
|
|
<description>System handler priority registers</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRI_14</name>
|
|
<description>Priority of system handler 14</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRI_15</name>
|
|
<description>Priority of system handler 15</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SHCSR</name>
|
|
<displayName>SHCSR</displayName>
|
|
<description>System handler control and state register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MEMFAULTACT</name>
|
|
<description>Memory management fault exception active bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTACT</name>
|
|
<description>Bus fault exception active bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTACT</name>
|
|
<description>Usage fault exception active bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLACT</name>
|
|
<description>SVC call active bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MONITORACT</name>
|
|
<description>Debug monitor active bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PENDSVACT</name>
|
|
<description>PendSV exception active bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSTICKACT</name>
|
|
<description>SysTick exception active bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTPENDED</name>
|
|
<description>Usage fault exception pending bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTPENDED</name>
|
|
<description>Memory management fault exception pending bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTPENDED</name>
|
|
<description>Bus fault exception pending bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SVCALLPENDED</name>
|
|
<description>SVC call pending bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEMFAULTENA</name>
|
|
<description>Memory management fault enable bit</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSFAULTENA</name>
|
|
<description>Bus fault enable bit</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USGFAULTENA</name>
|
|
<description>Usage fault enable bit</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFSR_UFSR_BFSR_MMFSR</name>
|
|
<displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
|
|
<description>Configurable fault status register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IACCVIOL</name>
|
|
<description>Instruction access violation flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUNSTKERR</name>
|
|
<description>Memory manager fault on unstacking for a return from exception</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSTKERR</name>
|
|
<description>Memory manager fault on stacking for exception entry.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MLSPERR</name>
|
|
<description>MLSPERR</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MMARVALID</name>
|
|
<description>Memory Management Fault Address Register (MMAR) valid flag</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IBUSERR</name>
|
|
<description>Instruction bus error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRECISERR</name>
|
|
<description>Precise data bus error</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IMPRECISERR</name>
|
|
<description>Imprecise data bus error</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNSTKERR</name>
|
|
<description>Bus fault on unstacking for a return from exception</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STKERR</name>
|
|
<description>Bus fault on stacking for exception entry</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSPERR</name>
|
|
<description>Bus fault on floating-point lazy state preservation</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BFARVALID</name>
|
|
<description>Bus Fault Address Register (BFAR) valid flag</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNDEFINSTR</name>
|
|
<description>Undefined instruction usage fault</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVSTATE</name>
|
|
<description>Invalid state usage fault</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INVPC</name>
|
|
<description>Invalid PC load usage fault</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOCP</name>
|
|
<description>No coprocessor usage fault.</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UNALIGNED</name>
|
|
<description>Unaligned access usage fault</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIVBYZERO</name>
|
|
<description>Divide by zero usage fault</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HFSR</name>
|
|
<displayName>HFSR</displayName>
|
|
<description>Hard fault status register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VECTTBL</name>
|
|
<description>Vector table hard fault</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCED</name>
|
|
<description>Forced hard fault</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DEBUG_VT</name>
|
|
<description>Reserved for Debug use</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MMFAR</name>
|
|
<displayName>MMFAR</displayName>
|
|
<description>Memory management fault address register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MMFAR</name>
|
|
<description>Memory management fault address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BFAR</name>
|
|
<displayName>BFAR</displayName>
|
|
<description>Bus fault address register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BFAR</name>
|
|
<description>Bus fault address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFSR</name>
|
|
<displayName>AFSR</displayName>
|
|
<description>Auxiliary fault status register</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IMPDEF</name>
|
|
<description>Implementation defined</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC</name>
|
|
<description>Nested Vectored Interrupt Controller</description>
|
|
<groupName>NVIC</groupName>
|
|
<baseAddress>0xE000E100</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ISER0</name>
|
|
<displayName>ISER0</displayName>
|
|
<description>Interrupt Set-Enable Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>SETENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISER1</name>
|
|
<displayName>ISER1</displayName>
|
|
<description>Interrupt Set-Enable Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>SETENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISER2</name>
|
|
<displayName>ISER2</displayName>
|
|
<description>Interrupt Set-Enable Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>SETENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISER3</name>
|
|
<displayName>ISER3</displayName>
|
|
<description>Interrupt Set-Enable Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETENA</name>
|
|
<description>SETENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICER0</name>
|
|
<displayName>ICER0</displayName>
|
|
<description>Interrupt Clear-Enable Register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>CLRENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICER1</name>
|
|
<displayName>ICER1</displayName>
|
|
<description>Interrupt Clear-Enable Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>CLRENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICER2</name>
|
|
<displayName>ICER2</displayName>
|
|
<description>Interrupt Clear-Enable Register</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>CLRENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICER3</name>
|
|
<displayName>ICER3</displayName>
|
|
<description>Interrupt Clear-Enable Register</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRENA</name>
|
|
<description>CLRENA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPR0</name>
|
|
<displayName>ISPR0</displayName>
|
|
<description>Interrupt Set-Pending Register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>SETPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPR1</name>
|
|
<displayName>ISPR1</displayName>
|
|
<description>Interrupt Set-Pending Register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>SETPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPR2</name>
|
|
<displayName>ISPR2</displayName>
|
|
<description>Interrupt Set-Pending Register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>SETPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISPR3</name>
|
|
<displayName>ISPR3</displayName>
|
|
<description>Interrupt Set-Pending Register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SETPEND</name>
|
|
<description>SETPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICPR0</name>
|
|
<displayName>ICPR0</displayName>
|
|
<description>Interrupt Clear-Pending Register</description>
|
|
<addressOffset>0x180</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>CLRPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICPR1</name>
|
|
<displayName>ICPR1</displayName>
|
|
<description>Interrupt Clear-Pending Register</description>
|
|
<addressOffset>0x184</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>CLRPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICPR2</name>
|
|
<displayName>ICPR2</displayName>
|
|
<description>Interrupt Clear-Pending Register</description>
|
|
<addressOffset>0x188</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>CLRPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICPR3</name>
|
|
<displayName>ICPR3</displayName>
|
|
<description>Interrupt Clear-Pending Register</description>
|
|
<addressOffset>0x18C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CLRPEND</name>
|
|
<description>CLRPEND</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IABR0</name>
|
|
<displayName>IABR0</displayName>
|
|
<description>Interrupt Active Bit Register</description>
|
|
<addressOffset>0x200</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>ACTIVE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IABR1</name>
|
|
<displayName>IABR1</displayName>
|
|
<description>Interrupt Active Bit Register</description>
|
|
<addressOffset>0x204</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>ACTIVE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IABR2</name>
|
|
<displayName>IABR2</displayName>
|
|
<description>Interrupt Active Bit Register</description>
|
|
<addressOffset>0x208</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>ACTIVE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IABR3</name>
|
|
<displayName>IABR3</displayName>
|
|
<description>Interrupt Active Bit Register</description>
|
|
<addressOffset>0x20C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACTIVE</name>
|
|
<description>ACTIVE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR0</name>
|
|
<displayName>IPR0</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x300</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR1</name>
|
|
<displayName>IPR1</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x304</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR2</name>
|
|
<displayName>IPR2</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR3</name>
|
|
<displayName>IPR3</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x30C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR4</name>
|
|
<displayName>IPR4</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x310</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR5</name>
|
|
<displayName>IPR5</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x314</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR6</name>
|
|
<displayName>IPR6</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x318</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR7</name>
|
|
<displayName>IPR7</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x31C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR8</name>
|
|
<displayName>IPR8</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x320</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR9</name>
|
|
<displayName>IPR9</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x324</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR10</name>
|
|
<displayName>IPR10</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x328</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR11</name>
|
|
<displayName>IPR11</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x32C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR12</name>
|
|
<displayName>IPR12</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x330</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR13</name>
|
|
<displayName>IPR13</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x334</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR14</name>
|
|
<displayName>IPR14</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x338</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR15</name>
|
|
<displayName>IPR15</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x33C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR16</name>
|
|
<displayName>IPR16</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x340</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR17</name>
|
|
<displayName>IPR17</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x344</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR18</name>
|
|
<displayName>IPR18</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x348</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR19</name>
|
|
<displayName>IPR19</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x34C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR20</name>
|
|
<displayName>IPR20</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x350</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IPR_N0</name>
|
|
<description>IPR_N0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N1</name>
|
|
<description>IPR_N1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N2</name>
|
|
<description>IPR_N2</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IPR_N3</name>
|
|
<description>IPR_N3</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IPR21</name>
|
|
<displayName>IPR21</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x354</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IPR22</name>
|
|
<displayName>IPR22</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x358</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IPR23</name>
|
|
<displayName>IPR23</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x35C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IPR24</name>
|
|
<displayName>IPR24</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x360</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
<register>
|
|
<name>IPR25</name>
|
|
<displayName>IPR25</displayName>
|
|
<description>Interrupt Priority Register</description>
|
|
<addressOffset>0x364</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>NVIC_STIR</name>
|
|
<description>Nested vectored interrupt
|
|
controller</description>
|
|
<groupName>NVIC</groupName>
|
|
<baseAddress>0xE000EF00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>STIR</name>
|
|
<displayName>STIR</displayName>
|
|
<description>Software trigger interrupt
|
|
register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTID</name>
|
|
<description>Software generated interrupt
|
|
ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FPU_CPACR</name>
|
|
<description>Floating point unit CPACR</description>
|
|
<groupName>FPU</groupName>
|
|
<baseAddress>0xE000ED88</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CPACR</name>
|
|
<displayName>CPACR</displayName>
|
|
<description>Coprocessor access control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CP</name>
|
|
<description>CP</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SCB_ACTLR</name>
|
|
<description>System control block ACTLR</description>
|
|
<groupName>SCB</groupName>
|
|
<baseAddress>0xE000E008</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x5</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>ACTRL</name>
|
|
<displayName>ACTRL</displayName>
|
|
<description>Auxiliary control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DISMCYCINT</name>
|
|
<description>DISMCYCINT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISDEFWBUF</name>
|
|
<description>DISDEFWBUF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISFOLD</name>
|
|
<description>DISFOLD</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISFPCA</name>
|
|
<description>DISFPCA</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DISOOFP</name>
|
|
<description>DISOOFP</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FDCAN</name>
|
|
<description>FDCAN</description>
|
|
<groupName>FDCAN</groupName>
|
|
<baseAddress>0x4000A400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CREL</name>
|
|
<displayName>CREL</displayName>
|
|
<description>FDCAN Core Release Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x32141218</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAY</name>
|
|
<description>DAY</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MON</name>
|
|
<description>MON</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>YEAR</name>
|
|
<description>YEAR</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUBSTEP</name>
|
|
<description>SUBSTEP</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STEP</name>
|
|
<description>STEP</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REL</name>
|
|
<description>REL</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ENDN</name>
|
|
<displayName>ENDN</displayName>
|
|
<description>FDCAN Core Release Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x87654321</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETV</name>
|
|
<description>ETV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DBTP</name>
|
|
<displayName>DBTP</displayName>
|
|
<description>This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000A33</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DSJW</name>
|
|
<description>DSJW</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTSEG2</name>
|
|
<description>DTSEG2</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DTSEG1</name>
|
|
<description>DTSEG1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBRP</name>
|
|
<description>DBRP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDC</name>
|
|
<description>TDC</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TEST</name>
|
|
<displayName>TEST</displayName>
|
|
<description>Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LBCK</name>
|
|
<description>LBCK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TX</name>
|
|
<description>TX</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RX</name>
|
|
<description>RX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RWD</name>
|
|
<displayName>RWD</displayName>
|
|
<description>The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WDC</name>
|
|
<description>WDC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WDV</name>
|
|
<description>WDV</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCCR</name>
|
|
<displayName>CCCR</displayName>
|
|
<description>For details about setting and resetting of single bits see Software initialization.</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INIT</name>
|
|
<description>INIT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCE</name>
|
|
<description>CCE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASM</name>
|
|
<description>ASM</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CSA</name>
|
|
<description>CSA</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CSR</name>
|
|
<description>CSR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MON</name>
|
|
<description>MON</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DAR</name>
|
|
<description>DAR</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEST</name>
|
|
<description>TEST</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FDOE</name>
|
|
<description>FDOE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BRSE</name>
|
|
<description>BRSE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PXHD</name>
|
|
<description>PXHD</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EFBI</name>
|
|
<description>EFBI</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXP</name>
|
|
<description>TXP</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NISO</name>
|
|
<description>NISO</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>NBTP</name>
|
|
<displayName>NBTP</displayName>
|
|
<description>FDCAN_NBTP</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x06000A03</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NTSEG2</name>
|
|
<description>NTSEG2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NTSEG1</name>
|
|
<description>NTSEG1</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NBRP</name>
|
|
<description>NBRP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NSJW</name>
|
|
<description>NSJW</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSCC</name>
|
|
<displayName>TSCC</displayName>
|
|
<description>FDCAN Timestamp Counter Configuration Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSS</name>
|
|
<description>TSS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCP</name>
|
|
<description>TCP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSCV</name>
|
|
<displayName>TSCV</displayName>
|
|
<description>FDCAN Timestamp Counter Value Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSC</name>
|
|
<description>TSC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOCC</name>
|
|
<displayName>TOCC</displayName>
|
|
<description>FDCAN Timeout Counter Configuration Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0xFFFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETOC</name>
|
|
<description>ETOC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TOS</name>
|
|
<description>TOS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TOP</name>
|
|
<description>TOP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TOCV</name>
|
|
<displayName>TOCV</displayName>
|
|
<description>FDCAN Timeout Counter Value Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TOC</name>
|
|
<description>TOC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECR</name>
|
|
<displayName>ECR</displayName>
|
|
<description>FDCAN Error Counter Register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TEC</name>
|
|
<description>TEC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>REC</name>
|
|
<description>TREC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RP</name>
|
|
<description>RP</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CEL</name>
|
|
<description>CEL</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSR</name>
|
|
<displayName>PSR</displayName>
|
|
<description>FDCAN Protocol Status Register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000707</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LEC</name>
|
|
<description>LEC</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACT</name>
|
|
<description>ACT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EP</name>
|
|
<description>EP</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>EW</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BO</name>
|
|
<description>BO</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DLEC</name>
|
|
<description>DLEC</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESI</name>
|
|
<description>RESI</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RBRS</name>
|
|
<description>RBRS</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REDL</name>
|
|
<description>REDL</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PXE</name>
|
|
<description>PXE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDCV</name>
|
|
<description>TDCV</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TDCR</name>
|
|
<displayName>TDCR</displayName>
|
|
<description>FDCAN Transmitter Delay Compensation Register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TDCF</name>
|
|
<description>TDCF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TDCO</name>
|
|
<description>TDCO</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IR</name>
|
|
<displayName>IR</displayName>
|
|
<description>The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RF0N</name>
|
|
<description>RF0N</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF0F</name>
|
|
<description>RF0F</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF0L</name>
|
|
<description>RF0L</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF1N</name>
|
|
<description>RF1N</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF1F</name>
|
|
<description>RF1F</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF1L</name>
|
|
<description>RF1L</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPM</name>
|
|
<description>HPM</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>TC</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCF</name>
|
|
<description>TCF</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFE</name>
|
|
<description>TFE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEFN</name>
|
|
<description>TEFN</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEFF</name>
|
|
<description>TEFF</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEFL</name>
|
|
<description>TEFL</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSW</name>
|
|
<description>TSW</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MRAF</name>
|
|
<description>MRAF</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TOO</name>
|
|
<description>TOO</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ELO</name>
|
|
<description>ELO</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP</name>
|
|
<description>EP</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EW</name>
|
|
<description>EW</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BO</name>
|
|
<description>BO</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDI</name>
|
|
<description>WDI</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEA</name>
|
|
<description>PEA</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PED</name>
|
|
<description>PED</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARA</name>
|
|
<description>ARA</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IE</name>
|
|
<displayName>IE</displayName>
|
|
<description>The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RF0NE</name>
|
|
<description>RF0NE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF0FE</name>
|
|
<description>RF0FE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF0LE</name>
|
|
<description>RF0LE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF1NE</name>
|
|
<description>RF1NE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF1FE</name>
|
|
<description>RF1FE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF1LE</name>
|
|
<description>RF1LE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HPME</name>
|
|
<description>HPME</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCE</name>
|
|
<description>TCE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCFE</name>
|
|
<description>TCFE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFEE</name>
|
|
<description>TFEE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEFNE</name>
|
|
<description>TEFNE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEFFE</name>
|
|
<description>TEFFE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEFLE</name>
|
|
<description>TEFLE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TSWE</name>
|
|
<description>TSWE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MRAFE</name>
|
|
<description>MRAFE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TOOE</name>
|
|
<description>TOOE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ELOE</name>
|
|
<description>ELOE</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EPE</name>
|
|
<description>EPE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EWE</name>
|
|
<description>EWE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOE</name>
|
|
<description>BOE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WDIE</name>
|
|
<description>WDIE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEAE</name>
|
|
<description>PEAE</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEDE</name>
|
|
<description>PEDE</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARAE</name>
|
|
<description>ARAE</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ILS</name>
|
|
<displayName>ILS</displayName>
|
|
<description>The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RxFIFO0</name>
|
|
<description>RxFIFO0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RxFIFO1</name>
|
|
<description>RxFIFO1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SMSG</name>
|
|
<description>SMSG</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFERR</name>
|
|
<description>TFERR</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MISC</name>
|
|
<description>MISC</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>BERR</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PERR</name>
|
|
<description>PERR</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ILE</name>
|
|
<displayName>ILE</displayName>
|
|
<description>Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EINT0</name>
|
|
<description>EINT0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EINT1</name>
|
|
<description>EINT1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXGFC</name>
|
|
<displayName>RXGFC</displayName>
|
|
<description>Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RRFE</name>
|
|
<description>RRFE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RRFS</name>
|
|
<description>RRFS</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ANFE</name>
|
|
<description>ANFE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ANFS</name>
|
|
<description>ANFS</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>F1OM</name>
|
|
<description>F1OM</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>F0OM</name>
|
|
<description>F0OM</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSS</name>
|
|
<description>LSS</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSE</name>
|
|
<description>LSE</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XIDAM</name>
|
|
<displayName>XIDAM</displayName>
|
|
<description>FDCAN Extended ID and Mask Register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1FFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EIDM</name>
|
|
<description>EIDM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>29</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HPMS</name>
|
|
<displayName>HPMS</displayName>
|
|
<description>This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BIDX</name>
|
|
<description>BIDX</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSI</name>
|
|
<description>MSI</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIDX</name>
|
|
<description>FIDX</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLST</name>
|
|
<description>FLST</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXF0S</name>
|
|
<displayName>RXF0S</displayName>
|
|
<description>FDCAN Rx FIFO 0 Status Register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>F0FL</name>
|
|
<description>F0FL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>F0GI</name>
|
|
<description>F0GI</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>F0PI</name>
|
|
<description>F0PI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>F0F</name>
|
|
<description>F0F</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF0L</name>
|
|
<description>RF0L</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXF0A</name>
|
|
<displayName>RXF0A</displayName>
|
|
<description>CAN Rx FIFO 0 Acknowledge Register</description>
|
|
<addressOffset>0x94</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>F0AI</name>
|
|
<description>F0AI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXF1S</name>
|
|
<displayName>RXF1S</displayName>
|
|
<description>FDCAN Rx FIFO 1 Status Register</description>
|
|
<addressOffset>0x98</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>F1FL</name>
|
|
<description>F1FL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>F1GI</name>
|
|
<description>F1GI</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>F1PI</name>
|
|
<description>F1PI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>F1F</name>
|
|
<description>F1F</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RF1L</name>
|
|
<description>RF1L</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXF1A</name>
|
|
<displayName>RXF1A</displayName>
|
|
<description>FDCAN Rx FIFO 1 Acknowledge Register</description>
|
|
<addressOffset>0x9C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>F1AI</name>
|
|
<description>F1AI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBC</name>
|
|
<displayName>TXBC</displayName>
|
|
<description>FDCAN Tx Buffer Configuration Register</description>
|
|
<addressOffset>0xC0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFQM</name>
|
|
<description>TFQM</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXFQS</name>
|
|
<displayName>TXFQS</displayName>
|
|
<description>The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).</description>
|
|
<addressOffset>0xC4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TFFL</name>
|
|
<description>TFFL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFGI</name>
|
|
<description>TFGI</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFQPI</name>
|
|
<description>TFQPI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TFQF</name>
|
|
<description>TFQF</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBRP</name>
|
|
<displayName>TXBRP</displayName>
|
|
<description>FDCAN Tx Buffer Request Pending Register</description>
|
|
<addressOffset>0xC8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRP</name>
|
|
<description>TRP</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBAR</name>
|
|
<displayName>TXBAR</displayName>
|
|
<description>FDCAN Tx Buffer Add Request Register</description>
|
|
<addressOffset>0xCC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AR</name>
|
|
<description>AR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBCR</name>
|
|
<displayName>TXBCR</displayName>
|
|
<description>FDCAN Tx Buffer Cancellation Request Register</description>
|
|
<addressOffset>0xD0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CR</name>
|
|
<description>CR</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBTO</name>
|
|
<displayName>TXBTO</displayName>
|
|
<description>FDCAN Tx Buffer Transmission Occurred Register</description>
|
|
<addressOffset>0xD4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TO</name>
|
|
<description>TO</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBCF</name>
|
|
<displayName>TXBCF</displayName>
|
|
<description>FDCAN Tx Buffer Cancellation Finished Register</description>
|
|
<addressOffset>0xD8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CF</name>
|
|
<description>CF</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBTIE</name>
|
|
<displayName>TXBTIE</displayName>
|
|
<description>FDCAN Tx Buffer Transmission Interrupt Enable Register</description>
|
|
<addressOffset>0xDC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>TIE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXBCIE</name>
|
|
<displayName>TXBCIE</displayName>
|
|
<description>FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register</description>
|
|
<addressOffset>0xE0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CFIE</name>
|
|
<description>CFIE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXEFS</name>
|
|
<displayName>TXEFS</displayName>
|
|
<description>FDCAN Tx Event FIFO Status Register</description>
|
|
<addressOffset>0xE4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EFFL</name>
|
|
<description>EFFL</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFGI</name>
|
|
<description>EFGI</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFPI</name>
|
|
<description>EFPI</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EFF</name>
|
|
<description>EFF</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TEFL</name>
|
|
<description>TEFL</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXEFA</name>
|
|
<displayName>TXEFA</displayName>
|
|
<description>FDCAN Tx Event FIFO Acknowledge Register</description>
|
|
<addressOffset>0xE8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EFAI</name>
|
|
<description>EFAI</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CKDIV</name>
|
|
<displayName>CKDIV</displayName>
|
|
<description>FDCAN CFG clock divider register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PDIV</name>
|
|
<description>input clock divider. the APB clock could be divided prior to be used by the CAN sub</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="FDCAN">
|
|
<name>FDCAN1</name>
|
|
<baseAddress>0x40006400</baseAddress>
|
|
<interrupt>
|
|
<name>fdcan1_intr1_it</name>
|
|
<description>FDCAN1 interrupt</description>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>fdcan1_intr0_it</name>
|
|
<description>FDCAN1 interrupt</description>
|
|
<value>22</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="FDCAN">
|
|
<name>FDCAN2</name>
|
|
<baseAddress>0x40006800</baseAddress>
|
|
<interrupt>
|
|
<name>FDCAN2_intr0</name>
|
|
<description>FDCAN2 interrupt</description>
|
|
<value>86</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>FDCAN2_intr1</name>
|
|
<description>FDCAN2 interrupt</description>
|
|
<value>87</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="FDCAN">
|
|
<name>FDCAN3</name>
|
|
<baseAddress>0x40006C00</baseAddress>
|
|
<interrupt>
|
|
<name>FDCAN3_intr0</name>
|
|
<description>FDCAN3 interrupt</description>
|
|
<value>88</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>FDCAN3_intr1</name>
|
|
<description>FDCAN3 interrupt</description>
|
|
<value>89</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>UCPD1</name>
|
|
<description>UCPD1</description>
|
|
<groupName>UCPD</groupName>
|
|
<baseAddress>0x4000A000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>UCPD1</name>
|
|
<description>UCPD1</description>
|
|
<value>63</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CFG1</name>
|
|
<displayName>CFG1</displayName>
|
|
<description>UCPD configuration register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HBITCLKDIV</name>
|
|
<description>HBITCLKDIV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IFRGAP</name>
|
|
<description>IFRGAP</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRANSWIN</name>
|
|
<description>TRANSWIN</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>5</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PSC_USBPDCLK</name>
|
|
<description>PSC_USBPDCLK</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXORDSETEN</name>
|
|
<description>RXORDSETEN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>TXDMAEN</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>RXDMAEN</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UCPDEN</name>
|
|
<description>UCPDEN</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFG2</name>
|
|
<displayName>CFG2</displayName>
|
|
<description>UCPD configuration register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXFILTDIS</name>
|
|
<description>RXFILTDIS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXFILT2N3</name>
|
|
<description>RXFILT2N3</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FORCECLK</name>
|
|
<description>FORCECLK</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WUPEN</name>
|
|
<description>WUPEN</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>UCPD configuration register 2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXMODE</name>
|
|
<description>TXMODE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXSEND</name>
|
|
<description>TXSEND</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXHRST</name>
|
|
<description>TXHRST</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXMODE</name>
|
|
<description>RXMODE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PHYRXEN</name>
|
|
<description>PHYRXEN</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PHYCCSEL</name>
|
|
<description>PHYCCSEL</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANASUBMODE</name>
|
|
<description>ANASUBMODE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ANAMODE</name>
|
|
<description>ANAMODE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCENABLE</name>
|
|
<description>CCENABLE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRSRXEN</name>
|
|
<description>FRSRXEN</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRSTX</name>
|
|
<description>FRSTX</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDCH</name>
|
|
<description>RDCH</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC1TCDIS</name>
|
|
<description>CC1TCDIS</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CC2TCDIS</name>
|
|
<description>CC2TCDIS</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<displayName>IMR</displayName>
|
|
<description>UCPD Interrupt Mask Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXISIE</name>
|
|
<description>TXISIE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGDISCIE</name>
|
|
<description>TXMSGDISCIE</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGSENTIE</name>
|
|
<description>TXMSGSENTIE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGABTIE</name>
|
|
<description>TXMSGABTIE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRSTDISCIE</name>
|
|
<description>HRSTDISCIE</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRSTSENTIE</name>
|
|
<description>HRSTSENTIE</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDIE</name>
|
|
<description>TXUNDIE</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>RXNEIE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXORDDETIE</name>
|
|
<description>RXORDDETIE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXHRSTDETIE</name>
|
|
<description>RXHRSTDETIE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOVRIE</name>
|
|
<description>RXOVRIE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXMSGENDIE</name>
|
|
<description>RXMSGENDIE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPECEVT1IE</name>
|
|
<description>TYPECEVT1IE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPECEVT2IE</name>
|
|
<description>TYPECEVT2IE</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRSEVTIE</name>
|
|
<description>FRSEVTIE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>UCPD Status Register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXIS</name>
|
|
<description>TXIS</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGDISC</name>
|
|
<description>TXMSGDISC</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGSENT</name>
|
|
<description>TXMSGSENT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGABT</name>
|
|
<description>TXMSGABT</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRSTDISC</name>
|
|
<description>HRSTDISC</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRSTSENT</name>
|
|
<description>HRSTSENT</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUND</name>
|
|
<description>TXUND</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>RXNE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXORDDET</name>
|
|
<description>RXORDDET</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXHRSTDET</name>
|
|
<description>RXHRSTDET</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOVR</name>
|
|
<description>RXOVR</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXMSGEND</name>
|
|
<description>RXMSGEND</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXERR</name>
|
|
<description>RXERR</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPECEVT1</name>
|
|
<description>TYPECEVT1</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPECEVT2</name>
|
|
<description>TYPECEVT2</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPEC_VSTATE_CC1</name>
|
|
<description>TYPEC_VSTATE_CC1</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPEC_VSTATE_CC2</name>
|
|
<description>TYPEC_VSTATE_CC2</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRSEVT</name>
|
|
<description>FRSEVT</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>UCPD Interrupt Clear Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXMSGDISCCF</name>
|
|
<description>TXMSGDISCCF</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGSENTCF</name>
|
|
<description>TXMSGSENTCF</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXMSGABTCF</name>
|
|
<description>TXMSGABTCF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRSTDISCCF</name>
|
|
<description>HRSTDISCCF</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HRSTSENTCF</name>
|
|
<description>HRSTSENTCF</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXUNDCF</name>
|
|
<description>TXUNDCF</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXORDDETCF</name>
|
|
<description>RXORDDETCF</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXHRSTDETCF</name>
|
|
<description>RXHRSTDETCF</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXOVRCF</name>
|
|
<description>RXOVRCF</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXMSGENDCF</name>
|
|
<description>RXMSGENDCF</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPECEVT1CF</name>
|
|
<description>TYPECEVT1CF</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TYPECEVT2CF</name>
|
|
<description>TYPECEVT2CF</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FRSEVTCF</name>
|
|
<description>FRSEVTCF</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX_ORDSET</name>
|
|
<displayName>TX_ORDSET</displayName>
|
|
<description>UCPD Tx Ordered Set Type Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXORDSET</name>
|
|
<description>TXORDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TX_PAYSZ</name>
|
|
<displayName>TX_PAYSZ</displayName>
|
|
<description>UCPD Tx Paysize Register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXPAYSZ</name>
|
|
<description>TXPAYSZ</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXDR</name>
|
|
<displayName>TXDR</displayName>
|
|
<description>UCPD Tx Data Register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXDATA</name>
|
|
<description>TXDATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_ORDSET</name>
|
|
<displayName>RX_ORDSET</displayName>
|
|
<description>UCPD Rx Ordered Set Register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXORDSET</name>
|
|
<description>RXORDSET</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXSOP3OF4</name>
|
|
<description>RXSOP3OF4</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXSOPKINVALID</name>
|
|
<description>RXSOPKINVALID</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_PAYSZ</name>
|
|
<displayName>RX_PAYSZ</displayName>
|
|
<description>UCPD Rx Paysize Register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXPAYSZ</name>
|
|
<description>RXPAYSZ</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>10</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXDR</name>
|
|
<displayName>RXDR</displayName>
|
|
<description>UCPD Rx Data Register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDATA</name>
|
|
<description>RXDATA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_ORDEXT1</name>
|
|
<displayName>RX_ORDEXT1</displayName>
|
|
<description>UCPD Rx Ordered Set Extension Register 1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXSOPX1</name>
|
|
<description>RXSOPX1</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RX_ORDEXT2</name>
|
|
<displayName>RX_ORDEXT2</displayName>
|
|
<description>UCPD Rx Ordered Set Extension Register 2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXSOPX2</name>
|
|
<description>RXSOPX2</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>20</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB_FS_device</name>
|
|
<description>USB_FS_device</description>
|
|
<groupName>USB</groupName>
|
|
<baseAddress>0x40005C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>EP0R</name>
|
|
<displayName>EP0R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP1R</name>
|
|
<displayName>EP1R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP2R</name>
|
|
<displayName>EP2R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP3R</name>
|
|
<displayName>EP3R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP4R</name>
|
|
<displayName>EP4R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP5R</name>
|
|
<displayName>EP5R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP6R</name>
|
|
<displayName>EP6R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP7R</name>
|
|
<displayName>EP7R</displayName>
|
|
<description>USB endpoint n register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EA</name>
|
|
<description>EA</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_TX</name>
|
|
<description>STAT_TX</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_TX</name>
|
|
<description>DTOG_TX</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_TX</name>
|
|
<description>CTR_TX</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_KIND</name>
|
|
<description>EP_KIND</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP_TYPE</name>
|
|
<description>EP_TYPE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SETUP</name>
|
|
<description>SETUP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STAT_RX</name>
|
|
<description>STAT_RX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DTOG_RX</name>
|
|
<description>DTOG_RX</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR_RX</name>
|
|
<description>CTR_RX</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTR</name>
|
|
<displayName>CNTR</displayName>
|
|
<description>USB control register</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FRES</name>
|
|
<description>FRES</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PDWN</name>
|
|
<description>PDWN</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LP_MODE</name>
|
|
<description>LP_MODE</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FSUSP</name>
|
|
<description>FSUSP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESUME</name>
|
|
<description>RESUME</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>L1RESUME</name>
|
|
<description>L1RESUME</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>L1REQM</name>
|
|
<description>L1REQM</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESOFM</name>
|
|
<description>ESOFM</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOFM</name>
|
|
<description>SOFM</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESETM</name>
|
|
<description>RESETM</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSPM</name>
|
|
<description>SUSPM</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WKUPM</name>
|
|
<description>WKUPM</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRM</name>
|
|
<description>ERRM</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMAOVRM</name>
|
|
<description>PMAOVRM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTRM</name>
|
|
<description>CTRM</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISTR</name>
|
|
<displayName>ISTR</displayName>
|
|
<description>USB interrupt status register</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EP_ID</name>
|
|
<description>EP_ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>DIR</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>L1REQ</name>
|
|
<description>L1REQ</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESOF</name>
|
|
<description>ESOF</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>SOF</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>RESET</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SUSP</name>
|
|
<description>SUSP</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WKUP</name>
|
|
<description>WKUP</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERR</name>
|
|
<description>ERR</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PMAOVR</name>
|
|
<description>PMAOVR</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTR</name>
|
|
<description>CTR</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FNR</name>
|
|
<displayName>FNR</displayName>
|
|
<description>USB frame number register</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FN</name>
|
|
<description>FN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSOF</name>
|
|
<description>LSOF</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK</name>
|
|
<description>LCK</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDM</name>
|
|
<description>RXDM</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXDP</name>
|
|
<description>RXDP</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DADDR</name>
|
|
<displayName>DADDR</displayName>
|
|
<description>USB device address</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD</name>
|
|
<description>ADD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EF</name>
|
|
<description>EF</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTABLE</name>
|
|
<displayName>BTABLE</displayName>
|
|
<description>Buffer table address</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BTABLE</name>
|
|
<description>BTABLE</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRS</name>
|
|
<description>CRS</description>
|
|
<groupName>CRS</groupName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>CRS control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00004000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYNCOKIE</name>
|
|
<description>SYNC event OK interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWARNIE</name>
|
|
<description>SYNC warning interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Synchronization or trimming error interrupt enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ESYNCIE</name>
|
|
<description>Expected SYNC interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTRIMEN</name>
|
|
<description>Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWSYNC</name>
|
|
<description>Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIM</name>
|
|
<description>HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2022BB7F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RELOAD</name>
|
|
<description>Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FELIM</name>
|
|
<description>Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCDIV</name>
|
|
<description>SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal.</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCSRC</name>
|
|
<description>SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal.</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCPOL</name>
|
|
<description>SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source.</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>CRS interrupt and status register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYNCOKF</name>
|
|
<description>SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWARNF</name>
|
|
<description>SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRF</name>
|
|
<description>Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESYNCF</name>
|
|
<description>Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCERR</name>
|
|
<description>SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCMISS</name>
|
|
<description>SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRIMOVF</name>
|
|
<description>Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FEDIR</name>
|
|
<description>Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target.</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FECAP</name>
|
|
<description>Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage.</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>CRS interrupt flag clear register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYNCOKC</name>
|
|
<description>SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYNCWARNC</name>
|
|
<description>SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRC</name>
|
|
<description>Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ESYNCC</name>
|
|
<description>Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|