From 75d8c8560d671b84212a458839d81e0d91a39314 Mon Sep 17 00:00:00 2001 From: bartool Date: Wed, 13 Dec 2023 21:26:21 +0100 Subject: [PATCH] working dac dma --- .mxproject | 16 +- .vscode/c_cpp_properties.json | 3 +- .vscode/launch.json | 22 + .vscode/settings.json | 5 + Core/Inc/opamp.h | 3 - Core/Inc/stm32g4xx_it.h | 2 +- Core/Src/dac.c | 40 +- Core/Src/dma.c | 3 - Core/Src/main.c | 142 +- Core/Src/opamp.c | 62 - Core/Src/stm32g4xx_it.c | 32 +- Core/Src/tim.c | 12 +- Makefile | 8 +- STM32G474xx.svd | 59063 ++++++++++++++++++++++++++++++++ stm32g474_dac_dma_demo.ioc | 68 +- 15 files changed, 59265 insertions(+), 216 deletions(-) create mode 100644 .vscode/launch.json create mode 100644 .vscode/settings.json create mode 100644 STM32G474xx.svd diff --git a/.mxproject b/.mxproject index 8c7542a..860f3b3 100644 --- a/.mxproject +++ b/.mxproject @@ -1,3 +1,11 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_def.h;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_bus.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_system.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_utils.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_crs.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ramfunc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_usart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_lpuart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_def.h;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_bus.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_system.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_utils.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_crs.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ramfunc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_usart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_lpuart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g474xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedMakefileFiles] +SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\dac.c;Core\Src\dma.c;Core\Src\usart.c;Core\Src\opamp.c;Core\Src\tim.c;Core\Src\stm32g4xx_it.c;Core\Src\stm32g4xx_hal_msp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;;; +HeaderPath=Drivers\STM32G4xx_HAL_Driver\Inc;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32G4xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32G474xx;USE_HAL_DRIVER;USE_HAL_DRIVER; + [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=9 @@ -27,11 +35,3 @@ SourceFolderListSize=1 SourcePath#0=..\Core\Src SourceFiles=; -[PreviousLibFiles] -LibFiles=Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_def.h;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_bus.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_system.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_utils.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_crs.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ramfunc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_usart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_lpuart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_def.h;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_bus.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_system.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_utils.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_crs.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ramfunc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_usart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_lpuart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_opamp_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g474xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; - -[PreviousUsedMakefileFiles] -SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\dac.c;Core\Src\dma.c;Core\Src\usart.c;Core\Src\opamp.c;Core\Src\tim.c;Core\Src\stm32g4xx_it.c;Core\Src\stm32g4xx_hal_msp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_opamp_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;;; -HeaderPath=Drivers\STM32G4xx_HAL_Driver\Inc;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32G4xx\Include;Drivers\CMSIS\Include;Core\Inc; -CDefines=USE_HAL_DRIVER;STM32G474xx;USE_HAL_DRIVER;USE_HAL_DRIVER; - diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json index 663bfbf..2362609 100644 --- a/.vscode/c_cpp_properties.json +++ b/.vscode/c_cpp_properties.json @@ -15,7 +15,8 @@ "STM32G474xx", "USE_HAL_DRIVER" ], - "compilerPath": "C:/MyApps/arm-gcc/arm-gnu-toolchain-12.2.mpacbti-bet1-mingw-w64-i686-arm-none-eabi/bin/arm-none-eabi-gcc.exe", + // "compilerPath": "C:/MyApps/arm-gcc/arm-gnu-toolchain-12.2.mpacbti-bet1-mingw-w64-i686-arm-none-eabi/bin/arm-none-eabi-gcc.exe", + "compilerPath": "C:/MyApps/arm-gcc/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-gcc.exe", "cStandard": "c11", "cppStandard": "gnu++17", "intelliSenseMode": "windows-gcc-x64" diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..1cba268 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,22 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "Cortex Debug", + "cwd": "${workspaceFolder}", + "executable": "build/${workspaceFolderBasename}.elf", + "request": "launch", + "type": "cortex-debug", + "runToEntryPoint": "main", + "servertype": "stlink", + "stlinkPath": "C:/MyApps/STM32CubeIDE/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.win32_2.1.100.202310302101/tools/bin/ST-LINK_gdbserver.exe", + // "serverpath": "C:/MyApps/STM32CubeIDE/STM32CubeIDE_1.14.0/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.stlink-gdb-server.win32_2.1.100.202310302101/tools/bin/ST-LINK_gdbserver.exe", + "stm32cubeprogrammer": "C:/MyApps/STM32CubeProgrammer/bin", + "device": "STM32G474RE", + "svdFile": "STM32G474xx.svd" + } + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..17f0091 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,5 @@ +{ + "files.associations": { + "main.h": "c" + } +} \ No newline at end of file diff --git a/Core/Inc/opamp.h b/Core/Inc/opamp.h index 867be5e..71c832d 100644 --- a/Core/Inc/opamp.h +++ b/Core/Inc/opamp.h @@ -34,14 +34,11 @@ extern "C" { extern OPAMP_HandleTypeDef hopamp4; -extern OPAMP_HandleTypeDef hopamp5; - /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_OPAMP4_Init(void); -void MX_OPAMP5_Init(void); /* USER CODE BEGIN Prototypes */ diff --git a/Core/Inc/stm32g4xx_it.h b/Core/Inc/stm32g4xx_it.h index 3c04575..81ea1e2 100644 --- a/Core/Inc/stm32g4xx_it.h +++ b/Core/Inc/stm32g4xx_it.h @@ -56,8 +56,8 @@ void DebugMon_Handler(void); void PendSV_Handler(void); void SysTick_Handler(void); void DMA1_Channel1_IRQHandler(void); -void DMA1_Channel2_IRQHandler(void); void EXTI15_10_IRQHandler(void); +void TIM7_DAC_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Src/dac.c b/Core/Src/dac.c index e42c92d..3cd3ae5 100644 --- a/Core/Src/dac.c +++ b/Core/Src/dac.c @@ -26,7 +26,6 @@ DAC_HandleTypeDef hdac4; DMA_HandleTypeDef hdma_dac4_ch1; -DMA_HandleTypeDef hdma_dac4_ch2; /* DAC4 init function */ void MX_DAC4_Init(void) @@ -52,7 +51,7 @@ void MX_DAC4_Init(void) /** DAC channel OUT1 config */ - sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ; + sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC; sConfig.DAC_DMADoubleDataMode = DISABLE; sConfig.DAC_SignedFormat = DISABLE; sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE; @@ -65,13 +64,6 @@ void MX_DAC4_Init(void) { Error_Handler(); } - - /** DAC channel OUT2 config - */ - if (HAL_DAC_ConfigChannel(&hdac4, &sConfig, DAC_CHANNEL_2) != HAL_OK) - { - Error_Handler(); - } /* USER CODE BEGIN DAC4_Init 2 */ /* USER CODE END DAC4_Init 2 */ @@ -96,7 +88,7 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) hdma_dac4_ch1.Init.Direction = DMA_MEMORY_TO_PERIPH; hdma_dac4_ch1.Init.PeriphInc = DMA_PINC_DISABLE; hdma_dac4_ch1.Init.MemInc = DMA_MINC_ENABLE; - hdma_dac4_ch1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_dac4_ch1.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; hdma_dac4_ch1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; hdma_dac4_ch1.Init.Mode = DMA_CIRCULAR; hdma_dac4_ch1.Init.Priority = DMA_PRIORITY_LOW; @@ -107,23 +99,6 @@ void HAL_DAC_MspInit(DAC_HandleTypeDef* dacHandle) __HAL_LINKDMA(dacHandle,DMA_Handle1,hdma_dac4_ch1); - /* DAC4_CH2 Init */ - hdma_dac4_ch2.Instance = DMA1_Channel2; - hdma_dac4_ch2.Init.Request = DMA_REQUEST_DAC4_CHANNEL2; - hdma_dac4_ch2.Init.Direction = DMA_MEMORY_TO_PERIPH; - hdma_dac4_ch2.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_dac4_ch2.Init.MemInc = DMA_MINC_ENABLE; - hdma_dac4_ch2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; - hdma_dac4_ch2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; - hdma_dac4_ch2.Init.Mode = DMA_CIRCULAR; - hdma_dac4_ch2.Init.Priority = DMA_PRIORITY_LOW; - if (HAL_DMA_Init(&hdma_dac4_ch2) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(dacHandle,DMA_Handle2,hdma_dac4_ch2); - /* USER CODE BEGIN DAC4_MspInit 1 */ /* USER CODE END DAC4_MspInit 1 */ @@ -143,7 +118,16 @@ void HAL_DAC_MspDeInit(DAC_HandleTypeDef* dacHandle) /* DAC4 DMA DeInit */ HAL_DMA_DeInit(dacHandle->DMA_Handle1); - HAL_DMA_DeInit(dacHandle->DMA_Handle2); + + /* DAC4 interrupt Deinit */ + /* USER CODE BEGIN DAC4:TIM7_DAC_IRQn disable */ + /** + * Uncomment the line below to disable the "TIM7_DAC_IRQn" interrupt + * Be aware, disabling shared interrupt may affect other IPs + */ + /* HAL_NVIC_DisableIRQ(TIM7_DAC_IRQn); */ + /* USER CODE END DAC4:TIM7_DAC_IRQn disable */ + /* USER CODE BEGIN DAC4_MspDeInit 1 */ /* USER CODE END DAC4_MspDeInit 1 */ diff --git a/Core/Src/dma.c b/Core/Src/dma.c index 63f923e..fc83efe 100644 --- a/Core/Src/dma.c +++ b/Core/Src/dma.c @@ -47,9 +47,6 @@ void MX_DMA_Init(void) /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); - /* DMA1_Channel2_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA1_Channel2_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(DMA1_Channel2_IRQn); } diff --git a/Core/Src/main.c b/Core/Src/main.c index 6a39d6c..3c51a14 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -1,20 +1,20 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" @@ -37,7 +37,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ - +#define DAC_LENGHT 16 /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ @@ -48,11 +48,14 @@ /* Private variables ---------------------------------------------------------*/ /* USER CODE BEGIN PV */ - +volatile uint8_t dac_no; +uint16_t dac_data_ch1[DAC_LENGHT]; +uint16_t dac_data_ch2[DAC_LENGHT]; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); +static void MX_NVIC_Init(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -63,9 +66,9 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { /* USER CODE BEGIN 1 */ @@ -94,16 +97,50 @@ int main(void) MX_DAC4_Init(); MX_LPUART1_UART_Init(); MX_OPAMP4_Init(); - MX_OPAMP5_Init(); MX_TIM7_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize interrupts */ + MX_NVIC_Init(); + /* USER CODE BEGIN 2 */ + for (size_t i = 0; i < DAC_LENGHT; i++) + { + if (i % 2 == 0) + { + dac_data_ch1[i] = 0; + dac_data_ch2[i] = 4095; + } + else + { + dac_data_ch1[i] = 4095; + dac_data_ch2[i] = 0; + } + } + + HAL_DAC_Start_DMA(&hdac4, DAC_CHANNEL_1, (uint32_t *)dac_data_ch1, DAC_LENGHT, DAC_ALIGN_12B_R); + // HAL_DAC_Start_DMA(&hdac4, DAC_CHANNEL_2, (uint32_t *)dac_data_ch2, DAC_LENGHT, DAC_ALIGN_12B_R); + // HAL_DAC_Start(&hdac4, DAC_CHANNEL_1); + // HAL_DAC_Start(&hdac4, DAC_CHANNEL_2); + HAL_OPAMP_Start(&hopamp4); + // HAL_OPAMP_Start(&hopamp5); + HAL_TIM_Base_Start_IT(&htim7); /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ + uint8_t i = 0; while (1) { + // HAL_DAC_SetValue(&hdac4, DAC_CHANNEL_1, DAC_ALIGN_12B_R, dac_data_ch1[i]); + // HAL_DAC_SetValue(&hdac4, DAC_CHANNEL_2, DAC_ALIGN_12B_R, dac_data_ch1[i++]); + + if (i >= DAC_LENGHT) + { + i = 0; + } + + // HAL_GPIO_TogglePin(LD2_GPIO_Port, LD2_Pin); + HAL_Delay(1000); + htim7.Instance->PSC = 100; /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ @@ -112,21 +149,21 @@ int main(void) } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; /** Configure the main internal regulator output voltage - */ + */ HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST); /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ + * in the RCC_OscInitTypeDef structure. + */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; @@ -142,9 +179,8 @@ void SystemClock_Config(void) } /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -156,14 +192,36 @@ void SystemClock_Config(void) } } -/* USER CODE BEGIN 4 */ +/** + * @brief NVIC Configuration. + * @retval None + */ +static void MX_NVIC_Init(void) +{ + /* TIM7_DAC_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(TIM7_DAC_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(TIM7_DAC_IRQn); +} +/* USER CODE BEGIN 4 */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + HAL_GPIO_TogglePin(LD2_GPIO_Port, LD2_Pin); +} + +void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) +{ + if (hdac->Instance == DAC4) + { + dac_no = 1; + } +} /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ @@ -175,14 +233,14 @@ void Error_Handler(void) /* USER CODE END Error_Handler_Debug */ } -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ diff --git a/Core/Src/opamp.c b/Core/Src/opamp.c index bea1157..d46936c 100644 --- a/Core/Src/opamp.c +++ b/Core/Src/opamp.c @@ -25,7 +25,6 @@ /* USER CODE END 0 */ OPAMP_HandleTypeDef hopamp4; -OPAMP_HandleTypeDef hopamp5; /* OPAMP4 init function */ void MX_OPAMP4_Init(void) @@ -53,33 +52,6 @@ void MX_OPAMP4_Init(void) /* USER CODE END OPAMP4_Init 2 */ -} -/* OPAMP5 init function */ -void MX_OPAMP5_Init(void) -{ - - /* USER CODE BEGIN OPAMP5_Init 0 */ - - /* USER CODE END OPAMP5_Init 0 */ - - /* USER CODE BEGIN OPAMP5_Init 1 */ - - /* USER CODE END OPAMP5_Init 1 */ - hopamp5.Instance = OPAMP5; - hopamp5.Init.PowerMode = OPAMP_POWERMODE_HIGHSPEED; - hopamp5.Init.Mode = OPAMP_FOLLOWER_MODE; - hopamp5.Init.NonInvertingInput = OPAMP_NONINVERTINGINPUT_DAC; - hopamp5.Init.InternalOutput = DISABLE; - hopamp5.Init.TimerControlledMuxmode = OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE; - hopamp5.Init.UserTrimming = OPAMP_TRIMMING_FACTORY; - if (HAL_OPAMP_Init(&hopamp5) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN OPAMP5_Init 2 */ - - /* USER CODE END OPAMP5_Init 2 */ - } void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* opampHandle) @@ -105,25 +77,6 @@ void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* opampHandle) /* USER CODE END OPAMP4_MspInit 1 */ } - else if(opampHandle->Instance==OPAMP5) - { - /* USER CODE BEGIN OPAMP5_MspInit 0 */ - - /* USER CODE END OPAMP5_MspInit 0 */ - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**OPAMP5 GPIO Configuration - PA8 ------> OPAMP5_VOUT - */ - GPIO_InitStruct.Pin = GPIO_PIN_8; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN OPAMP5_MspInit 1 */ - - /* USER CODE END OPAMP5_MspInit 1 */ - } } void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* opampHandle) @@ -144,21 +97,6 @@ void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* opampHandle) /* USER CODE END OPAMP4_MspDeInit 1 */ } - else if(opampHandle->Instance==OPAMP5) - { - /* USER CODE BEGIN OPAMP5_MspDeInit 0 */ - - /* USER CODE END OPAMP5_MspDeInit 0 */ - - /**OPAMP5 GPIO Configuration - PA8 ------> OPAMP5_VOUT - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8); - - /* USER CODE BEGIN OPAMP5_MspDeInit 1 */ - - /* USER CODE END OPAMP5_MspDeInit 1 */ - } } /* USER CODE BEGIN 1 */ diff --git a/Core/Src/stm32g4xx_it.c b/Core/Src/stm32g4xx_it.c index ba97cff..deca35d 100644 --- a/Core/Src/stm32g4xx_it.c +++ b/Core/Src/stm32g4xx_it.c @@ -56,7 +56,8 @@ /* External variables --------------------------------------------------------*/ extern DMA_HandleTypeDef hdma_dac4_ch1; -extern DMA_HandleTypeDef hdma_dac4_ch2; +extern DAC_HandleTypeDef hdac4; +extern TIM_HandleTypeDef htim7; /* USER CODE BEGIN EV */ /* USER CODE END EV */ @@ -213,20 +214,6 @@ void DMA1_Channel1_IRQHandler(void) /* USER CODE END DMA1_Channel1_IRQn 1 */ } -/** - * @brief This function handles DMA1 channel2 global interrupt. - */ -void DMA1_Channel2_IRQHandler(void) -{ - /* USER CODE BEGIN DMA1_Channel2_IRQn 0 */ - - /* USER CODE END DMA1_Channel2_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_dac4_ch2); - /* USER CODE BEGIN DMA1_Channel2_IRQn 1 */ - - /* USER CODE END DMA1_Channel2_IRQn 1 */ -} - /** * @brief This function handles EXTI line[15:10] interrupts. */ @@ -241,6 +228,21 @@ void EXTI15_10_IRQHandler(void) /* USER CODE END EXTI15_10_IRQn 1 */ } +/** + * @brief This function handles TIM7 global interrupt, DAC2 and DAC4 channel underrun error interrupts. + */ +void TIM7_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM7_DAC_IRQn 0 */ + + /* USER CODE END TIM7_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim7); + HAL_DAC_IRQHandler(&hdac4); + /* USER CODE BEGIN TIM7_DAC_IRQn 1 */ + + /* USER CODE END TIM7_DAC_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Core/Src/tim.c b/Core/Src/tim.c index 2dbe282..f32d83c 100644 --- a/Core/Src/tim.c +++ b/Core/Src/tim.c @@ -40,7 +40,7 @@ void MX_TIM7_Init(void) /* USER CODE END TIM7_Init 1 */ htim7.Instance = TIM7; - htim7.Init.Prescaler = 0; + htim7.Init.Prescaler = 1000; htim7.Init.CounterMode = TIM_COUNTERMODE_UP; htim7.Init.Period = 169; htim7.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; @@ -86,6 +86,16 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) /* USER CODE END TIM7_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM7_CLK_DISABLE(); + + /* TIM7 interrupt Deinit */ + /* USER CODE BEGIN TIM7:TIM7_DAC_IRQn disable */ + /** + * Uncomment the line below to disable the "TIM7_DAC_IRQn" interrupt + * Be aware, disabling shared interrupt may affect other IPs + */ + /* HAL_NVIC_DisableIRQ(TIM7_DAC_IRQn); */ + /* USER CODE END TIM7:TIM7_DAC_IRQn disable */ + /* USER CODE BEGIN TIM7_MspDeInit 1 */ /* USER CODE END TIM7_MspDeInit 1 */ diff --git a/Makefile b/Makefile index 73278cb..63c7b18 100644 --- a/Makefile +++ b/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [4.1.0] date: [Mon Dec 11 19:03:06 CET 2023] +# File automatically-generated by tool: [projectgenerator] version: [4.1.0] date: [Tue Dec 12 23:07:03 CET 2023] ########################################################################################################################## # ------------------------------------------------ @@ -39,7 +39,6 @@ C_SOURCES = \ Core/Src/main.c \ Core/Src/gpio.c \ Core/Src/dac.c \ -Core/Src/dma.c \ Core/Src/usart.c \ Core/Src/opamp.c \ Core/Src/tim.c \ @@ -66,7 +65,8 @@ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_opamp.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_opamp_ex.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim.c \ Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_tim_ex.c \ -Core/Src/system_stm32g4xx.c +Core/Src/system_stm32g4xx.c \ +Core/Src/dma.c # ASM sources ASM_SOURCES = \ @@ -199,4 +199,4 @@ clean: ####################################### -include $(wildcard $(BUILD_DIR)/*.d) -# *** EOF *** \ No newline at end of file +# *** EOF *** diff --git a/STM32G474xx.svd b/STM32G474xx.svd new file mode 100644 index 0000000..34d0ecd --- /dev/null +++ b/STM32G474xx.svd @@ -0,0 +1,59063 @@ + + + + STM32G474xx + 1.6 + STM32G474xx + + CM4 + r0p1 + little + true + true + 4 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + CRC + Cyclic redundancy check calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data register bits + 0 + 32 + + + + + IDR + IDR + Independent data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + General-purpose 8-bit data register bits + 0 + 32 + + + + + CR + CR + Control register + 0x8 + 0x20 + 0x00000000 + + + REV_OUT + Reverse output data + 7 + 1 + read-write + + + REV_IN + Reverse input data + 5 + 2 + read-write + + + POLYSIZE + Polynomial size + 3 + 2 + read-write + + + RESET + RESET bit + 0 + 1 + write-only + + + + + INIT + INIT + Initial CRC value + 0x10 + 0x20 + read-write + 0xFFFFFFFF + + + CRC_INIT + Programmable initial CRC value + 0 + 32 + + + + + POL + POL + polynomial + 0x14 + 0x20 + read-write + 0x04C11DB7 + + + POL + Programmable polynomial + 0 + 32 + + + + + + + IWDG + WinWATCHDOG + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value (write only, read 0x0000) + 0 + 16 + + + + + PR + PR + Prescaler register + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload value + 0 + 12 + + + + + SR + SR + Status register + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value update + 1 + 1 + + + PVU + Watchdog prescaler value update + 0 + 1 + + + + + WINR + WINR + Window register + 0x10 + 0x20 + read-write + 0x00000FFF + + + WIN + Watchdog counter window value + 0 + 12 + + + + + + + WWDG + System window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + 0x4 + 0x20 + read-write + 0x0000007F + + + WDGTB + Timer base + 11 + 3 + + + EWI + Early wakeup interrupt + 9 + 1 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early wakeup interrupt flag + 0 + 1 + + + + + + + I2C1 + Inter-integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1_EV + I2C1_EV + 31 + + + I2C1_ER + I2C1_ER + 32 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + PE + Peripheral enable + 0 + 1 + + + TXIE + TX Interrupt enable + 1 + 1 + + + RXIE + RX Interrupt enable + 2 + 1 + + + ADDRIE + Address match interrupt enable (slave only) + 3 + 1 + + + NACKIE + Not acknowledge received interrupt enable + 4 + 1 + + + STOPIE + STOP detection Interrupt enable + 5 + 1 + + + TCIE + Transfer Complete interrupt enable + 6 + 1 + + + ERRIE + Error interrupts enable + 7 + 1 + + + DNF + Digital noise filter + 8 + 4 + + + ANFOFF + Analog noise filter OFF + 12 + 1 + + + TXDMAEN + DMA transmission requests enable + 14 + 1 + + + RXDMAEN + DMA reception requests enable + 15 + 1 + + + SBC + Slave byte control + 16 + 1 + + + NOSTRETCH + Clock stretching disable + 17 + 1 + + + WUPEN + Wakeup from STOP enable + 18 + 1 + + + GCEN + General call enable + 19 + 1 + + + SMBHEN + SMBus Host address enable + 20 + 1 + + + SMBDEN + SMBus Device Default address enable + 21 + 1 + + + ALERTEN + SMBUS alert enable + 22 + 1 + + + PECEN + PEC enable + 23 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PECBYTE + Packet error checking byte + 26 + 1 + + + AUTOEND + Automatic end mode (master mode) + 25 + 1 + + + RELOAD + NBYTES reload mode + 24 + 1 + + + NBYTES + Number of bytes + 16 + 8 + + + NACK + NACK generation (slave mode) + 15 + 1 + + + STOP + Stop generation (master mode) + 14 + 1 + + + START + Start generation + 13 + 1 + + + HEAD10R + 10-bit address header only read direction (master receiver mode) + 12 + 1 + + + ADD10 + 10-bit addressing mode (master mode) + 11 + 1 + + + RD_WRN + Transfer direction (master mode) + 10 + 1 + + + SADD + Slave address bit (master mode) + 0 + 10 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x00000000 + + + OA1 + Interface address + 0 + 10 + + + OA1MODE + Own Address 1 10-bit mode + 10 + 1 + + + OA1EN + Own Address 1 enable + 15 + 1 + + + + + OAR2 + OAR2 + Own address register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + OA2 + Interface address + 1 + 7 + + + OA2MSK + Own Address 2 masks + 8 + 3 + + + OA2EN + Own Address 2 enable + 15 + 1 + + + + + TIMINGR + TIMINGR + Timing register + 0x10 + 0x20 + read-write + 0x00000000 + + + SCLL + SCL low period (master mode) + 0 + 8 + + + SCLH + SCL high period (master mode) + 8 + 8 + + + SDADEL + Data hold time + 16 + 4 + + + SCLDEL + Data setup time + 20 + 4 + + + PRESC + Timing prescaler + 28 + 4 + + + + + TIMEOUTR + TIMEOUTR + Status register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + TIMEOUTA + Bus timeout A + 0 + 12 + + + TIDLE + Idle clock timeout detection + 12 + 1 + + + TIMOUTEN + Clock timeout enable + 15 + 1 + + + TIMEOUTB + Bus timeout B + 16 + 12 + + + TEXTEN + Extended clock timeout enable + 31 + 1 + + + + + ISR + ISR + Interrupt and Status register + 0x18 + 0x20 + 0x00000001 + + + ADDCODE + Address match code (Slave mode) + 17 + 7 + read-only + + + DIR + Transfer direction (Slave mode) + 16 + 1 + read-only + + + BUSY + Bus busy + 15 + 1 + read-only + + + ALERT + SMBus alert + 13 + 1 + read-only + + + TIMEOUT + Timeout or t_low detection flag + 12 + 1 + read-only + + + PECERR + PEC Error in reception + 11 + 1 + read-only + + + OVR + Overrun/Underrun (slave mode) + 10 + 1 + read-only + + + ARLO + Arbitration lost + 9 + 1 + read-only + + + BERR + Bus error + 8 + 1 + read-only + + + TCR + Transfer Complete Reload + 7 + 1 + read-only + + + TC + Transfer Complete (master mode) + 6 + 1 + read-only + + + STOPF + Stop detection flag + 5 + 1 + read-only + + + NACKF + Not acknowledge received flag + 4 + 1 + read-only + + + ADDR + Address matched (slave mode) + 3 + 1 + read-only + + + RXNE + Receive data register not empty (receivers) + 2 + 1 + read-only + + + TXIS + Transmit interrupt status (transmitters) + 1 + 1 + read-write + + + TXE + Transmit data register empty (transmitters) + 0 + 1 + read-write + + + + + ICR + ICR + Interrupt clear register + 0x1C + 0x20 + write-only + 0x00000000 + + + ALERTCF + Alert flag clear + 13 + 1 + + + TIMOUTCF + Timeout detection flag clear + 12 + 1 + + + PECCF + PEC Error flag clear + 11 + 1 + + + OVRCF + Overrun/Underrun flag clear + 10 + 1 + + + ARLOCF + Arbitration lost flag clear + 9 + 1 + + + BERRCF + Bus error flag clear + 8 + 1 + + + STOPCF + Stop detection flag clear + 5 + 1 + + + NACKCF + Not Acknowledge flag clear + 4 + 1 + + + ADDRCF + Address Matched flag clear + 3 + 1 + + + + + PECR + PECR + PEC register + 0x20 + 0x20 + read-only + 0x00000000 + + + PEC + Packet error checking register + 0 + 8 + + + + + RXDR + RXDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RXDATA + 8-bit receive data + 0 + 8 + + + + + TXDR + TXDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TXDATA + 8-bit transmit data + 0 + 8 + + + + + + + I2C2 + 0x40005800 + + WWDG + Window Watchdog interrupt + 0 + + + I2C2_EV + I2C2_EV + 33 + + + I2C2_ER + I2C2_ER + 34 + + + + I2C3 + 0x40007800 + + I2C3_EV + I2C3_EV + 92 + + + I2C3_ER + I2C3_ER + 93 + + + + I2C4 + 0x40008400 + + I2C4_EV + I2C4_EV + 82 + + + I2C4_ER + I2C4_ER + 83 + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH + 4 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 4 + + + PRFTEN + Prefetch enable + 8 + 1 + + + ICEN + Instruction cache enable + 9 + 1 + + + DCEN + Data cache enable + 10 + 1 + + + ICRST + Instruction cache reset + 11 + 1 + + + DCRST + Data cache reset + 12 + 1 + + + RUN_PD + Flash Power-down mode during Low-power run mode + 13 + 1 + + + SLEEP_PD + Flash Power-down mode during Low-power sleep mode + 14 + 1 + + + DBG_SWEN + Debug software enable + 18 + 1 + + + + + PDKEYR + PDKEYR + Power down key register + 0x4 + 0x20 + write-only + 0x00000000 + + + PDKEYR + RUN_PD in FLASH_ACR key + 0 + 32 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEYR + KEYR + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEYR + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + PROGERR + Programming error + 3 + 1 + read-write + + + WRPERR + Write protected error + 4 + 1 + read-write + + + PGAERR + Programming alignment error + 5 + 1 + read-write + + + SIZERR + Size error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + MISERR + Fast programming data miss error + 8 + 1 + read-write + + + FASTERR + Fast programming error + 9 + 1 + read-write + + + RDERR + PCROP read error + 14 + 1 + read-write + + + OPTVERR + Option validity error + 15 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + PG + Programming + 0 + 1 + + + PER + Page erase + 1 + 1 + + + MER1 + Bank 1 Mass erase + 2 + 1 + + + PNB + Page number + 3 + 7 + + + STRT + Start + 16 + 1 + + + OPTSTRT + Options modification start + 17 + 1 + + + FSTPG + Fast programming + 18 + 1 + + + EOPIE + End of operation interrupt enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + RDERRIE + PCROP read error interrupt enable + 26 + 1 + + + OBL_LAUNCH + Force the option byte loading + 27 + 1 + + + SEC_PROT1 + SEC_PROT1 + 28 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + + + ECCR + ECCR + Flash ECC register + 0x18 + 0x20 + 0x00000000 + + + ADDR_ECC + ECC fail address + 0 + 19 + read-only + + + BK_ECC + BK_ECC + 21 + 1 + read-only + + + SYSF_ECC + SYSF_ECC + 22 + 1 + read-only + + + ECCIE + ECCIE + 24 + 1 + read-write + + + ECCC2 + ECC correction + 28 + 1 + read-write + + + ECCD2 + ECC2 detection + 29 + 1 + read-write + + + ECCC + ECC correction + 30 + 1 + read-write + + + ECCD + ECC detection + 31 + 1 + read-write + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0xF0000000 + + + RDP + Read protection level + 0 + 8 + + + BOR_LEV + BOR reset Level + 8 + 3 + + + nRST_STOP + nRST_STOP + 12 + 1 + + + nRST_STDBY + nRST_STDBY + 13 + 1 + + + nRST_SHDW + nRST_SHDW + 14 + 1 + + + IDWG_SW + Independent watchdog selection + 16 + 1 + + + IWDG_STOP + Independent watchdog counter freeze in Stop mode + 17 + 1 + + + IWDG_STDBY + Independent watchdog counter freeze in Standby mode + 18 + 1 + + + WWDG_SW + Window watchdog selection + 19 + 1 + + + nBOOT1 + Boot configuration + 23 + 1 + + + SRAM2_PE + SRAM2 parity check enable + 24 + 1 + + + SRAM2_RST + SRAM2 Erase when system reset + 25 + 1 + + + nSWBOOT0 + nSWBOOT0 + 26 + 1 + + + nBOOT0 + nBOOT0 + 27 + 1 + + + NRST_MODE + NRST_MODE + 28 + 2 + + + IRHEN + IRHEN + 30 + 1 + + + + + PCROP1SR + PCROP1SR + Flash Bank 1 PCROP Start address register + 0x24 + 0x20 + read-write + 0xFFFF0000 + + + PCROP1_STRT + Bank 1 PCROP area start offset + 0 + 15 + + + + + PCROP1ER + PCROP1ER + Flash Bank 1 PCROP End address register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + PCROP1_END + Bank 1 PCROP area end offset + 0 + 15 + + + PCROP_RDP + PCROP area preserved when RDP level decreased + 31 + 1 + + + + + WRP1AR + WRP1AR + Flash Bank 1 WRP area A address register + 0x2C + 0x20 + read-write + 0x00000000 + + + WRP1A_STRT + Bank 1 WRP first area start offset + 0 + 7 + + + WRP1A_END + Bank 1 WRP first area A end offset + 16 + 7 + + + + + WRP1BR + WRP1BR + Flash Bank 1 WRP area B address register + 0x30 + 0x20 + read-write + 0x00000000 + + + WRP1B_STRT + Bank 1 WRP second area B end offset + 0 + 7 + + + WRP1B_END + Bank 1 WRP second area B start offset + 16 + 7 + + + + + SEC1R + SEC1R + securable area bank1 register + 0x70 + 0x20 + read-write + 0xFF00FF00 + + + BOOT_LOCK + BOOT_LOCK + 16 + 1 + + + SEC_SIZE1 + SEC_SIZE1 + 0 + 8 + + + + + + + DBGMCU + Debug support + DBGMCU + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + Device Identifier + 0 + 16 + + + REV_ID + Revision Identifier + 16 + 16 + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + DBG_STANDBY + Debug Standby Mode + 2 + 1 + + + TRACE_IOEN + Trace pin assignment control + 5 + 1 + + + TRACE_MODE + Trace pin assignment control + 6 + 2 + + + + + APB1L_FZ + APB1L_FZ + APB Low Freeze Register 1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + Debug Timer 2 stopped when Core is halted + 0 + 1 + + + DBG_TIM3_STOP + TIM3 counter stopped when core is halted + 1 + 1 + + + DBG_TIM4_STOP + TIM4 counter stopped when core is halted + 2 + 1 + + + DBG_TIM5_STOP + TIM5 counter stopped when core is halted + 3 + 1 + + + DBG_TIMER6_STOP + Debug Timer 6 stopped when Core is halted + 4 + 1 + + + DBG_TIM7_STOP + TIM7 counter stopped when core is halted + 5 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when Core is halted + 12 + 1 + + + DBG_I2C1_STOP + I2C1 SMBUS timeout mode stopped when core is halted + 21 + 1 + + + DBG_I2C2_STOP + I2C2 SMBUS timeout mode stopped when core is halted + 22 + 1 + + + DBG_I2C3_STOP + I2C3 SMBUS timeout mode stopped when core is halted + 30 + 1 + + + DBG_LPTIMER_STOP + LPTIM1 counter stopped when core is halted + 31 + 1 + + + + + APB1H_FZ + APB1H_FZ + APB Low Freeze Register 2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_I2C4_STOP + DBG_I2C4_STOP + 1 + 1 + + + + + APB2_FZ + APB2_FZ + APB High Freeze Register + 0x10 + 0x20 + read-write + 0x0 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is halted + 11 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is halted + 13 + 1 + + + DBG_TIM15_STOP + TIM15 counter stopped when core is halted + 16 + 1 + + + DBG_TIM16_STOP + TIM16 counter stopped when core is halted + 17 + 1 + + + DBG_TIM17_STOP + TIM17 counter stopped when core is halted + 18 + 1 + + + DBG_TIM20_STOP + TIM20counter stopped when core is halted + 20 + 1 + + + DBG_HRTIM0_STOP + DBG_HRTIM0_STOP + 26 + 1 + + + DBG_HRTIM1_STOP + DBG_HRTIM0_STOP + 27 + 1 + + + DBG_HRTIM2_STOP + DBG_HRTIM0_STOP + 28 + 1 + + + DBG_HRTIM3_STOP + DBG_HRTIM0_STOP + 29 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000063 + + + PLLSYSRDY + Main PLL clock ready flag + 25 + 1 + read-only + + + PLLSYSON + Main PLL enable + 24 + 1 + read-write + + + HSECSSON + Clock security system enable + 19 + 1 + write-only + + + HSEBYP + HSE crystal oscillator bypass + 18 + 1 + read-write + + + HSERDY + HSE clock ready flag + 17 + 1 + read-only + + + HSEON + HSE clock enable + 16 + 1 + read-write + + + HSIRDY + HSI clock ready flag + 10 + 1 + read-only + + + HSIKERON + HSI always enable for peripheral kernels + 9 + 1 + read-write + + + HSION + HSI clock enable + 8 + 1 + read-write + + + + + ICSCR + ICSCR + Internal clock sources calibration register + 0x4 + 0x20 + 0x40000000 + + + HSICAL0 + Internal High Speed clock Calibration + 16 + 8 + read-only + + + HSITRIM + Internal High Speed clock trimming + 24 + 7 + read-write + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00000005 + + + MCOPRE + Microcontroller clock output prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock output + 24 + 4 + read-write + + + PPRE2 + APB high-speed prescaler (APB2) + 11 + 3 + read-write + + + PPRE1 + PB low-speed prescaler (APB1) + 8 + 3 + read-write + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + SWS + System clock switch status + 2 + 2 + read-only + + + SW + System clock switch + 0 + 2 + read-write + + + + + PLLSYSCFGR + PLLSYSCFGR + PLL configuration register + 0xC + 0x20 + read-write + 0x00001000 + + + PLLSYSPDIV + Main PLL division factor for PLLSAI2CLK + 27 + 5 + + + PLLSYSR + Main PLL division factor for PLLCLK (system clock) + 25 + 2 + + + PLLSYSREN + Main PLL PLLCLK output enable + 24 + 1 + + + PLLSYSQ + Main PLL division factor for PLLUSB1CLK(48 MHz clock) + 21 + 2 + + + PLLSYSQEN + Main PLL PLLUSB1CLK output enable + 20 + 1 + + + PLLSYSP + Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock) + 17 + 1 + + + PLLPEN + Main PLL PLLSAI3CLK output enable + 16 + 1 + + + PLLSYSN + Main PLL multiplication factor for VCO + 8 + 7 + + + PLLSYSM + Division factor for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock + 4 + 4 + + + PLLSRC + Main PLL, PLLSAI1 and PLLSAI2 entry clock source + 0 + 2 + + + + + CIER + CIER + Clock interrupt enable register + 0x18 + 0x20 + read-write + 0x00000000 + + + LSIRDYIE + LSI ready interrupt enable + 0 + 1 + + + LSERDYIE + LSE ready interrupt enable + 1 + 1 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + HSERDYIE + HSE ready interrupt enable + 4 + 1 + + + PLLSYSRDYIE + PLL ready interrupt enable + 5 + 1 + + + LSECSSIE + LSE clock security system interrupt enable + 9 + 1 + + + RC48RDYIE + HSI48 ready interrupt enable + 10 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + HSERDYF + HSE ready interrupt flag + 4 + 1 + + + PLLSYSRDYF + PLL ready interrupt flag + 5 + 1 + + + HSECSSF + Clock security system interrupt flag + 8 + 1 + + + LSECSSF + LSE Clock security system interrupt flag + 9 + 1 + + + RC48RDYF + HSI48 ready interrupt flag + 10 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + LSIRDYC + LSI ready interrupt clear + 0 + 1 + + + LSERDYC + LSE ready interrupt clear + 1 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + HSERDYC + HSE ready interrupt clear + 4 + 1 + + + PLLSYSRDYC + PLL ready interrupt clear + 5 + 1 + + + HSECSSC + Clock security system interrupt clear + 8 + 1 + + + LSECSSC + LSE Clock security system interrupt clear + 9 + 1 + + + RC48RDYC + HSI48 oscillator ready interrupt clear + 10 + 1 + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMA1RST + DMA1 reset + 0 + 1 + + + DMA2RST + DMA2 reset + 1 + 1 + + + DMAMUX1RST + DMAMUXRST + 2 + 1 + + + CORDICRST + CORDIC reset + 3 + 1 + + + MATRIXRST + MATRIX reset + 4 + 1 + + + FLITFRST_ + FLITF reset + 8 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x2C + 0x20 + read-write + 0x00000000 + + + GPIOARST + IO port A reset + 0 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + ADC12RST + ADC reset + 13 + 1 + + + ADC345RST_ + SAR ADC345 interface reset + 14 + 1 + + + DAC1RST_ + DAC1 interface reset + 16 + 1 + + + DAC2RST + DAC2 interface reset + 17 + 1 + + + DAC3RST + DAC3 interface reset + 18 + 1 + + + DAC4RST + DAC4 interface reset + 19 + 1 + + + CRYPTRST + Cryptography module reset + 24 + 1 + + + RNGRST + Random Number Generator module reset + 26 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x30 + 0x20 + read-write + 0x00000000 + + + FMCRST + Flexible memory controller reset + 0 + 1 + + + QUADSPI1RST + Quad SPI 1 module reset + 8 + 1 + + + + + APB1RSTR1 + APB1RSTR1 + APB1 peripheral reset register 1 + 0x38 + 0x20 + read-write + 0x00000000 + + + LPTIM1RST + Low Power Timer 1 reset + 31 + 1 + + + I2C3 + I2C3 interface reset + 30 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + FDCANRST + FDCAN reset + 25 + 1 + + + USBDRST + USBD reset + 23 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + UART5RST + UART5 reset + 20 + 1 + + + UART4RST + UART4 reset + 19 + 1 + + + USART3RST + USART3 reset + 18 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + CRSRST + Clock recovery system reset + 8 + 1 + + + TIM7RST + TIM7 timer reset + 5 + 1 + + + TIM6RST + TIM6 timer reset + 4 + 1 + + + TIM5RST + TIM5 timer reset + 3 + 1 + + + TIM4RST + TIM3 timer reset + 2 + 1 + + + TIM3RST + TIM3 timer reset + 1 + 1 + + + TIM2RST + TIM2 timer reset + 0 + 1 + + + + + APB1RSTR2 + APB1RSTR2 + APB1 peripheral reset register 2 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPUART1RST + Low-power UART 1 reset + 0 + 1 + + + I2C4RST + I2C4 reset + 1 + 1 + + + USBPDRST + USBPD reset + 8 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x40 + 0x20 + read-write + 0x00000000 + + + SYSCFGRST + System configuration (SYSCFG) reset + 0 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM8RST + TIM8 timer reset + 13 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI4RST + SPI 4 reset + 15 + 1 + + + TIM15RST + TIM15 timer reset + 16 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM20RST + Timer 20 reset + 20 + 1 + + + SAI1RST + Serial audio interface 1 (SAI1) reset + 21 + 1 + + + HRTIM1RST + HRTIMER reset + 26 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock enable register + 0x48 + 0x20 + read-write + 0x00000100 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + DMAMUXEN + DMAMUX clock enable + 2 + 1 + + + CORDICEN + CORDIC clock enable + 3 + 1 + + + FMACEN + FMAC clock enable + 4 + 1 + + + FLITFEN + FLITF clock enable + 8 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable register + 0x4C + 0x20 + read-write + 0x00000000 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + ADC12EN + ADC clock enable + 13 + 1 + + + ADC345EN + DCMI clock enable + 14 + 1 + + + DAC1 + AES accelerator clock enable + 16 + 1 + + + DAC2 + HASH clock enable + 17 + 1 + + + DAC3 + Random Number Generator clock enable + 18 + 1 + + + DAC4 + DAC4 clock enable + 19 + 1 + + + CRYPTEN + Cryptography clock enable + 24 + 1 + + + RNGEN + Random Number Generator clock enable + 26 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable register + 0x50 + 0x20 + read-write + 0x00000000 + + + FMCEN + Flexible memory controller clock enable + 0 + 1 + + + QUADSPI1EN + Quad SPI 1 module clock enable + 8 + 1 + + + + + APB1ENR1 + APB1ENR1 + APB1ENR1 + 0x58 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2 timer clock enable + 0 + 1 + + + TIM3EN + TIM3 timer clock enable + 1 + 1 + + + TIM4EN + TIM4 timer clock enable + 2 + 1 + + + TIM5EN + TIM5 timer clock enable + 3 + 1 + + + TIM6EN + TIM6 timer clock enable + 4 + 1 + + + TIM7EN + TIM7 timer clock enable + 5 + 1 + + + CRSEN + CRSclock enable + 8 + 1 + + + RTCAPBEN + RTC APB clock enable + 10 + 1 + + + WWDGEN + Window watchdog clock enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SP3EN + SPI3 clock enable + 15 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + USBDEN + USBDclock enable + 23 + 1 + + + FDCANEN + FDCAN clock enable + 25 + 1 + + + PWREN + Power interface clock enable + 28 + 1 + + + I2C3 + OPAMP interface clock enable + 30 + 1 + + + LPTIM1EN + Low power timer 1 clock enable + 31 + 1 + + + + + APB1ENR2 + APB1ENR2 + APB1 peripheral clock enable register 2 + 0x5C + 0x20 + read-write + 0x00000000 + + + LPUART1EN + Low power UART 1 clock enable + 0 + 1 + + + I2C4EN + I2C4 clock enable + 1 + 1 + + + USBPDEN + USBPD clock enable + 8 + 1 + + + + + APB2ENR + APB2ENR + APB2ENR + 0x60 + 0x20 + read-write + 0x00000000 + + + SYSCFGEN + SYSCFG clock enable + 0 + 1 + + + TIM1EN + TIM1 timer clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TIM8EN + TIM8 timer clock enable + 13 + 1 + + + USART1EN + USART1clock enable + 14 + 1 + + + SPI4EN + SPI 4 clock enable + 15 + 1 + + + TIM15EN + TIM15 timer clock enable + 16 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM17EN + TIM17 timer clock enable + 18 + 1 + + + TIM20EN + Timer 20 clock enable + 20 + 1 + + + SAI1EN + SAI1 clock enable + 21 + 1 + + + HRTIMEREN + HRTIMER clock enable + 26 + 1 + + + + + AHB1SMENR + AHB1SMENR + AHB1 peripheral clocks enable in Sleep and Stop modes register + 0x68 + 0x20 + read-write + 0x0000130F + + + DMA1SMEN + DMA1 clocks enable during Sleep and Stop modes + 0 + 1 + + + DMA2SMEN + DMA2 clocks enable during Sleep and Stop modes + 1 + 1 + + + DMAMUX1SMEN + DMAMUX clock enable during Sleep and Stop modes + 2 + 1 + + + CORDICSMEN + CORDIC clock enable during sleep mode + 3 + 1 + + + FLASHSMEN + Flash memory interface clocks enable during Sleep and Stop modes + 8 + 1 + + + SRAM1SMEN + SRAM1 interface clocks enable during Sleep and Stop modes + 9 + 1 + + + CRCSMEN + CRCSMEN + 12 + 1 + + + FMACSMEN + FMACSM clock enable + 4 + 1 + + + + + AHB2SMENR + AHB2SMENR + AHB2 peripheral clocks enable in Sleep and Stop modes register + 0x6C + 0x20 + read-write + 0x050F667F + + + GPIOASMEN + IO port A clocks enable during Sleep and Stop modes + 0 + 1 + + + GPIOBSMEN + IO port B clocks enable during Sleep and Stop modes + 1 + 1 + + + GPIOCSMEN + IO port C clocks enable during Sleep and Stop modes + 2 + 1 + + + GPIODSMEN + IO port D clocks enable during Sleep and Stop modes + 3 + 1 + + + GPIOESMEN + IO port E clocks enable during Sleep and Stop modes + 4 + 1 + + + GPIOFSMEN + IO port F clocks enable during Sleep and Stop modes + 5 + 1 + + + GPIOGSMEN + IO port G clocks enable during Sleep and Stop modes + 6 + 1 + + + SRAM2SMEN + SRAM2 interface clocks enable during Sleep and Stop modes + 9 + 1 + + + SRAM3SMEN + SRAM2 interface clocks enable during Sleep and Stop modes + 10 + 1 + + + AD12CSMEN + ADC clocks enable during Sleep and Stop modes + 13 + 1 + + + ADC345SMEN + DCMI clock enable during Sleep and Stop modes + 14 + 1 + + + DAC1SMEN + AES accelerator clocks enable during Sleep and Stop modes + 16 + 1 + + + DAC2SMEN + HASH clock enable during Sleep and Stop modes + 17 + 1 + + + DAC3SMEN + DAC3 clock enable during sleep mode + 18 + 1 + + + DAC4SMEN + DAC4 clock enable during sleep mode + 19 + 1 + + + CRYPTSMEN + Cryptography clock enable during sleep mode + 24 + 1 + + + RNGSMEN + Random Number Generator clock enable during sleep mode + 26 + 1 + + + + + AHB3SMENR + AHB3SMENR + AHB3 peripheral clocks enable in Sleep and Stop modes register + 0x70 + 0x20 + read-write + 0x000000101 + + + FMCSMEN + Flexible memory controller clocks enable during Sleep and Stop modes + 0 + 1 + + + QUADSPI1SMEN + QUAD SPI 1 module clock enable during sleep mode + 8 + 1 + + + + + APB1SMENR1 + APB1SMENR1 + APB1SMENR1 + 0x78 + 0x20 + read-write + 0xD2FECD3F + + + TIM2SMEN + TIM2 timer clocks enable during Sleep and Stop modes + 0 + 1 + + + TIM3SMEN + TIM3 timer clocks enable during Sleep and Stop modes + 1 + 1 + + + TIM4SMEN + TIM4 timer clocks enable during Sleep and Stop modes + 2 + 1 + + + TIM5SMEN + TIM5 timer clocks enable during Sleep and Stop modes + 3 + 1 + + + TIM6SMEN + TIM6 timer clocks enable during Sleep and Stop modes + 4 + 1 + + + TIM7SMEN + TIM7 timer clocks enable during Sleep and Stop modes + 5 + 1 + + + CRSSMEN + CRS clock enable during sleep mode + 8 + 1 + + + RTCAPBSMEN + RTC APB clock enable during Sleep and Stop modes + 10 + 1 + + + WWDGSMEN + Window watchdog clocks enable during Sleep and Stop modes + 11 + 1 + + + SPI2SMEN + SPI2 clocks enable during Sleep and Stop modes + 14 + 1 + + + SP3SMEN + SPI3 clocks enable during Sleep and Stop modes + 15 + 1 + + + USART2SMEN + USART2 clocks enable during Sleep and Stop modes + 17 + 1 + + + USART3SMEN + USART3 clocks enable during Sleep and Stop modes + 18 + 1 + + + UART4SMEN + UART4 clocks enable during Sleep and Stop modes + 19 + 1 + + + UART5SMEN + UART5 clocks enable during Sleep and Stop modes + 20 + 1 + + + I2C1SMEN + I2C1 clocks enable during Sleep and Stop modes + 21 + 1 + + + I2C2SMEN + I2C2 clocks enable during Sleep and Stop modes + 22 + 1 + + + I2C3SMEN + I2C3 clocks enable during Sleep and Stop modes + 23 + 1 + + + FDCANSMEN + FDCAN clock enable during sleep mode + 25 + 1 + + + PWRSMEN + Power interface clocks enable during Sleep and Stop modes + 28 + 1 + + + I2C3SMEN_3 + I2C 3 interface clock enable during sleep mode + 30 + 1 + + + LPTIM1SMEN + Low Power Timer1 clock enable during sleep mode + 31 + 1 + + + + + APB1SMENR2 + APB1SMENR2 + APB1 peripheral clocks enable in Sleep and Stop modes register 2 + 0x7C + 0x20 + read-write + 0x00000103 + + + LPUART1SMEN + Low power UART 1 clocks enable during Sleep and Stop modes + 0 + 1 + + + I2C4SMEN + I2C4 clocks enable during Sleep and Stop modes + 1 + 1 + + + USBPDSMEN + USB PD clock enable during sleep mode + 8 + 1 + + + + + APB2SMENR + APB2SMENR + APB2SMENR + 0x80 + 0x20 + read-write + 0x0437F801 + + + SYSCFGSMEN + SYSCFG clocks enable during Sleep and Stop modes + 0 + 1 + + + TIM1SMEN + TIM1 timer clocks enable during Sleep and Stop modes + 11 + 1 + + + SPI1SMEN + SPI1 clocks enable during Sleep and Stop modes + 12 + 1 + + + TIM8SMEN + TIM8 timer clocks enable during Sleep and Stop modes + 13 + 1 + + + USART1SMEN + USART1clocks enable during Sleep and Stop modes + 14 + 1 + + + SPI4SMEN + SPI4 timer clocks enable during Sleep and Stop modes + 15 + 1 + + + TIM15SMEN + TIM15 timer clocks enable during Sleep and Stop modes + 16 + 1 + + + TIM16SMEN + TIM16 timer clocks enable during Sleep and Stop modes + 17 + 1 + + + TIM17SMEN + TIM17 timer clocks enable during Sleep and Stop modes + 18 + 1 + + + TIM20SMEN + Timer 20clock enable during sleep mode + 20 + 1 + + + SAI1SMEN + SAI1 clock enable during sleep mode + 21 + 1 + + + HRTIMERSMEN + HRTIMER clock enable during sleep mode + 26 + 1 + + + + + CCIPR1 + CCIPR1 + CCIPR + 0x88 + 0x20 + read-write + 0x00000000 + + + ADC345SEL + ADC3/4/5 clock source selection + 30 + 2 + + + ADCSEL + ADCs clock source selection + 28 + 2 + + + CLK48SEL + 48 MHz clock source selection + 26 + 2 + + + FDCANSEL + SAI2 clock source selection + 24 + 2 + + + SPISEL_ + SAI1 clock source selection + 22 + 2 + + + SAISEL + Low power timer 2 clock source selection + 20 + 2 + + + LPTIM1SEL + Low power timer 1 clock source selection + 18 + 2 + + + I2C3SEL + I2C3 clock source selection + 16 + 2 + + + I2C2SEL + I2C2 clock source selection + 14 + 2 + + + I2C1SEL + I2C1 clock source selection + 12 + 2 + + + LPUART1SEL + LPUART1 clock source selection + 10 + 2 + + + UART5SEL + UART5 clock source selection + 8 + 2 + + + UART4SEL + UART4 clock source selection + 6 + 2 + + + USART3SEL + USART3 clock source selection + 4 + 2 + + + USART2SEL + USART2 clock source selection + 2 + 2 + + + USART1SEL + USART1 clock source selection + 0 + 2 + + + + + BDCR + BDCR + BDCR + 0x90 + 0x20 + 0x00000000 + + + LSCOSEL + Low speed clock output selection + 25 + 1 + read-write + + + LSCCOEN + Low speed clock output enable + 24 + 1 + read-write + + + VSWRST + Vswitch domain software reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + LSECSSD + LSECSSD + 6 + 1 + read-only + + + LSECSSON + LSECSSON + 5 + 1 + read-write + + + LSEDRV + SE oscillator drive capability + 3 + 2 + read-write + + + LSEBYP + LSE oscillator bypass + 2 + 1 + read-write + + + LSERDY + LSE oscillator ready + 1 + 1 + read-only + + + LSEON + LSE oscillator enable + 0 + 1 + read-write + + + + + CSR + CSR + CSR + 0x94 + 0x20 + 0x0C000000 + + + LPWRSTF + Low-power reset flag + 31 + 1 + read-only + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-only + + + WDGRSTF + Independent window watchdog reset flag + 29 + 1 + read-only + + + SFTRSTF + Software reset flag + 28 + 1 + read-only + + + BORRSTF + BOR flag + 27 + 1 + read-only + + + PADRSTF + Pad reset flag + 26 + 1 + read-only + + + OBLRSTF + Option byte loader reset flag + 25 + 1 + read-only + + + RMVF + Remove reset flag + 23 + 1 + read-write + + + LSIRDY + LSI oscillator ready + 1 + 1 + read-only + + + LSION + LSI oscillator enable + 0 + 1 + read-write + + + + + CRRCR + CRRCR + Clock recovery RC register + 0x98 + 0x20 + 0x00000000 + + + RC48ON + HSI48 clock enable + 0 + 1 + read-write + + + RC48RDY + HSI48 clock ready flag + 1 + 1 + read-only + + + RC48CAL + HSI48 clock calibration + 7 + 9 + read-only + + + + + CCIPR2 + CCIPR2 + Peripherals independent clock configuration register + 0x9C + 0x20 + read-write + 0x00000000 + + + I2C4SEL + I2C4 clock source selection + 0 + 2 + + + QUADSPISEL + Octospi clock source selection + 20 + 2 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00000200 + + + LPR + Low-power run + 14 + 1 + + + VOS + Voltage scaling range selection + 9 + 2 + + + DBP + Disable backup domain write protection + 8 + 1 + + + LPMS + Low-power mode selection + 0 + 3 + + + + + CR2 + CR2 + Power control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + PVMEN1 + Peripheral voltage monitoring 1 enable: VDDA vs. COMP min voltage + 4 + 1 + + + PLS + Power voltage detector level selection + 1 + 3 + + + PVDE + Power voltage detector enable + 0 + 1 + + + PVMEN2 + Peripheral voltage monitoring 2 enable: VDDA vs. Fast DAC min voltage + 5 + 1 + + + PVMEN3 + Peripheral voltage monitoring 3 enable: VDDA vs. ADC min voltage 1.62V + 6 + 1 + + + PVMEN4 + Peripheral voltage monitoring 4 enable: VDDA vs. OPAMP/DAC min voltage + 7 + 1 + + + + + CR3 + CR3 + Power control register 3 + 0x8 + 0x20 + read-write + 0X00008000 + + + EWUP1 + Enable Wakeup pin WKUP1 + 0 + 1 + + + EWUP2 + Enable Wakeup pin WKUP2 + 1 + 1 + + + EWUP3 + Enable Wakeup pin WKUP3 + 2 + 1 + + + EWUP4 + Enable Wakeup pin WKUP4 + 3 + 1 + + + EWUP5 + Enable Wakeup pin WKUP5 + 4 + 1 + + + RRS + SRAM2 retention in Standby mode + 8 + 1 + + + APC + Apply pull-up and pull-down configuration + 10 + 1 + + + UCPD1_STDBY + STDBY + 13 + 1 + + + UCPD1_DBDIS + DBDIS + 14 + 1 + + + EIWUL + Enable external WakeUp line + 15 + 1 + + + + + CR4 + CR4 + Power control register 4 + 0xC + 0x20 + read-write + 0x00000000 + + + VBRS + VBAT battery charging resistor selection + 9 + 1 + + + VBE + VBAT battery charging enable + 8 + 1 + + + WP5 + Wakeup pin WKUP5 polarity + 4 + 1 + + + WP4 + Wakeup pin WKUP4 polarity + 3 + 1 + + + WP3 + Wakeup pin WKUP3 polarity + 2 + 1 + + + WP2 + Wakeup pin WKUP2 polarity + 1 + 1 + + + WP1 + Wakeup pin WKUP1 polarity + 0 + 1 + + + + + SR1 + SR1 + Power status register 1 + 0x10 + 0x20 + read-only + 0x00000000 + + + WUFI + Wakeup flag internal + 15 + 1 + + + SBF + Standby flag + 8 + 1 + + + WUF5 + Wakeup flag 5 + 4 + 1 + + + WUF4 + Wakeup flag 4 + 3 + 1 + + + WUF3 + Wakeup flag 3 + 2 + 1 + + + WUF2 + Wakeup flag 2 + 1 + 1 + + + WUF1 + Wakeup flag 1 + 0 + 1 + + + + + SR2 + SR2 + Power status register 2 + 0x14 + 0x20 + read-only + 0x00000000 + + + PVMO4 + Peripheral voltage monitoring output: VDDA vs. 2.2 V + 15 + 1 + + + PVMO3 + Peripheral voltage monitoring output: VDDA vs. 1.62 V + 14 + 1 + + + PVMO2 + Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V + 13 + 1 + + + PVMO1 + Peripheral voltage monitoring output: VDDUSB vs. 1.2 V + 12 + 1 + + + PVDO + Power voltage detector output + 11 + 1 + + + VOSF + Voltage scaling flag + 10 + 1 + + + REGLPF + Low-power regulator flag + 9 + 1 + + + REGLPS + Low-power regulator started + 8 + 1 + + + + + SCR + SCR + Power status clear register + 0x18 + 0x20 + write-only + 0x00000000 + + + CSBF + Clear standby flag + 8 + 1 + + + CWUF5 + Clear wakeup flag 5 + 4 + 1 + + + CWUF4 + Clear wakeup flag 4 + 3 + 1 + + + CWUF3 + Clear wakeup flag 3 + 2 + 1 + + + CWUF2 + Clear wakeup flag 2 + 1 + 1 + + + CWUF1 + Clear wakeup flag 1 + 0 + 1 + + + + + PUCRA + PUCRA + Power Port A pull-up control register + 0x20 + 0x20 + read-write + 0x00000000 + + + PU15 + Port A pull-up bit y (y=0..15) + 15 + 1 + + + PU13 + Port A pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port A pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port A pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port A pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port A pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port A pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port A pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port A pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port A pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port A pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port A pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port A pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port A pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port A pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRA + PDCRA + Power Port A pull-down control register + 0x24 + 0x20 + read-write + 0x00000000 + + + PD14 + Port A pull-down bit y (y=0..15) + 14 + 1 + + + PD12 + Port A pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port A pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port A pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port A pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port A pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port A pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port A pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port A pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port A pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port A pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port A pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port A pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port A pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRB + PUCRB + Power Port B pull-up control register + 0x28 + 0x20 + read-write + 0x00000000 + + + PU15 + Port B pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port B pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port B pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port B pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port B pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port B pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port B pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port B pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port B pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port B pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port B pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port B pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port B pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port B pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port B pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port B pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRB + PDCRB + Power Port B pull-down control register + 0x2C + 0x20 + read-write + 0x00000000 + + + PD15 + Port B pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port B pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port B pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port B pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port B pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port B pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port B pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port B pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port B pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port B pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port B pull-down bit y (y=0..15) + 5 + 1 + + + PD3 + Port B pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port B pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port B pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port B pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRC + PUCRC + Power Port C pull-up control register + 0x30 + 0x20 + read-write + 0x00000000 + + + PU15 + Port C pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port C pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port C pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port C pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port C pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port C pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port C pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port C pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port C pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port C pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port C pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port C pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port C pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port C pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port C pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port C pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRC + PDCRC + Power Port C pull-down control register + 0x34 + 0x20 + read-write + 0x00000000 + + + PD15 + Port C pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port C pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port C pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port C pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port C pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port C pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port C pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port C pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port C pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port C pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port C pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port C pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port C pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port C pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port C pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port C pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRD + PUCRD + Power Port D pull-up control register + 0x38 + 0x20 + read-write + 0x00000000 + + + PU15 + Port D pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port D pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port D pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port D pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port D pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port D pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port D pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port D pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port D pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port D pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port D pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port D pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port D pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port D pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port D pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port D pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRD + PDCRD + Power Port D pull-down control register + 0x3C + 0x20 + read-write + 0x00000000 + + + PD15 + Port D pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port D pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port D pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port D pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port D pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port D pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port D pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port D pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port D pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port D pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port D pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port D pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port D pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port D pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port D pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port D pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRE + PUCRE + Power Port E pull-up control register + 0x40 + 0x20 + read-write + 0x00000000 + + + PU15 + Port E pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port E pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port E pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port E pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port E pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port E pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port E pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port E pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port E pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port E pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port E pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port E pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port E pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port E pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port E pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port E pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRE + PDCRE + Power Port E pull-down control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PD15 + Port E pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port E pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port E pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port E pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port E pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port E pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port E pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port E pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port E pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port E pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port E pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port E pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port E pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port E pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port E pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port E pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRF + PUCRF + Power Port F pull-up control register + 0x48 + 0x20 + read-write + 0x00000000 + + + PU15 + Port F pull-up bit y (y=0..15) + 15 + 1 + + + PU14 + Port F pull-up bit y (y=0..15) + 14 + 1 + + + PU13 + Port F pull-up bit y (y=0..15) + 13 + 1 + + + PU12 + Port F pull-up bit y (y=0..15) + 12 + 1 + + + PU11 + Port F pull-up bit y (y=0..15) + 11 + 1 + + + PU10 + Port F pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port F pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port F pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port F pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port F pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port F pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port F pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port F pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port F pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port F pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port F pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRF + PDCRF + Power Port F pull-down control register + 0x4C + 0x20 + read-write + 0x00000000 + + + PD15 + Port F pull-down bit y (y=0..15) + 15 + 1 + + + PD14 + Port F pull-down bit y (y=0..15) + 14 + 1 + + + PD13 + Port F pull-down bit y (y=0..15) + 13 + 1 + + + PD12 + Port F pull-down bit y (y=0..15) + 12 + 1 + + + PD11 + Port F pull-down bit y (y=0..15) + 11 + 1 + + + PD10 + Port F pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port F pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port F pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port F pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port F pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port F pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port F pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port F pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port F pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port F pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port F pull-down bit y (y=0..15) + 0 + 1 + + + + + PUCRG + PUCRG + Power Port G pull-up control register + 0x50 + 0x20 + read-write + 0x00000000 + + + PU10 + Port G pull-up bit y (y=0..15) + 10 + 1 + + + PU9 + Port G pull-up bit y (y=0..15) + 9 + 1 + + + PU8 + Port G pull-up bit y (y=0..15) + 8 + 1 + + + PU7 + Port G pull-up bit y (y=0..15) + 7 + 1 + + + PU6 + Port G pull-up bit y (y=0..15) + 6 + 1 + + + PU5 + Port G pull-up bit y (y=0..15) + 5 + 1 + + + PU4 + Port G pull-up bit y (y=0..15) + 4 + 1 + + + PU3 + Port G pull-up bit y (y=0..15) + 3 + 1 + + + PU2 + Port G pull-up bit y (y=0..15) + 2 + 1 + + + PU1 + Port G pull-up bit y (y=0..15) + 1 + 1 + + + PU0 + Port G pull-up bit y (y=0..15) + 0 + 1 + + + + + PDCRG + PDCRG + Power Port G pull-down control register + 0x54 + 0x20 + read-write + 0x00000000 + + + PD10 + Port G pull-down bit y (y=0..15) + 10 + 1 + + + PD9 + Port G pull-down bit y (y=0..15) + 9 + 1 + + + PD8 + Port G pull-down bit y (y=0..15) + 8 + 1 + + + PD7 + Port G pull-down bit y (y=0..15) + 7 + 1 + + + PD6 + Port G pull-down bit y (y=0..15) + 6 + 1 + + + PD5 + Port G pull-down bit y (y=0..15) + 5 + 1 + + + PD4 + Port G pull-down bit y (y=0..15) + 4 + 1 + + + PD3 + Port G pull-down bit y (y=0..15) + 3 + 1 + + + PD2 + Port G pull-down bit y (y=0..15) + 2 + 1 + + + PD1 + Port G pull-down bit y (y=0..15) + 1 + 1 + + + PD0 + Port G pull-down bit y (y=0..15) + 0 + 1 + + + + + CR5 + CR5 + Power control register 5 + 0x80 + 0x20 + read-write + 0x00000100 + + + R1MODE + Main regular range 1 mode + 0 + 1 + + + + + + + RNG + Random number generator + RNG + 0x50060800 + + 0x0 + 0x400 + registers + + + RNG + RNG + 90 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + CED + Clock error detection + 5 + 1 + + + IE + Interrupt enable + 3 + 1 + + + RNGEN + Random number generator enable + 2 + 1 + + + + + SR + SR + status register + 0x4 + 0x20 + 0x00000000 + + + SEIS + Seed error interrupt status + 6 + 1 + read-write + + + CEIS + Clock error interrupt status + 5 + 1 + read-write + + + SECS + Seed error current status + 2 + 1 + read-only + + + CECS + Clock error current status + 1 + 1 + read-only + + + DRDY + Data ready + 0 + 1 + read-only + + + + + DR + DR + data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RNDATA + Random data + 0 + 32 + + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x48000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xABFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOB + General-purpose I/Os + GPIO + 0x48000400 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFEBF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x000000C0 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000100 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOC + General-purpose I/Os + GPIO + 0x48000800 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + MODER15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = 0..15) + 15 + 1 + + + IDR14 + Port input data (y = 0..15) + 14 + 1 + + + IDR13 + Port input data (y = 0..15) + 13 + 1 + + + IDR12 + Port input data (y = 0..15) + 12 + 1 + + + IDR11 + Port input data (y = 0..15) + 11 + 1 + + + IDR10 + Port input data (y = 0..15) + 10 + 1 + + + IDR9 + Port input data (y = 0..15) + 9 + 1 + + + IDR8 + Port input data (y = 0..15) + 8 + 1 + + + IDR7 + Port input data (y = 0..15) + 7 + 1 + + + IDR6 + Port input data (y = 0..15) + 6 + 1 + + + IDR5 + Port input data (y = 0..15) + 5 + 1 + + + IDR4 + Port input data (y = 0..15) + 4 + 1 + + + IDR3 + Port input data (y = 0..15) + 3 + 1 + + + IDR2 + Port input data (y = 0..15) + 2 + 1 + + + IDR1 + Port input data (y = 0..15) + 1 + 1 + + + IDR0 + Port input data (y = 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = 0..15) + 15 + 1 + + + ODR14 + Port output data (y = 0..15) + 14 + 1 + + + ODR13 + Port output data (y = 0..15) + 13 + 1 + + + ODR12 + Port output data (y = 0..15) + 12 + 1 + + + ODR11 + Port output data (y = 0..15) + 11 + 1 + + + ODR10 + Port output data (y = 0..15) + 10 + 1 + + + ODR9 + Port output data (y = 0..15) + 9 + 1 + + + ODR8 + Port output data (y = 0..15) + 8 + 1 + + + ODR7 + Port output data (y = 0..15) + 7 + 1 + + + ODR6 + Port output data (y = 0..15) + 6 + 1 + + + ODR5 + Port output data (y = 0..15) + 5 + 1 + + + ODR4 + Port output data (y = 0..15) + 4 + 1 + + + ODR3 + Port output data (y = 0..15) + 3 + 1 + + + ODR2 + Port output data (y = 0..15) + 2 + 1 + + + ODR1 + Port output data (y = 0..15) + 1 + 1 + + + ODR0 + Port output data (y = 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + GPIO port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR0 + Port Reset bit + 0 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR8 + Port Reset bit + 8 + 1 + + + BR9 + Port Reset bit + 9 + 1 + + + BR10 + Port Reset bit + 10 + 1 + + + BR11 + Port Reset bit + 11 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR15 + Port Reset bit + 15 + 1 + + + + + + + GPIOD + 0x48000C00 + + + GPIOE + 0x48001000 + + + GPIOF + 0x48001400 + + + GPIOG + 0x48001800 + + + TIM15 + General purpose timers + TIM + 0x40014000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + DITHEN + Dithering Enable + 12 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS2 + Output idle state 2 (OC2 output) + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC2OF + Capture/Compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC2IF + Capture/compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + OC2M + OC2M + 12 + 3 + + + OC2PE + OC2PE + 11 + 1 + + + OC2FE + OC2FE + 10 + 1 + + + CC2S + CC2S + 8 + 2 + + + OC1CE + OC1CE + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + IC2F + 12 + 4 + + + IC2PSC + IC2PSC + 10 + 2 + + + CC2S + CC2S + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC2NP + Capture/Compare 2 complementary output polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BKDSRM + BKDSRM + 26 + 1 + + + BKBID + BKBID + 28 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTGF + Dead-time generator setup + 0 + 8 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM16 + General purpose timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + CEN + Counter enable + 0 + 1 + + + UDIS + Update disable + 1 + 1 + + + URS + Update request source + 2 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CKD + Clock division + 8 + 2 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + DITHEN + Dithering Enable + 12 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + BG + Break generation + 7 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M_3 + Output Compare 1 mode + 16 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + CNT + counter value + 0 + 16 + read-write + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + DTG + Dead-time generator setup + 0 + 8 + + + LOCK + Lock configuration + 8 + 2 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + BKE + Break enable + 12 + 1 + + + BKP + Break polarity + 13 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + MOE + Main output enable + 15 + 1 + + + BKF + Break filter + 16 + 4 + + + BKDSRM + BKDSRM + 26 + 1 + + + BKBID + BKBID + 28 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTGF + Dead-time generator setup + 0 + 8 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + + + OR1 + OR1 + TIM option register 1 + 0x68 + 0x20 + read-write + 0x00000000 + + + HSE32EN + HSE Divided by 32 enable + 0 + 1 + + + + + DCR + DCR + DMA control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM17 + 0x40014800 + + + TIM1 + Advanced-timers + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM15 + TIM1_BRK_TIM15 + 24 + + + TIM1_UP_TIM16 + TIM1_UP_TIM16 + 25 + + + TIM1_TRG_COM + TIM1_TRG_COM/ + 26 + + + TIM1_CC + TIM1 capture compare interrupt + 27 + + + TIM8_CC + TIM8_CC + 46 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS_3 + Master mode selection - bit 3 + 25 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + OIS4N + Output Idle state 4 (OC4N output) + 15 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMSPS + SMS Preload Source + 25 + 1 + + + SMSPE + SMS Preload Enable + 24 + 1 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TERRIE + Transition Error interrupt enable + 23 + 1 + + + IERRIE + Index Error interrupt enable + 22 + 1 + + + DIRIE + Direction Change interrupt enable + 21 + 1 + + + IDXIE + Index interrupt enable + 20 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + TERRF + Transition Error interrupt flag + 23 + 1 + + + IERRF + Index Error interrupt flag + 22 + 1 + + + DIRF + Direction Change interrupt flag + 21 + 1 + + + IDXF + Index interrupt flag + 20 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + B2G + Break 2 generation + 8 + 1 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + CC4NE + Capture/Compare 4 complementary output enable + 14 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIFCPY + 31 + 1 + read-only + + + CNT + counter value + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + BK2ID + BK2ID + 29 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + BK2E + Break 2 Enable + 24 + 1 + + + BK2F + Break 2 filter + 20 + 4 + + + BKF + Break filter + 16 + 4 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x48 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x4C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x50 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTGF + Dead-time falling edge generator setup + 0 + 8 + + + + + ECR + ECR + DMA control register + 0x58 + 0x20 + read-write + 0x00000000 + + + IE + Index Enable + 0 + 1 + + + IDIR + Index Direction + 1 + 2 + + + IBLK + Index Blanking + 3 + 2 + + + FIDX + First Index + 5 + 1 + + + IPOS + Index Positioning + 6 + 2 + + + PW + Pulse width + 16 + 8 + + + PWPRSC + Pulse Width prescaler + 24 + 3 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input selection + 24 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + ETRSEL + ETR source selection + 14 + 4 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + BK2CMP4P + BRK2 COMP4 input polarity + 13 + 1 + + + BK2CMP3P + BRK2 COMP3 input polarity + 12 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP7E + BRK2 COMP7 enable + 7 + 1 + + + BK2CMP6E + BRK2 COMP6 enable + 6 + 1 + + + BK2CMP5E + BRK2 COMP5 enable + 5 + 1 + + + BK2CMP4E + BRK2 COMP4 enable + 4 + 1 + + + BK2CMP3E + BRK2 COMP3 enable + 3 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + DCR + DCR + control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM20 + 0x40015000 + + TIM20_BRK + TIM20_BRK + 77 + + + TIM20_UP + TIM20_UP + 78 + + + TIM20_TRG_COM + TIM20_TRG_COM + 79 + + + TIM20_CC + TIM20_CC + 80 + + + + TIM8 + 0x40013400 + + TIM8_BRK + TIM8_BRK + 43 + + + TIM8_UP + TIM8_UP + 44 + + + TIM8_TRG_COM + TIM8_TRG_COM + 45 + + + + TIM2 + Advanced-timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS_3 + Master mode selection - bit 3 + 25 + 1 + + + MMS2 + Master mode selection 2 + 20 + 4 + + + OIS6 + Output Idle state 6 (OC6 output) + 18 + 1 + + + OIS5 + Output Idle state 5 (OC5 output) + 16 + 1 + + + OIS4N + Output Idle state 4 (OC4N output) + 15 + 1 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA selection + 3 + 1 + + + CCUS + Capture/compare control update selection + 2 + 1 + + + CCPC + Capture/compare preloaded control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x00000000 + + + SMSPS + SMS Preload Source + 25 + 1 + + + SMSPE + SMS Preload Enable + 24 + 1 + + + TS_4_3 + Trigger selection - bit 4:3 + 20 + 2 + + + SMS_3 + Slave mode selection - bit 3 + 16 + 1 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + TERRIE + Transition Error interrupt enable + 23 + 1 + + + IERRIE + Index Error interrupt enable + 22 + 1 + + + DIRIE + Direction Change interrupt enable + 21 + 1 + + + IDXIE + Index interrupt enable + 20 + 1 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + TERRF + Transition Error interrupt flag + 23 + 1 + + + IERRF + Index Error interrupt flag + 22 + 1 + + + DIRF + Direction Change interrupt flag + 21 + 1 + + + IDXF + Index interrupt flag + 20 + 1 + + + CC6IF + Compare 6 interrupt flag + 17 + 1 + + + CC5IF + Compare 5 interrupt flag + 16 + 1 + + + SBIF + System Break interrupt flag + 13 + 1 + + + CC4OF + Capture/Compare 4 overcapture flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture flag + 9 + 1 + + + B2IF + Break 2 interrupt flag + 8 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + B2G + Break 2 generation + 8 + 1 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update generation + 5 + 1 + + + CC4G + Capture/compare 4 generation + 4 + 1 + + + CC3G + Capture/compare 3 generation + 3 + 1 + + + CC2G + Capture/compare 2 generation + 2 + 1 + + + CC1G + Capture/compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M_3 + Output Compare 2 mode - bit 3 + 24 + 1 + + + OC1M_3 + Output Compare 1 mode - bit 3 + 16 + 1 + + + OC2CE + Output Compare 2 clear enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload enable + 11 + 1 + + + OC2FE + Output Compare 2 fast enable + 10 + 1 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + OC1CE + Output Compare 1 clear enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload enable + 3 + 1 + + + OC1FE + Output Compare 1 fast enable + 2 + 1 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4M_3 + Output Compare 4 mode - bit 3 + 24 + 1 + + + OC3M_3 + Output Compare 3 mode - bit 3 + 16 + 1 + + + OC4CE + Output compare 4 clear enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload enable + 11 + 1 + + + OC4FE + Output compare 4 fast enable + 10 + 1 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + OC3CE + Output compare 3 clear enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload enable + 3 + 1 + + + OC3FE + Output compare 3 fast enable + 2 + 1 + + + CC3S + Capture/Compare 3 selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable register + 0x20 + 0x20 + read-write + 0x00000000 + + + CC6P + Capture/Compare 6 output polarity + 21 + 1 + + + CC6E + Capture/Compare 6 output enable + 20 + 1 + + + CC5P + Capture/Compare 5 output polarity + 17 + 1 + + + CC5E + Capture/Compare 5 output enable + 16 + 1 + + + CC4NP + Capture/Compare 4 complementary output polarity + 15 + 1 + + + CC4NE + Capture/Compare 4 complementary output enable + 14 + 1 + + + CC4P + Capture/Compare 3 output Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output enable + 10 + 1 + + + CC3P + Capture/Compare 3 output Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output enable + 6 + 1 + + + CC2P + Capture/Compare 2 output Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output enable + 2 + 1 + + + CC1P + Capture/Compare 1 output Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + UIFCPY + UIFCPY + 31 + 1 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0xFFFFFFFF + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x00000000 + + + REP + Repetition counter value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x00000000 + + + BK2ID + BK2ID + 29 + 1 + + + BKBID + BKBID + 28 + 1 + + + BK2DSRM + BK2DSRM + 27 + 1 + + + BKDSRM + BKDSRM + 26 + 1 + + + BK2P + Break 2 polarity + 25 + 1 + + + BK2E + Break 2 Enable + 24 + 1 + + + BK2F + Break 2 filter + 20 + 4 + + + BKF + Break filter + 16 + 4 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run mode + 11 + 1 + + + OSSI + Off-state selection for Idle mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + CCR5 + CCR5 + capture/compare register 4 + 0x48 + 0x20 + read-write + 0x00000000 + + + CCR5 + Capture/Compare value + 0 + 16 + + + GC5C1 + Group Channel 5 and Channel 1 + 29 + 1 + + + GC5C2 + Group Channel 5 and Channel 2 + 30 + 1 + + + GC5C3 + Group Channel 5 and Channel 3 + 31 + 1 + + + + + CCR6 + CCR6 + capture/compare register 4 + 0x4C + 0x20 + read-write + 0x00000000 + + + CCR6 + Capture/Compare value + 0 + 16 + + + + + CCMR3_Output + CCMR3_Output + capture/compare mode register 2 (output mode) + 0x50 + 0x20 + read-write + 0x00000000 + + + OC6M_bit3 + Output Compare 6 mode bit 3 + 24 + 1 + + + OC5M_bit3 + Output Compare 5 mode bit 3 + 16 + 3 + + + OC6CE + Output compare 6 clear enable + 15 + 1 + + + OC6M + Output compare 6 mode + 12 + 3 + + + OC6PE + Output compare 6 preload enable + 11 + 1 + + + OC6FE + Output compare 6 fast enable + 10 + 1 + + + OC5CE + Output compare 5 clear enable + 7 + 1 + + + OC5M + Output compare 5 mode + 4 + 3 + + + OC5PE + Output compare 5 preload enable + 3 + 1 + + + OC5FE + Output compare 5 fast enable + 2 + 1 + + + + + DTR2 + DTR2 + timer Deadtime Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + DTPE + Deadtime Preload Enable + 17 + 1 + + + DTAE + Deadtime Asymmetric Enable + 16 + 1 + + + DTGF + Dead-time falling edge generator setup + 0 + 8 + + + + + ECR + ECR + DMA control register + 0x58 + 0x20 + read-write + 0x00000000 + + + IE + Index Enable + 0 + 1 + + + IDIR + Index Direction + 1 + 2 + + + IBLK + Index Blanking + 3 + 2 + + + FIDX + First Index + 5 + 1 + + + IPOS + Index Positioning + 6 + 2 + + + PW + Pulse width + 16 + 8 + + + PWPRSC + Pulse Width prescaler + 24 + 3 + + + + + TISEL + TISEL + TIM timer input selection register + 0x5C + 0x20 + read-write + 0x00000000 + + + TI1SEL + TI1[0] to TI1[15] input selection + 0 + 4 + + + TI2SEL + TI2[0] to TI2[15] input selection + 8 + 4 + + + TI3SEL + TI3[0] to TI3[15] input selection + 16 + 4 + + + TI4SEL + TI4[0] to TI4[15] input selection + 24 + 4 + + + + + AF1 + AF1 + TIM alternate function option register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + ETRSEL + ETR source selection + 14 + 4 + + + BKCMP4P + BRK COMP4 input polarity + 13 + 1 + + + BKCMP3P + BRK COMP3 input polarity + 12 + 1 + + + BKCMP2P + BRK COMP2 input polarity + 11 + 1 + + + BKCMP1P + BRK COMP1 input polarity + 10 + 1 + + + BKINP + BRK BKIN input polarity + 9 + 1 + + + BKCMP7E + BRK COMP7 enable + 7 + 1 + + + BKCMP6E + BRK COMP6 enable + 6 + 1 + + + BKCMP5E + BRK COMP5 enable + 5 + 1 + + + BKCMP4E + BRK COMP4 enable + 4 + 1 + + + BKCMP3E + BRK COMP3 enable + 3 + 1 + + + BKCMP2E + BRK COMP2 enable + 2 + 1 + + + BKCMP1E + BRK COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + AF2 + AF2 + TIM alternate function option register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OCRSEL + OCREF_CLR source selection + 16 + 3 + + + BK2CMP4P + BRK2 COMP4 input polarity + 13 + 1 + + + BK2CMP3P + BRK2 COMP3 input polarity + 12 + 1 + + + BK2CMP2P + BRK2 COMP2 input polarity + 11 + 1 + + + BK2CMP1P + BRK2 COMP1 input polarity + 10 + 1 + + + BK2INP + BRK2 BKIN input polarity + 9 + 1 + + + BK2CMP7E + BRK2 COMP7 enable + 7 + 1 + + + BK2CMP6E + BRK2 COMP6 enable + 6 + 1 + + + BK2CMP5E + BRK2 COMP5 enable + 5 + 1 + + + BK2CMP4E + BRK2 COMP4 enable + 4 + 1 + + + BK2CMP3E + BRK2 COMP3 enable + 3 + 1 + + + BK2CMP2E + BRK2 COMP2 enable + 2 + 1 + + + BK2CMP1E + BRK2 COMP1 enable + 1 + 1 + + + BKINE + BRK BKIN input enable + 0 + 1 + + + + + DCR + DCR + control register + 0x3DC + 0x20 + read-write + 0x00000000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x3E0 + 0x20 + read-write + 0x00000000 + + + DMAB + DMA register for burst accesses + 0 + 32 + + + + + + + TIM3 + 0x40000400 + + TIM3 + TIM3 + 29 + + + + TIM4 + 0x40000800 + + TIM4 + TIM4 + 30 + + + + TIM5 + 0x40000C00 + + TIM5 + TIM5 + 50 + + + + TIM6 + Basic-timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DACUNDER + TIM6_DACUNDER + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + DITHEN + Dithering Enable + 12 + 1 + + + UIFREMAP + UIF status bit remapping + 11 + 1 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x00000000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x00000000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x00000000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + 0x00000000 + + + UIFCPY + UIF Copy + 31 + 1 + read-only + + + CNT + Low counter value + 0 + 16 + read-write + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x00000000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 + 55 + + + + LPTIMER1 + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + DOWN + Counter direction change up to down + 6 + 1 + + + UP + Counter direction change down to up + 5 + 1 + + + ARROK + Autoreload register update OK + 4 + 1 + + + CMPOK + Compare register update OK + 3 + 1 + + + EXTTRIG + External trigger edge event + 2 + 1 + + + ARRM + Autoreload match + 1 + 1 + + + CMPM + Compare match + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + DOWNCF + Direction change to down Clear Flag + 6 + 1 + + + UPCF + Direction change to UP Clear Flag + 5 + 1 + + + ARROKCF + Autoreload register update OK Clear Flag + 4 + 1 + + + CMPOKCF + Compare register update OK Clear Flag + 3 + 1 + + + EXTTRIGCF + External trigger valid edge Clear Flag + 2 + 1 + + + ARRMCF + Autoreload match Clear Flag + 1 + 1 + + + CMPMCF + compare match Clear Flag + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + DOWNIE + Direction change to down Interrupt Enable + 6 + 1 + + + UPIE + Direction change to UP Interrupt Enable + 5 + 1 + + + ARROKIE + Autoreload register update OK Interrupt Enable + 4 + 1 + + + CMPOKIE + Compare register update OK Interrupt Enable + 3 + 1 + + + EXTTRIGIE + External trigger valid edge Interrupt Enable + 2 + 1 + + + ARRMIE + Autoreload match Interrupt Enable + 1 + 1 + + + CMPMIE + Compare match Interrupt Enable + 0 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + ENC + Encoder mode enable + 24 + 1 + + + COUNTMODE + counter mode enabled + 23 + 1 + + + PRELOAD + Registers update mode + 22 + 1 + + + WAVPOL + Waveform shape polarity + 21 + 1 + + + WAVE + Waveform shape + 20 + 1 + + + TIMOUT + Timeout enable + 19 + 1 + + + TRIGEN + Trigger enable and polarity + 17 + 2 + + + TRIGSEL + Trigger selector + 13 + 4 + + + PRESC + Clock prescaler + 9 + 3 + + + TRGFLT + Configurable digital filter for trigger + 6 + 2 + + + CKFLT + Configurable digital filter for external clock + 3 + 2 + + + CKPOL + Clock Polarity + 1 + 2 + + + CKSEL + Clock selector + 0 + 1 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + RSTARE + 4 + 1 + + + COUNTRST + COUNTRST + 3 + 1 + + + CNTSTRT + Timer start in continuous mode + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + CMP + CMP + Compare Register + 0x14 + 0x20 + read-write + 0x00000000 + + + CMP + Compare value + 0 + 16 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + OR + OR + option register + 0x20 + 0x20 + read-write + 0x00000000 + + + IN1 + IN1 + 0 + 1 + + + IN2 + IN2 + 1 + 1 + + + IN1_2_1 + IN1_2_1 + 2 + 2 + + + IN2_2_1 + IN2_2_1 + 4 + 2 + + + + + + + USART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 + 37 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + M1 + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TCBGTIE + TCBGTIE + 24 + 1 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00000000 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + TCBGT + TCBGT + 25 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + UDR + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 + 38 + + + + USART3 + 0x40004800 + + USART3 + USART3 + 39 + + + + UART4 + Universal synchronous asynchronous receiver transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 + 52 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + M1 + 28 + 1 + + + EOBIE + End of Block interrupt enable + 27 + 1 + + + RTOIE + Receiver timeout interrupt enable + 26 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + OVER8 + Oversampling mode + 15 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + RTOEN + Receiver timeout enable + 23 + 1 + + + ABRMOD1 + Auto baud rate mode + 22 + 1 + + + ABRMOD0 + ABRMOD0 + 21 + 1 + + + ABREN + Auto baud rate enable + 20 + 1 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + LBDIE + LIN break detection interrupt enable + 6 + 1 + + + LBDL + LIN break detection length + 5 + 1 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + DIS_NSS + DIS_NSS + 3 + 1 + + + SLVEN + SLVEN + 0 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x00000000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TCBGTIE + TCBGTIE + 24 + 1 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + SCARCNT + Smartcard auto-retry count + 17 + 3 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + ONEBIT + One sample bit method enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + SCEN + Smartcard mode enable + 5 + 1 + + + NACK + Smartcard NACK enable + 4 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + Ir low-power + 2 + 1 + + + IREN + Ir mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x00000000 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + + + GTPR + GTPR + Guard time and prescaler register + 0x10 + 0x20 + read-write + 0x00000000 + + + GT + Guard time value + 8 + 8 + + + PSC + Prescaler value + 0 + 8 + + + + + RTOR + RTOR + Receiver timeout register + 0x14 + 0x20 + read-write + 0x00000000 + + + BLEN + Block Length + 24 + 8 + + + RTO + Receiver timeout value + 0 + 24 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x00000000 + + + TXFRQ + Transmit data flush request + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + ABRRQ + Auto baud rate request + 0 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x000000C0 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + TCBGT + TCBGT + 25 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + ABRF + ABRF + 15 + 1 + + + ABRE + ABRE + 14 + 1 + + + UDR + UDR + 13 + 1 + + + EOBF + EOBF + 12 + 1 + + + RTOF + RTOF + 11 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + LBDF + LBDF + 8 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + UDRCF + UDRCF + 13 + 1 + + + EOBCF + End of block clear flag + 12 + 1 + + + RTOCF + Receiver timeout clear flag + 11 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + LBDCF + LIN break detection clear flag + 8 + 1 + + + TCBGTCF + TCBGTCF + 7 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + TXFECF + TXFECF + 5 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x00000000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x00000000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + USART prescaler register + 0x2C + 0x20 + read-write + 0x00000000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + UART5 + 0x40005000 + + UART5 + UART5 + 53 + + + + LPUART1 + Universal synchronous asynchronous receiver transmitter + USART + 0x40008000 + + 0x0 + 0x400 + registers + + + LPTIM1 + LPTIM1 + 49 + + + LPUART + LPUART + 91 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + RXFFIE + RXFFIE + 31 + 1 + + + TXFEIE + TXFEIE + 30 + 1 + + + FIFOEN + FIFOEN + 29 + 1 + + + M1 + Word length + 28 + 1 + + + DEAT4 + Driver Enable assertion time + 25 + 1 + + + DEAT3 + DEAT3 + 24 + 1 + + + DEAT2 + DEAT2 + 23 + 1 + + + DEAT1 + DEAT1 + 22 + 1 + + + DEAT0 + DEAT0 + 21 + 1 + + + DEDT4 + Driver Enable de-assertion time + 20 + 1 + + + DEDT3 + DEDT3 + 19 + 1 + + + DEDT2 + DEDT2 + 18 + 1 + + + DEDT1 + DEDT1 + 17 + 1 + + + DEDT0 + DEDT0 + 16 + 1 + + + CMIE + Character match interrupt enable + 14 + 1 + + + MME + Mute mode enable + 13 + 1 + + + M0 + Word length + 12 + 1 + + + WAKE + Receiver wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + UESM + USART enable in Stop mode + 1 + 1 + + + UE + USART enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ADD4_7 + Address of the USART node + 28 + 4 + + + ADD0_3 + Address of the USART node + 24 + 4 + + + MSBFIRST + Most significant bit first + 19 + 1 + + + TAINV + Binary data inversion + 18 + 1 + + + TXINV + TX pin active level inversion + 17 + 1 + + + RXINV + RX pin active level inversion + 16 + 1 + + + SWAP + Swap TX/RX pins + 15 + 1 + + + STOP + STOP bits + 12 + 2 + + + ADDM7 + 7-bit Address Detection/4-bit Address Detection + 4 + 1 + + + + + CR3 + CR3 + Control register 3 + 0x8 + 0x20 + read-write + 0x0000 + + + TXFTCFG + TXFTCFG + 29 + 3 + + + RXFTIE + RXFTIE + 28 + 1 + + + RXFTCFG + RXFTCFG + 25 + 3 + + + TXFTIE + TXFTIE + 23 + 1 + + + WUFIE + Wakeup from Stop mode interrupt enable + 22 + 1 + + + WUS + Wakeup from Stop mode interrupt flag selection + 20 + 2 + + + DEP + Driver enable polarity selection + 15 + 1 + + + DEM + Driver enable mode + 14 + 1 + + + DDRE + DMA Disable on Reception Error + 13 + 1 + + + OVRDIS + Overrun Disable + 12 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + BRR + BRR + Baud rate register + 0xC + 0x20 + read-write + 0x0000 + + + BRR + BRR + 0 + 20 + + + + + RQR + RQR + Request register + 0x18 + 0x20 + write-only + 0x0000 + + + TXFRQ + TXFRQ + 4 + 1 + + + RXFRQ + Receive data flush request + 3 + 1 + + + MMRQ + Mute mode request + 2 + 1 + + + SBKRQ + Send break request + 1 + 1 + + + + + ISR + ISR + Interrupt & status register + 0x1C + 0x20 + read-only + 0x00C0 + + + TXFT + TXFT + 27 + 1 + + + RXFT + RXFT + 26 + 1 + + + RXFF + RXFF + 24 + 1 + + + TXFE + TXFE + 23 + 1 + + + REACK + REACK + 22 + 1 + + + TEACK + TEACK + 21 + 1 + + + WUF + WUF + 20 + 1 + + + RWU + RWU + 19 + 1 + + + SBKF + SBKF + 18 + 1 + + + CMF + CMF + 17 + 1 + + + BUSY + BUSY + 16 + 1 + + + CTS + CTS + 10 + 1 + + + CTSIF + CTSIF + 9 + 1 + + + TXE + TXE + 7 + 1 + + + TC + TC + 6 + 1 + + + RXNE + RXNE + 5 + 1 + + + IDLE + IDLE + 4 + 1 + + + ORE + ORE + 3 + 1 + + + NF + NF + 2 + 1 + + + FE + FE + 1 + 1 + + + PE + PE + 0 + 1 + + + + + ICR + ICR + Interrupt flag clear register + 0x20 + 0x20 + write-only + 0x0000 + + + WUCF + Wakeup from Stop mode clear flag + 20 + 1 + + + CMCF + Character match clear flag + 17 + 1 + + + CTSCF + CTS clear flag + 9 + 1 + + + TCCF + Transmission complete clear flag + 6 + 1 + + + IDLECF + Idle line detected clear flag + 4 + 1 + + + ORECF + Overrun error clear flag + 3 + 1 + + + NCF + Noise detected clear flag + 2 + 1 + + + FECF + Framing error clear flag + 1 + 1 + + + PECF + Parity error clear flag + 0 + 1 + + + + + RDR + RDR + Receive data register + 0x24 + 0x20 + read-only + 0x0000 + + + RDR + Receive data value + 0 + 9 + + + + + TDR + TDR + Transmit data register + 0x28 + 0x20 + read-write + 0x0000 + + + TDR + Transmit data value + 0 + 9 + + + + + PRESC + PRESC + Prescaler register + 0x2C + 0x20 + read-write + 0x0000 + + + PRESCALER + PRESCALER + 0 + 4 + + + + + + + SPI1 + Serial peripheral interface/Inter-IC sound + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000700 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + NSSP + NSS pulse management + 3 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + + DS + Data size + 8 + 4 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + LDMA_RX + Last DMA transfer for reception + 13 + 1 + + + LDMA_TX + Last DMA transfer for transmission + 14 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x00000000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x00000000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x00000000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + CHLEN + 0 + 1 + + + DATLEN + DATLEN + 1 + 2 + + + CKPOL + CKPOL + 3 + 1 + + + I2SSTD + I2SSTD + 4 + 2 + + + PCMSYNC + PCMSYNC + 7 + 1 + + + I2SCFG + I2SCFG + 8 + 2 + + + I2SE + I2SE + 10 + 1 + + + I2SMOD + I2SMOD + 11 + 1 + + + + + I2SPR + I2SPR + prescaler register + 0x20 + 0x20 + read-write + 0x00000002 + + + I2SDIV + I2SDIV + 0 + 8 + + + ODD + ODD + 8 + 1 + + + MCKOE + MCKOE + 9 + 1 + + + + + + + SPI4 + Serial peripheral interface/Inter-IC sound + SPI + 0x40013C00 + + 0x0 + 0x400 + registers + + + SPI4 + SPI4 + 84 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x00000700 + + + BIDIMODE + Bidirectional data mode enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional mode + 14 + 1 + + + CRCEN + Hardware CRC calculation enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + SSOE + SS output enable + 2 + 1 + + + NSSP + NSS pulse management + 3 + 1 + + + FRF + Frame format + 4 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + RXNEIE + RX buffer not empty interrupt enable + 6 + 1 + + + TXEIE + Tx buffer empty interrupt enable + 7 + 1 + + + DS + Data size + 8 + 4 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + LDMA_RX + Last DMA transfer for reception + 13 + 1 + + + LDMA_TX + Last DMA transfer for transmission + 14 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x00000002 + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + MODF + Mode fault + 5 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x00000000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x00000007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x00000000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x00000000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + CHLEN + CHLEN + 0 + 1 + + + DATLEN + DATLEN + 1 + 2 + + + CKPOL + CKPOL + 3 + 1 + + + I2SSTD + I2SSTD + 4 + 2 + + + PCMSYNC + PCMSYNC + 7 + 1 + + + I2SCFG + I2SCFG + 8 + 2 + + + I2SE + I2SE + 10 + 1 + + + I2SMOD + I2SMOD + 11 + 1 + + + + + I2SPR + I2SPR + prescaler register + 0x20 + 0x20 + read-write + 0x00000002 + + + I2SDIV + I2SDIV + 0 + 8 + + + ODD + ODD + 8 + 1 + + + MCKOE + MCKOE + 9 + 1 + + + + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 + 51 + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 + 36 + + + + EXTI + External interrupt/event controller + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + PVD_PVM + PVD through EXTI line detection + 1 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + USB_HP + USB_HP + 19 + + + USB_LP + USB_LP + 20 + + + EXTI9_5 + EXTI9_5 + 23 + + + EXTI15_10 + EXTI15_10 + 40 + + + USBWakeUP + USBWakeUP + 42 + + + CRS + CRS + 75 + + + + IMR1 + IMR1 + Interrupt mask register + 0x0 + 0x20 + read-write + 0xFF820000 + + + IM0 + Interrupt Mask on line 0 + 0 + 1 + + + IM1 + Interrupt Mask on line 1 + 1 + 1 + + + IM2 + Interrupt Mask on line 2 + 2 + 1 + + + IM3 + Interrupt Mask on line 3 + 3 + 1 + + + IM4 + Interrupt Mask on line 4 + 4 + 1 + + + IM5 + Interrupt Mask on line 5 + 5 + 1 + + + IM6 + Interrupt Mask on line 6 + 6 + 1 + + + IM7 + Interrupt Mask on line 7 + 7 + 1 + + + IM8 + Interrupt Mask on line 8 + 8 + 1 + + + IM9 + Interrupt Mask on line 9 + 9 + 1 + + + IM10 + Interrupt Mask on line 10 + 10 + 1 + + + IM11 + Interrupt Mask on line 11 + 11 + 1 + + + IM12 + Interrupt Mask on line 12 + 12 + 1 + + + IM13 + Interrupt Mask on line 13 + 13 + 1 + + + IM14 + Interrupt Mask on line 14 + 14 + 1 + + + IM15 + Interrupt Mask on line 15 + 15 + 1 + + + IM16 + Interrupt Mask on line 16 + 16 + 1 + + + IM17 + Interrupt Mask on line 17 + 17 + 1 + + + IM18 + Interrupt Mask on line 18 + 18 + 1 + + + IM19 + Interrupt Mask on line 19 + 19 + 1 + + + IM20 + Interrupt Mask on line 20 + 20 + 1 + + + IM21 + Interrupt Mask on line 21 + 21 + 1 + + + IM22 + Interrupt Mask on line 22 + 22 + 1 + + + IM23 + Interrupt Mask on line 23 + 23 + 1 + + + IM24 + Interrupt Mask on line 24 + 24 + 1 + + + IM25 + Interrupt Mask on line 25 + 25 + 1 + + + IM26 + Interrupt Mask on line 26 + 26 + 1 + + + IM27 + Interrupt Mask on line 27 + 27 + 1 + + + IM28 + Interrupt Mask on line 28 + 28 + 1 + + + IM29 + Interrupt Mask on line 29 + 29 + 1 + + + IM30 + Interrupt Mask on line 30 + 30 + 1 + + + IM31 + Interrupt Mask on line 31 + 31 + 1 + + + + + EMR1 + EMR1 + Event mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + EM0 + Event Mask on line 0 + 0 + 1 + + + EM1 + Event Mask on line 1 + 1 + 1 + + + EM2 + Event Mask on line 2 + 2 + 1 + + + EM3 + Event Mask on line 3 + 3 + 1 + + + EM4 + Event Mask on line 4 + 4 + 1 + + + EM5 + Event Mask on line 5 + 5 + 1 + + + EM6 + Event Mask on line 6 + 6 + 1 + + + EM7 + Event Mask on line 7 + 7 + 1 + + + EM8 + Event Mask on line 8 + 8 + 1 + + + EM9 + Event Mask on line 9 + 9 + 1 + + + EM10 + Event Mask on line 10 + 10 + 1 + + + EM11 + Event Mask on line 11 + 11 + 1 + + + EM12 + Event Mask on line 12 + 12 + 1 + + + EM13 + Event Mask on line 13 + 13 + 1 + + + EM14 + Event Mask on line 14 + 14 + 1 + + + EM15 + Event Mask on line 15 + 15 + 1 + + + EM16 + Event Mask on line 16 + 16 + 1 + + + EM17 + Event Mask on line 17 + 17 + 1 + + + EM18 + Event Mask on line 18 + 18 + 1 + + + EM19 + Event Mask on line 19 + 19 + 1 + + + EM20 + Event Mask on line 20 + 20 + 1 + + + EM21 + Event Mask on line 21 + 21 + 1 + + + EM22 + Event Mask on line 22 + 22 + 1 + + + EM23 + Event Mask on line 23 + 23 + 1 + + + EM24 + Event Mask on line 24 + 24 + 1 + + + EM25 + Event Mask on line 25 + 25 + 1 + + + EM26 + Event Mask on line 26 + 26 + 1 + + + EM27 + Event Mask on line 27 + 27 + 1 + + + EM28 + Event Mask on line 28 + 28 + 1 + + + EM29 + Event Mask on line 29 + 29 + 1 + + + EM30 + Event Mask on line 30 + 30 + 1 + + + EM31 + Event Mask on line 31 + 31 + 1 + + + + + RTSR1 + RTSR1 + Rising Trigger selection register + 0x8 + 0x20 + read-write + 0x00000000 + + + RT0 + Rising trigger event configuration of line 0 + 0 + 1 + + + RT1 + Rising trigger event configuration of line 1 + 1 + 1 + + + RT2 + Rising trigger event configuration of line 2 + 2 + 1 + + + RT3 + Rising trigger event configuration of line 3 + 3 + 1 + + + RT4 + Rising trigger event configuration of line 4 + 4 + 1 + + + RT5 + Rising trigger event configuration of line 5 + 5 + 1 + + + RT6 + Rising trigger event configuration of line 6 + 6 + 1 + + + RT7 + Rising trigger event configuration of line 7 + 7 + 1 + + + RT8 + Rising trigger event configuration of line 8 + 8 + 1 + + + RT9 + Rising trigger event configuration of line 9 + 9 + 1 + + + RT10 + Rising trigger event configuration of line 10 + 10 + 1 + + + RT11 + Rising trigger event configuration of line 11 + 11 + 1 + + + RT12 + Rising trigger event configuration of line 12 + 12 + 1 + + + RT13 + Rising trigger event configuration of line 13 + 13 + 1 + + + RT14 + Rising trigger event configuration of line 14 + 14 + 1 + + + RT15 + Rising trigger event configuration of line 15 + 15 + 1 + + + RT16 + Rising trigger event configuration of line 16 + 16 + 1 + + + RT18 + Rising trigger event configuration of line 18 + 18 + 1 + + + RT19 + Rising trigger event configuration of line 19 + 19 + 1 + + + RT20 + Rising trigger event configuration of line 20 + 20 + 1 + + + RT21 + Rising trigger event configuration of line 21 + 21 + 1 + + + RT22 + Rising trigger event configuration of line 22 + 22 + 1 + + + RT + RT + 29 + 3 + + + + + FTSR1 + FTSR1 + Falling Trigger selection register + 0xC + 0x20 + read-write + 0x00000000 + + + FT0 + Falling trigger event configuration of line 0 + 0 + 1 + + + FT1 + Falling trigger event configuration of line 1 + 1 + 1 + + + FT2 + Falling trigger event configuration of line 2 + 2 + 1 + + + FT3 + Falling trigger event configuration of line 3 + 3 + 1 + + + FT4 + Falling trigger event configuration of line 4 + 4 + 1 + + + FT5 + Falling trigger event configuration of line 5 + 5 + 1 + + + FT6 + Falling trigger event configuration of line 6 + 6 + 1 + + + FT7 + Falling trigger event configuration of line 7 + 7 + 1 + + + FT8 + Falling trigger event configuration of line 8 + 8 + 1 + + + FT9 + Falling trigger event configuration of line 9 + 9 + 1 + + + FT10 + Falling trigger event configuration of line 10 + 10 + 1 + + + FT11 + Falling trigger event configuration of line 11 + 11 + 1 + + + FT12 + Falling trigger event configuration of line 12 + 12 + 1 + + + FT13 + Falling trigger event configuration of line 13 + 13 + 1 + + + FT14 + Falling trigger event configuration of line 14 + 14 + 1 + + + FT15 + Falling trigger event configuration of line 15 + 15 + 1 + + + FT16 + Falling trigger event configuration of line 16 + 16 + 1 + + + FT18 + Falling trigger event configuration of line 18 + 18 + 1 + + + FT19 + Falling trigger event configuration of line 19 + 19 + 1 + + + FT20 + Falling trigger event configuration of line 20 + 20 + 1 + + + FT21 + Falling trigger event configuration of line 21 + 21 + 1 + + + FT22 + Falling trigger event configuration of line 22 + 22 + 1 + + + + + SWIER1 + SWIER1 + Software interrupt event register + 0x10 + 0x20 + read-write + 0x00000000 + + + SWI0 + Software Interrupt on line 0 + 0 + 1 + + + SWI1 + Software Interrupt on line 1 + 1 + 1 + + + SWI2 + Software Interrupt on line 2 + 2 + 1 + + + SWI3 + Software Interrupt on line 3 + 3 + 1 + + + SWI4 + Software Interrupt on line 4 + 4 + 1 + + + SWI5 + Software Interrupt on line 5 + 5 + 1 + + + SWI6 + Software Interrupt on line 6 + 6 + 1 + + + SWI7 + Software Interrupt on line 7 + 7 + 1 + + + SWI8 + Software Interrupt on line 8 + 8 + 1 + + + SWI9 + Software Interrupt on line 9 + 9 + 1 + + + SWI10 + Software Interrupt on line 10 + 10 + 1 + + + SWI11 + Software Interrupt on line 11 + 11 + 1 + + + SWI12 + Software Interrupt on line 12 + 12 + 1 + + + SWI13 + Software Interrupt on line 13 + 13 + 1 + + + SWI14 + Software Interrupt on line 14 + 14 + 1 + + + SWI15 + Software Interrupt on line 15 + 15 + 1 + + + SWI16 + Software Interrupt on line 16 + 16 + 1 + + + SWI18 + Software Interrupt on line 18 + 18 + 1 + + + SWI19 + Software Interrupt on line 19 + 19 + 1 + + + SWI20 + Software Interrupt on line 20 + 20 + 1 + + + SWI21 + Software Interrupt on line 21 + 21 + 1 + + + SWI22 + Software Interrupt on line 22 + 22 + 1 + + + + + PR1 + PR1 + Pending register + 0x14 + 0x20 + read-write + 0x00000000 + + + PIF0 + Pending bit 0 + 0 + 1 + + + PIF1 + Pending bit 1 + 1 + 1 + + + PIF2 + Pending bit 2 + 2 + 1 + + + PIF3 + Pending bit 3 + 3 + 1 + + + PIF4 + Pending bit 4 + 4 + 1 + + + PIF5 + Pending bit 5 + 5 + 1 + + + PIF6 + Pending bit 6 + 6 + 1 + + + PIF7 + Pending bit 7 + 7 + 1 + + + PIF8 + Pending bit 8 + 8 + 1 + + + PIF9 + Pending bit 9 + 9 + 1 + + + PIF10 + Pending bit 10 + 10 + 1 + + + PIF11 + Pending bit 11 + 11 + 1 + + + PIF12 + Pending bit 12 + 12 + 1 + + + PIF13 + Pending bit 13 + 13 + 1 + + + PIF14 + Pending bit 14 + 14 + 1 + + + PIF15 + Pending bit 15 + 15 + 1 + + + PIF16 + Pending bit 16 + 16 + 1 + + + PIF18 + Pending bit 18 + 18 + 1 + + + PIF19 + Pending bit 19 + 19 + 1 + + + PIF20 + Pending bit 20 + 20 + 1 + + + PIF21 + Pending bit 21 + 21 + 1 + + + PIF22 + Pending bit 22 + 22 + 1 + + + + + IMR2 + IMR2 + Interrupt mask register + 0x20 + 0x20 + read-write + 0xFFFFFF87 + + + IM32 + Interrupt Mask on external/internal line 32 + 0 + 1 + + + IM33 + Interrupt Mask on external/internal line 33 + 1 + 1 + + + IM34 + Interrupt Mask on external/internal line 34 + 2 + 1 + + + IM35 + Interrupt Mask on external/internal line 35 + 3 + 1 + + + IM36 + Interrupt Mask on external/internal line 36 + 4 + 1 + + + IM37 + Interrupt Mask on external/internal line 37 + 5 + 1 + + + IM38 + Interrupt Mask on external/internal line 38 + 6 + 1 + + + IM39 + Interrupt Mask on external/internal line 39 + 7 + 1 + + + IM40 + Interrupt Mask on external/internal line 40 + 8 + 1 + + + IM41 + Interrupt Mask on external/internal line 41 + 9 + 1 + + + IM42 + Interrupt Mask on external/internal line 42 + 10 + 1 + + + IM43 + Interrupt Mask on external/internal line 43 + 11 + 1 + + + + + EMR2 + EMR2 + Event mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + EM32 + Event mask on external/internal line 32 + 0 + 1 + + + EM33 + Event mask on external/internal line 33 + 1 + 1 + + + EM34 + Event mask on external/internal line 34 + 2 + 1 + + + EM35 + Event mask on external/internal line 35 + 3 + 1 + + + EM36 + Event mask on external/internal line 36 + 4 + 1 + + + EM37 + Event mask on external/internal line 37 + 5 + 1 + + + EM38 + Event mask on external/internal line 38 + 6 + 1 + + + EM39 + Event mask on external/internal line 39 + 7 + 1 + + + EM40 + Event mask on external/internal line 40 + 8 + 1 + + + + + RTSR2 + RTSR2 + Rising Trigger selection register + 0x28 + 0x20 + read-write + 0x00000000 + + + RT32 + Rising trigger event configuration bit of line 32 + 0 + 1 + + + RT33 + Rising trigger event configuration bit of line 32 + 1 + 1 + + + RT38 + Rising trigger event configuration bit of line 38 + 6 + 1 + + + RT39 + Rising trigger event configuration bit of line 39 + 7 + 1 + + + RT40 + Rising trigger event configuration bit of line 40 + 8 + 1 + + + RT41 + Rising trigger event configuration bit of line 41 + 9 + 1 + + + + + FTSR2 + FTSR2 + Falling Trigger selection register + 0x2C + 0x20 + read-write + 0x00000000 + + + FT35 + Falling trigger event configuration bit of line 35 + 3 + 1 + + + FT36 + Falling trigger event configuration bit of line 36 + 4 + 1 + + + FT37 + Falling trigger event configuration bit of line 37 + 5 + 1 + + + FT38 + Falling trigger event configuration bit of line 38 + 6 + 1 + + + + + SWIER2 + SWIER2 + Software interrupt event register + 0x30 + 0x20 + read-write + 0x00000000 + + + SWI35 + Software interrupt on line 35 + 3 + 1 + + + SWI36 + Software interrupt on line 36 + 4 + 1 + + + SWI37 + Software interrupt on line 37 + 5 + 1 + + + SWI38 + Software interrupt on line 38 + 6 + 1 + + + + + PR2 + PR2 + Pending register + 0x34 + 0x20 + read-write + 0x00000000 + + + PIF35 + Pending interrupt flag on line 35 + 3 + 1 + + + PIF36 + Pending interrupt flag on line 36 + 4 + 1 + + + PIF37 + Pending interrupt flag on line 37 + 5 + 1 + + + PIF38 + Pending interrupt flag on line 38 + 6 + 1 + + + + + + + RTC + Real-time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC_TAMP_CSS_LSE + RTC_TAMP_CSS_LSE + 2 + + + RTC_WKUP + RTC Wakeup timer + 3 + + + RTC_ALARM + RTC_ALARM + 41 + + + + TR + TR + time register + 0x0 + 0x20 + read-write + 0x00000000 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + DR + DR + date register + 0x4 + 0x20 + read-write + 0x00002101 + + + YT + Year tens in BCD format + 20 + 4 + + + YU + Year units in BCD format + 16 + 4 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + SSR + SSR + sub second register + 0x8 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ICSR + ICSR + initialization and status register + 0xC + 0x20 + 0x00000007 + + + ALRAWF + Alarm A write flag + 0 + 1 + read-only + + + ALRBWF + Alarm B write flag + 1 + 1 + read-only + + + WUTWF + Wakeup timer write flag + 2 + 1 + read-only + + + SHPF + Shift operation pending + 3 + 1 + read-write + + + INITS + Initialization status flag + 4 + 1 + read-only + + + RSF + Registers synchronization flag + 5 + 1 + read-write + + + INITF + Initialization flag + 6 + 1 + read-only + + + INIT + Initialization mode + 7 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value bits + 0 + 16 + + + + + CR + CR + control register + 0x18 + 0x20 + read-write + 0x00000000 + + + WCKSEL + Wakeup clock selection + 0 + 3 + + + TSEDGE + Time-stamp event active edge + 3 + 1 + + + REFCKON + Reference clock detection enable (50 or 60 Hz) + 4 + 1 + + + BYPSHAD + Bypass the shadow registers + 5 + 1 + + + FMT + Hour format + 6 + 1 + + + ALRAE + Alarm A enable + 8 + 1 + + + ALRBE + Alarm B enable + 9 + 1 + + + WUTE + Wakeup timer enable + 10 + 1 + + + TSE + Time stamp enable + 11 + 1 + + + ALRAIE + Alarm A interrupt enable + 12 + 1 + + + ALRBIE + Alarm B interrupt enable + 13 + 1 + + + WUTIE + Wakeup timer interrupt enable + 14 + 1 + + + TSIE + Time-stamp interrupt enable + 15 + 1 + + + ADD1H + Add 1 hour (summer time change) + 16 + 1 + + + SUB1H + Subtract 1 hour (winter time change) + 17 + 1 + + + BKP + Backup + 18 + 1 + + + COSEL + Calibration output selection + 19 + 1 + + + POL + Output polarity + 20 + 1 + + + OSEL + Output selection + 21 + 2 + + + COE + Calibration output enable + 23 + 1 + + + ITSE + timestamp on internal event enable + 24 + 1 + + + TAMPTS + TAMPTS + 25 + 1 + + + TAMPOE + TAMPOE + 26 + 1 + + + TAMPALRM_PU + TAMPALRM_PU + 29 + 1 + + + TAMPALRM_TYPE + TAMPALRM_TYPE + 30 + 1 + + + OUT2EN + OUT2EN + 31 + 1 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + CALR + CALR + calibration register + 0x28 + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + SU + Second units in BCD format + 0 + 4 + + + ST + Second tens in BCD format + 4 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MNT + Minute tens in BCD format + 12 + 3 + + + HU + Hour units in BCD format + 16 + 4 + + + HT + Hour tens in BCD format + 20 + 2 + + + PM + AM/PM notation + 22 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + ALRMAR + ALRMAR + alarm A register + 0x40 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBR + ALRMBR + alarm B register + 0x48 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x4C + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + SR + SR + status register + 0x50 + 0x20 + read-only + 0x00000000 + + + ALRAF + ALRAF + 0 + 1 + + + ALRBF + ALRBF + 1 + 1 + + + WUTF + WUTF + 2 + 1 + + + TSF + TSF + 3 + 1 + + + TSOVF + TSOVF + 4 + 1 + + + ITSF + ITSF + 5 + 1 + + + + + MISR + MISR + status register + 0x54 + 0x20 + read-only + 0x00000000 + + + ALRAMF + ALRAMF + 0 + 1 + + + ALRBMF + ALRBMF + 1 + 1 + + + WUTMF + WUTMF + 2 + 1 + + + TSMF + TSMF + 3 + 1 + + + TSOVMF + TSOVMF + 4 + 1 + + + ITSMF + ITSMF + 5 + 1 + + + + + SCR + SCR + status register + 0x5C + 0x20 + write-only + 0x00000000 + + + CALRAF + CALRAF + 0 + 1 + + + CALRBF + CALRBF + 1 + 1 + + + CWUTF + CWUTF + 2 + 1 + + + CTSF + CTSF + 3 + 1 + + + CTSOVF + CTSOVF + 4 + 1 + + + CITSF + CITSF + 5 + 1 + + + + + + + FMC + Flexible memory controller + FMC + 0xA0000000 + + 0x0 + 0x400 + registers + + + FMC + FMC + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + MBKEN + MBKEN + 0 + 1 + + + MUXEN + MUXEN + 1 + 1 + + + MTYP + MTYP + 2 + 2 + + + MWID + MWID + 4 + 2 + + + FACCEN + FACCEN + 6 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WREN + WREN + 12 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + CPSIZE + CPSIZE + 16 + 3 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + CCLKEN + CCLKEN + 20 + 1 + + + WFDIS + WFDIS + 21 + 1 + + + NBLSET + NBLSET + 22 + 2 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCSCNTR + PCSCNTR + PSRAM chip select counter register + 0x20 + 0x20 + read-write + 0x00000000 + + + CSCOUNT + CSCOUNT + 0 + 16 + + + CNTB1EN + CNTB1EN + 16 + 1 + + + CNTB2EN + CNTB2EN + 17 + 1 + + + CNTB3EN + CNTB3EN + 18 + 1 + + + CNTB4EN + CNTB4EN + 19 + 1 + + + + + PCR + PCR + PC Card/NAND Flash control register 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR + SR + FIFO status and interrupt register 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM + PMEM + Common memory space timing register 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT + PATT + Attribute memory space timing register 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR + ECCR + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + DATAHLD + DATAHLD + 30 + 2 + + + ACCMOD + ACCMOD + 28 + 2 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + + + DMA1 + DMA controller + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_CH1 + DMA1 channel 1 interrupt + 11 + + + DMA1_CH2 + DMA1 channel 2 interrupt + 12 + + + DMA1_CH3 + DMA1 channel 3 interrupt + 13 + + + DMA1_CH4 + DMA1 channel 4 interrupt + 14 + + + DMA1_CH5 + DMA1 channel 5 interrupt + 15 + + + DMA1_CH6 + DMA1 channel 6 interrupt + 16 + + + DMA1_CH8 + DMA1_CH8 + 96 + + + + ISR + ISR + interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + 0x4 + 0x20 + write-only + 0x00000000 + + + TEIF8 + TEIF8 + 31 + 1 + + + HTIF8 + HTIF8 + 30 + 1 + + + TCIF8 + TCIF8 + 29 + 1 + + + GIF8 + GIF8 + 28 + 1 + + + TEIF7 + TEIF7 + 27 + 1 + + + HTIF7 + HTIF7 + 26 + 1 + + + TCIF7 + TCIF7 + 25 + 1 + + + GIF7 + GIF7 + 24 + 1 + + + TEIF6 + TEIF6 + 23 + 1 + + + HTIF6 + HTIF6 + 22 + 1 + + + TCIF6 + TCIF6 + 21 + 1 + + + GIF6 + GIF6 + 20 + 1 + + + TEIF5 + TEIF5 + 19 + 1 + + + HTIF5 + HTIF5 + 18 + 1 + + + TCIF5 + TCIF5 + 17 + 1 + + + GIF5 + GIF5 + 16 + 1 + + + TEIF4 + TEIF4 + 15 + 1 + + + HTIF4 + HTIF4 + 14 + 1 + + + TCIF4 + TCIF4 + 13 + 1 + + + GIF4 + GIF4 + 12 + 1 + + + TEIF3 + TEIF3 + 11 + 1 + + + HTIF3 + HTIF3 + 10 + 1 + + + TCIF3 + TCIF3 + 9 + 1 + + + GIF3 + GIF3 + 8 + 1 + + + TEIF2 + TEIF2 + 7 + 1 + + + HTIF2 + HTIF2 + 6 + 1 + + + TCIF2 + TCIF2 + 5 + 1 + + + GIF2 + GIF2 + 4 + 1 + + + TEIF1 + TEIF1 + 3 + 1 + + + HTIF1 + HTIF1 + 2 + 1 + + + TCIF1 + TCIF1 + 1 + 1 + + + GIF1 + GIF1 + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel 1 configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR2 + CCR2 + DMA channel 2 configuration register + 0x1C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR3 + CCR3 + DMA channel 3 configuration register + 0x30 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR4 + CCR4 + DMA channel 3 configuration register + 0x44 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR5 + CCR5 + DMA channel 4 configuration register + 0x58 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR6 + CCR6 + DMA channel 5 configuration register + 0x6C + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR7 + CCR7 + DMA channel 6 configuration register + 0x80 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CCR8 + CCR8 + DMA channel 7 configuration register + 0x94 + 0x20 + read-write + 0x00000000 + + + EN + channel enable + 0 + 1 + + + TCIE + TCIE + 1 + 1 + + + HTIE + HTIE + 2 + 1 + + + TEIE + TEIE + 3 + 1 + + + DIR + DIR + 4 + 1 + + + CIRC + CIRC + 5 + 1 + + + PINC + PINC + 6 + 1 + + + MINC + MINC + 7 + 1 + + + PSIZE + PSIZE + 8 + 2 + + + MSIZE + MSIZE + 10 + 2 + + + PL + PL + 12 + 2 + + + MEM2MEM + MEM2MEM + 14 + 1 + + + + + CNDTR1 + CNDTR1 + channel x number of data to transfer register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR2 + CNDTR2 + channel x number of data to transfer register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR3 + CNDTR3 + channel x number of data to transfer register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR4 + CNDTR4 + channel x number of data to transfer register + 0x48 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR5 + CNDTR5 + channel x number of data to transfer register + 0x5C + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR6 + CNDTR6 + channel x number of data to transfer register + 0x70 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR7 + CNDTR7 + channel x number of data to transfer register + 0x84 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CNDTR8 + CNDTR8 + channel x number of data to transfer register + 0x98 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel x peripheral address register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR2 + CPAR2 + DMA channel x peripheral address register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR3 + CPAR3 + DMA channel x peripheral address register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR4 + CPAR4 + DMA channel x peripheral address register + 0x4C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR5 + CPAR5 + DMA channel x peripheral address register + 0x60 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR6 + CPAR6 + DMA channel x peripheral address register + 0x74 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR7 + CPAR7 + DMA channel x peripheral address register + 0x88 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CPAR8 + CPAR8 + DMA channel x peripheral address register + 0x9C + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel x memory address register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel x memory address register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel x memory address register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR4 + CMAR4 + DMA channel x memory address register + 0x50 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR5 + CMAR5 + DMA channel x memory address register + 0x64 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR6 + CMAR6 + DMA channel x memory address register + 0x78 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR7 + CMAR7 + DMA channel x memory address register + 0x8C + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + CMAR8 + CMAR8 + DMA channel x memory address register + 0xA0 + 0x20 + read-write + 0x00000000 + + + MA + Memory 1 address (used in case of Double buffer mode) + 0 + 32 + + + + + + + DMA2 + 0x40020400 + + DMA1_CH7 + DMA1 channel 7 interrupt + 17 + + + DMA2_CH1 + DMA2_CH1 + 56 + + + DMA2_CH2 + DMA2_CH2 + 57 + + + DMA2_CH3 + DMA2_CH3 + 58 + + + DMA2_CH4 + DMA2_CH4 + 59 + + + DMA2_CH5 + DMA2_CH5 + 60 + + + DMA2_CH6 + DMA2_CH6 + 97 + + + DMA2_CH7 + DMA2_CH7 + 98 + + + DMA2_CH8 + DMA2_CH8 + 99 + + + + DMAMUX + DMAMUX + DMAMUX + 0x40020800 + + 0x0 + 0x400 + registers + + + DMAMUX_OVR + DMAMUX_OVR + 94 + + + + C0CR + C0CR + DMAMux - DMA request line multiplexer channel x control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C1CR + C1CR + DMAMux - DMA request line multiplexer channel x control register + 0x4 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C2CR + C2CR + DMAMux - DMA request line multiplexer channel x control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C3CR + C3CR + DMAMux - DMA request line multiplexer channel x control register + 0xC + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C4CR + C4CR + DMAMux - DMA request line multiplexer channel x control register + 0x10 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C5CR + C5CR + DMAMux - DMA request line multiplexer channel x control register + 0x14 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C6CR + C6CR + DMAMux - DMA request line multiplexer channel x control register + 0x18 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C7CR + C7CR + DMAMux - DMA request line multiplexer channel x control register + 0x1C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C8CR + C8CR + DMAMux - DMA request line multiplexer channel x control register + 0x20 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C9CR + C9CR + DMAMux - DMA request line multiplexer channel x control register + 0x24 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C10CR + C10CR + DMAMux - DMA request line multiplexer channel x control register + 0x28 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C11CR + C11CR + DMAMux - DMA request line multiplexer channel x control register + 0x2C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C12CR + C12CR + DMAMux - DMA request line multiplexer channel x control register + 0x30 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C13CR + C13CR + DMAMux - DMA request line multiplexer channel x control register + 0x34 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C14CR + C14CR + DMAMux - DMA request line multiplexer channel x control register + 0x38 + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + C15CR + C15CR + DMAMux - DMA request line multiplexer channel x control register + 0x3C + 0x20 + read-write + 0x00000000 + + + DMAREQ_ID + Input DMA request line selected + 0 + 7 + + + SOIE + Interrupt enable at synchronization event overrun + 8 + 1 + + + EGE + Event generation enable/disable + 9 + 1 + + + SE + Synchronous operating mode enable/disable + 16 + 1 + + + SPOL + Synchronization event type selector Defines the synchronization event on the selected synchronization input: + 17 + 2 + + + NBREQ + Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset. + 19 + 5 + + + SYNC_ID + Synchronization input selected + 24 + 5 + + + + + RG0CR + RG0CR + DMAMux - DMA request generator channel x control register + 0x100 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG1CR + RG1CR + DMAMux - DMA request generator channel x control register + 0x104 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG2CR + RG2CR + DMAMux - DMA request generator channel x control register + 0x108 + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RG3CR + RG3CR + DMAMux - DMA request generator channel x control register + 0x10C + 0x20 + read-write + 0x00000000 + + + SIG_ID + DMA request trigger input selected + 0 + 5 + + + OIE + Interrupt enable at trigger event overrun + 8 + 1 + + + GE + DMA request generator channel enable/disable + 16 + 1 + + + GPOL + DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input + 17 + 2 + + + GNBREQ + Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset. + 19 + 5 + + + + + RGSR + RGSR + DMAMux - DMA request generator status register + 0x140 + 0x20 + read-only + 0x00000000 + + + OF + Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register. + 0 + 4 + + + + + RGCFR + RGCFR + DMAMux - DMA request generator clear flag register + 0x144 + 0x20 + write-only + 0x00000000 + + + COF + Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register. + 0 + 4 + + + + + CSR + CSR + DMAMUX request line multiplexer interrupt channel status register + 0x80 + 0x20 + read-only + 0x00000000 + + + SOF + Synchronization overrun event flag + 0 + 16 + + + + + CFR + CFR + DMAMUX request line multiplexer interrupt clear flag register + 0x84 + 0x20 + write-only + 0x00000000 + + + CSOF + Clear synchronization overrun event flag + 0 + 16 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x2A + registers + + + + MEMRMP + MEMRMP + Remap Memory register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + 0 + 3 + + + FB_mode + User Flash Bank mode + 8 + 1 + + + + + CFGR1 + CFGR1 + peripheral mode configuration register + 0x4 + 0x20 + read-write + 0x7C000001 + + + BOOSTEN + BOOSTEN + 8 + 1 + + + ANASWVDD + GPIO analog switch control voltage selection + 9 + 1 + + + I2C_PB6_FMP + FM+ drive capability on PB6 + 16 + 1 + + + I2C_PB7_FMP + FM+ drive capability on PB6 + 17 + 1 + + + I2C_PB8_FMP + FM+ drive capability on PB6 + 18 + 1 + + + I2C_PB9_FMP + FM+ drive capability on PB6 + 19 + 1 + + + I2C1_FMP + I2C1 FM+ drive capability enable + 20 + 1 + + + I2C2_FMP + I2C1 FM+ drive capability enable + 21 + 1 + + + I2C3_FMP + I2C1 FM+ drive capability enable + 22 + 1 + + + I2C4_FMP + I2C1 FM+ drive capability enable + 23 + 1 + + + FPU_IE + FPU Interrupts Enable + 26 + 6 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to 15) + 0 + 4 + + + + + SCSR + SCSR + CCM SRAM control and status register + 0x18 + 0x20 + 0x00000000 + + + CCMER + CCM SRAM Erase + 0 + 1 + read-write + + + CCMBSY + CCM SRAM busy by erase operation + 1 + 1 + read-only + + + + + CFGR2 + CFGR2 + configuration register 2 + 0x1C + 0x20 + read-write + 0x00000000 + + + CLL + Core Lockup Lock + 0 + 1 + + + SPL + SRAM Parity Lock + 1 + 1 + + + PVDL + PVD Lock + 2 + 1 + + + ECCL + ECC Lock + 3 + 1 + + + SPF + SRAM Parity Flag + 8 + 1 + + + + + SWPR + SWPR + SRAM Write protection register 1 + 0x20 + 0x20 + read-write + 0x00000000 + + + Page0_WP + Write protection + 0 + 1 + + + Page1_WP + Write protection + 1 + 1 + + + Page2_WP + Write protection + 2 + 1 + + + Page3_WP + Write protection + 3 + 1 + + + Page4_WP + Write protection + 4 + 1 + + + Page5_WP + Write protection + 5 + 1 + + + Page6_WP + Write protection + 6 + 1 + + + Page7_WP + Write protection + 7 + 1 + + + Page8_WP + Write protection + 8 + 1 + + + Page9_WP + Write protection + 9 + 1 + + + Page10_WP + Write protection + 10 + 1 + + + Page11_WP + Write protection + 11 + 1 + + + Page12_WP + Write protection + 12 + 1 + + + Page13_WP + Write protection + 13 + 1 + + + Page14_WP + Write protection + 14 + 1 + + + Page15_WP + Write protection + 15 + 1 + + + Page16_WP + Write protection + 16 + 1 + + + Page17_WP + Write protection + 17 + 1 + + + Page18_WP + Write protection + 18 + 1 + + + Page19_WP + Write protection + 19 + 1 + + + Page20_WP + Write protection + 20 + 1 + + + Page21_WP + Write protection + 21 + 1 + + + Page22_WP + Write protection + 22 + 1 + + + Page23_WP + Write protection + 23 + 1 + + + Page24_WP + Write protection + 24 + 1 + + + Page25_WP + Write protection + 25 + 1 + + + Page26_WP + Write protection + 26 + 1 + + + Page27_WP + Write protection + 27 + 1 + + + Page28_WP + Write protection + 28 + 1 + + + Page29_WP + Write protection + 29 + 1 + + + Page30_WP + Write protection + 30 + 1 + + + Page31_WP + Write protection + 31 + 1 + + + + + SKR + SKR + SRAM2 Key Register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + SRAM2 Key for software erase + 0 + 8 + + + + + + + VREFBUF + Voltage reference buffer + VREFBUF + 0x40010030 + + 0x0 + 0x1D0 + registers + + + + VREFBUF_CSR + VREFBUF_CSR + VREF_BUF Control and Status Register + 0x0 + 0x20 + 0x00000002 + + + ENVR + Enable Voltage Reference + 0 + 1 + read-write + + + HIZ + High impedence mode for the VREF_BUF + 1 + 1 + read-write + + + VRR + Voltage reference buffer ready + 3 + 1 + read-only + + + VRS + Voltage reference scale + 4 + 2 + read-write + + + + + VREFBUF_CCR + VREFBUF_CCR + VREF_BUF Calibration Control Register + 0x04 + 0x20 + read-write + 0x00000000 + + + TRIM + Trimming code + 0 + 6 + + + + + + + COMP + Comparator control and status register + COMP + 0x40010200 + + 0x0 + 0x100 + registers + + + COMP1_2_3 + COMP1_2_3 + 64 + + + COMP4_5_6 + COMP4_5_6 + 65 + + + COMP7 + COMP7 + 66 + + + + COMP_C1CSR + COMP_C1CSR + Comparator control/status register + 0x0 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + COMP_DEGLITCH_EN + COMP_DEGLITCH_EN + 1 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C2CSR + COMP_C2CSR + Comparator control/status register + 0x4 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + COMP_DEGLITCH_EN + COMP_DEGLITCH_EN + 1 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C3CSR + COMP_C3CSR + Comparator control/status register + 0x8 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + COMP_DEGLITCH_EN + COMP_DEGLITCH_EN + 1 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C4CSR + COMP_C4CSR + Comparator control/status register + 0x0C + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + COMP_DEGLITCH_EN + COMP_DEGLITCH_EN + 1 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C5CSR + COMP_C5CSR + Comparator control/status register + 0x10 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + COMP_DEGLITCH_EN + COMP_DEGLITCH_EN + 1 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C6CSR + COMP_C6CSR + Comparator control/status register + 0x14 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + COMP_DEGLITCH_EN + COMP_DEGLITCH_EN + 1 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + COMP_C7CSR + COMP_C7CSR + Comparator control/status register + 0x18 + 0x20 + 0x00000000 + + + EN + EN + 0 + 1 + read-write + + + COMP_DEGLITCH_EN + COMP_DEGLITCH_EN + 1 + 1 + read-write + + + INMSEL + INMSEL + 4 + 3 + read-write + + + INPSEL + INPSEL + 8 + 1 + read-write + + + POL + POL + 15 + 1 + read-write + + + HYST + HYST + 16 + 3 + read-write + + + BLANKSEL + BLANKSEL + 19 + 3 + read-write + + + BRGEN + BRGEN + 22 + 1 + read-write + + + SCALEN + SCALEN + 23 + 1 + read-write + + + VALUE + VALUE + 30 + 1 + read-only + + + LOCK + LOCK + 31 + 1 + read-write + + + + + + + OPAMP + Operational amplifiers + OPAMP + 0x40010300 + + 0x0 + 0x100 + registers + + + + OPAMP1_CSR + OPAMP1_CSR + OPAMP1 control/status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP2_CSR + OPAMP2_CSR + OPAMP2 control/status register + 0x4 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP3_CSR + OPAMP3_CSR + OPAMP3 control/status register + 0x8 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP4_CSR + OPAMP4_CSR + OPAMP4 control/status register + 0xC + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP5_CSR + OPAMP5_CSR + OPAMP5 control/status register + 0x10 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP6_CSR + OPAMP6_CSR + OPAMP6 control/status register + 0x14 + 0x20 + read-write + 0x00000000 + + + OPAEN + Operational amplifier Enable + 0 + 1 + + + FORCE_VP + FORCE_VP + 1 + 1 + + + VP_SEL + VP_SEL + 2 + 2 + + + USERTRIM + USERTRIM + 4 + 1 + + + VM_SEL + VM_SEL + 5 + 2 + + + OPAHSM + OPAHSM + 7 + 1 + + + OPAINTOEN + OPAINTOEN + 8 + 1 + + + CALON + CALON + 11 + 1 + + + CALSEL + CALSEL + 12 + 2 + + + PGA_GAIN + PGA_GAIN + 14 + 5 + + + TRIMOFFSETP + TRIMOFFSETP + 19 + 5 + + + TRIMOFFSETN + TRIMOFFSETN + 24 + 5 + + + CALOUT + CALOUT + 30 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP1_TCMR + OPAMP1_TCMR + OPAMP1 control/status register + 0x18 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP2_TCMR + OPAMP2_TCMR + OPAMP2 control/status register + 0x1C + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP3_TCMR + OPAMP3_TCMR + OPAMP3 control/status register + 0x20 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP4_TCMR + OPAMP4_TCMR + OPAMP4 control/status register + 0x24 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP5_TCMR + OPAMP5_TCMR + OPAMP5 control/status register + 0x28 + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + OPAMP6_TCMR + OPAMP6_TCMR + OPAMP6 control/status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VMS_SEL + VMS_SEL + 0 + 1 + + + VPS_SEL + VPS_SEL + 1 + 2 + + + T1CM_EN + T1CM_EN + 3 + 1 + + + T8CM_EN + T8CM_EN + 4 + 1 + + + T20CM_EN + T20CM_EN + 5 + 1 + + + LOCK + LOCK + 31 + 1 + + + + + + + HRTIM_Master + High Resolution Timer: Master Timers + HRTIM + 0x40016800 + + 0x0 + 0x80 + registers + + + HRTIM_Master_IRQn + HRTIM_Master_IRQn + 67 + + + + MCR + MCR + Master Timer Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + BRSTDMA + Burst DMA Update + 30 + 2 + + + MREPU + Master Timer Repetition update + 29 + 1 + + + PREEN + Preload enable + 27 + 1 + + + DACSYNC + AC Synchronization + 25 + 2 + + + TFCEN + Timer F counter enable + 22 + 1 + + + TECEN + Timer E counter enable + 21 + 1 + + + TDCEN + Timer D counter enable + 20 + 1 + + + TCCEN + Timer C counter enable + 19 + 1 + + + TBCEN + Timer B counter enable + 18 + 1 + + + TACEN + Timer A counter enable + 17 + 1 + + + MCEN + Master Counter enable + 16 + 1 + + + SYNC_SRC + Synchronization source + 14 + 2 + + + SYNC_OUT + Synchronization output + 12 + 2 + + + SYNCSTRTM + Synchronization Starts Master + 11 + 1 + + + SYNCRSTM + Synchronization Resets Master + 10 + 1 + + + SYNC_IN + synchronization input + 8 + 2 + + + INTLVD + Interleaved mode + 6 + 2 + + + HALF + Half mode enable + 5 + 1 + + + RETRIG + Master Re-triggerable mode + 4 + 1 + + + CONT + Master Continuous mode + 3 + 1 + + + CK_PSC + HRTIM Master Clock prescaler + 0 + 3 + + + + + MISR + MISR + Master Timer Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + MUPD + Master Update Interrupt Flag + 6 + 1 + + + SYNC + Sync Input Interrupt Flag + 5 + 1 + + + MREP + Master Repetition Interrupt Flag + 4 + 1 + + + MCMP4 + Master Compare 4 Interrupt Flag + 3 + 1 + + + MCMP3 + Master Compare 3 Interrupt Flag + 2 + 1 + + + MCMP2 + Master Compare 2 Interrupt Flag + 1 + 1 + + + MCMP1 + Master Compare 1 Interrupt Flag + 0 + 1 + + + + + MICR + MICR + Master Timer Interrupt Clear Register + 0x8 + 0x20 + write-only + 0x00000000 + + + MUPDC + Master update Interrupt flag clear + 6 + 1 + + + SYNCC + Sync Input Interrupt flag clear + 5 + 1 + + + MREPC + Repetition Interrupt flag clear + 4 + 1 + + + MCMP4C + Master Compare 4 Interrupt flag clear + 3 + 1 + + + MCMP3C + Master Compare 3 Interrupt flag clear + 2 + 1 + + + MCMP2C + Master Compare 2 Interrupt flag clear + 1 + 1 + + + MCMP1C + Master Compare 1 Interrupt flag clear + 0 + 1 + + + + + MDIER + MDIER + HRTIM Master Timer DMA / Interrupt Enable Register + 0xC + 0x20 + read-write + 0x00000000 + + + MUPDDE + MUPDDE + 22 + 1 + + + SYNCDE + SYNCDE + 21 + 1 + + + MREPDE + MREPDE + 20 + 1 + + + MCMP4DE + MCMP4DE + 19 + 1 + + + MCMP3DE + MCMP3DE + 18 + 1 + + + MCMP2DE + MCMP2DE + 17 + 1 + + + MCMP1DE + MCMP1DE + 16 + 1 + + + MUPDIE + MUPDIE + 6 + 1 + + + SYNCIE + SYNCIE + 5 + 1 + + + MREPIE + MREPIE + 4 + 1 + + + MCMP4IE + MCMP4IE + 3 + 1 + + + MCMP3IE + MCMP3IE + 2 + 1 + + + MCMP2IE + MCMP2IE + 1 + 1 + + + MCMP1IE + MCMP1IE + 0 + 1 + + + + + MCNTR + MCNTR + Master Timer Counter Register + 0x10 + 0x20 + read-write + 0x00000000 + + + MCNT + Counter value + 0 + 16 + + + + + MPER + MPER + Master Timer Period Register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + MPER + Master Timer Period value + 0 + 16 + + + + + MREP + MREP + Master Timer Repetition Register + 0x18 + 0x20 + read-write + 0x00000000 + + + MREP + Master Timer Repetition counter value + 0 + 8 + + + + + MCMP1R + MCMP1R + Master Timer Compare 1 Register + 0x1C + 0x20 + read-write + 0x00000000 + + + MCMP1 + Master Timer Compare 1 value + 0 + 16 + + + + + MCMP2R + MCMP2R + Master Timer Compare 2 Register + 0x24 + 0x20 + read-write + 0x00000000 + + + MCMP2 + Master Timer Compare 2 value + 0 + 16 + + + + + MCMP3R + MCMP3R + Master Timer Compare 3 Register + 0x28 + 0x20 + read-write + 0x00000000 + + + MCMP3 + Master Timer Compare 3 value + 0 + 16 + + + + + MCMP4R + MCMP4R + Master Timer Compare 4 Register + 0x2C + 0x20 + read-write + 0x00000000 + + + MCMP4 + Master Timer Compare 4 value + 0 + 16 + + + + + + + HRTIM_TIMA + High Resolution Timer: TIMA + HRTIM + 0x40016880 + + 0x0 + 0x80 + registers + + + HRTIM_TIMA_IRQn + HRTIM_TIMA_IRQn + 68 + + + + TIMACR + TIMACR + Timerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + UPDGAT + Update Gating + 28 + 4 + + + PREEN + Preload enable + 27 + 1 + + + DACSYNC + AC Synchronization + 25 + 2 + + + MSTU + Master Timer update + 24 + 1 + + + TEU + TEU + 23 + 1 + + + TDU + TDU + 22 + 1 + + + TCU + TCU + 21 + 1 + + + TBU + TBU + 20 + 1 + + + TxRSTU + Timerx reset update + 18 + 1 + + + TxREPU + Timer x Repetition update + 17 + 1 + + + TFU + TFU + 16 + 1 + + + DELCMP4 + Delayed CMP4 mode + 14 + 2 + + + DELCMP2 + Delayed CMP2 mode + 12 + 2 + + + SYNCSTRTx + Synchronization Starts Timer x + 11 + 1 + + + SYNCRSTx + Synchronization Resets Timer x + 10 + 1 + + + RSYNCU + Re-Synchronized Update + 9 + 1 + + + INTLVD + Interleaved mode + 7 + 2 + + + PSHPLL + Push-Pull mode enable + 6 + 1 + + + HALF + Half mode enable + 5 + 1 + + + RETRIG + Re-triggerable mode + 4 + 1 + + + CONT + Continuous mode + 3 + 1 + + + CK_PSCx + HRTIM Timer x Clock prescaler + 0 + 3 + + + + + TIMAISR + TIMAISR + Timerx Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + O2CPY + Output 2 Copy + 21 + 1 + + + O1CPY + Output 1 Copy + 20 + 1 + + + O2STAT + Output 2 State + 19 + 1 + + + O1STAT + Output 1 State + 18 + 1 + + + IPPSTAT + Idle Push Pull Status + 17 + 1 + + + CPPSTAT + Current Push Pull Status + 16 + 1 + + + DLYPRT + Delayed Protection Flag + 14 + 1 + + + RST + Reset Interrupt Flag + 13 + 1 + + + RSTx2 + Output 2 Reset Interrupt Flag + 12 + 1 + + + SETx2 + Output 2 Set Interrupt Flag + 11 + 1 + + + RSTx1 + Output 1 Reset Interrupt Flag + 10 + 1 + + + SETx1 + Output 1 Set Interrupt Flag + 9 + 1 + + + CPT2 + Capture2 Interrupt Flag + 8 + 1 + + + CPT1 + Capture1 Interrupt Flag + 7 + 1 + + + UPD + Update Interrupt Flag + 6 + 1 + + + REP + Repetition Interrupt Flag + 4 + 1 + + + CMP4 + Compare 4 Interrupt Flag + 3 + 1 + + + CMP3 + Compare 3 Interrupt Flag + 2 + 1 + + + CMP2 + Compare 2 Interrupt Flag + 1 + 1 + + + CMP1 + Compare 1 Interrupt Flag + 0 + 1 + + + + + TIMAICR + TIMAICR + Timerx Interrupt Clear Register + 0x8 + 0x20 + write-only + 0x00000000 + + + DLYPRTC + Delayed Protection Flag Clear + 14 + 1 + + + RSTC + Reset Interrupt flag Clear + 13 + 1 + + + RSTx2C + Output 2 Reset flag Clear + 12 + 1 + + + SET2xC + Output 2 Set flag Clear + 11 + 1 + + + RSTx1C + Output 1 Reset flag Clear + 10 + 1 + + + SET1xC + Output 1 Set flag Clear + 9 + 1 + + + CPT2C + Capture2 Interrupt flag Clear + 8 + 1 + + + CPT1C + Capture1 Interrupt flag Clear + 7 + 1 + + + UPDC + Update Interrupt flag Clear + 6 + 1 + + + REPC + Repetition Interrupt flag Clear + 4 + 1 + + + CMP4C + Compare 4 Interrupt flag Clear + 3 + 1 + + + CMP3C + Compare 3 Interrupt flag Clear + 2 + 1 + + + CMP2C + Compare 2 Interrupt flag Clear + 1 + 1 + + + CMP1C + Compare 1 Interrupt flag Clear + 0 + 1 + + + + + TIMADIER + TIMADIER + TIMxDIER + 0xC + 0x20 + read-write + 0x00000000 + + + DLYPRTDE + DLYPRTDE + 30 + 1 + + + RSTDE + RSTDE + 29 + 1 + + + RSTx2DE + RSTx2DE + 28 + 1 + + + SETx2DE + SETx2DE + 27 + 1 + + + RSTx1DE + RSTx1DE + 26 + 1 + + + SET1xDE + SET1xDE + 25 + 1 + + + CPT2DE + CPT2DE + 24 + 1 + + + CPT1DE + CPT1DE + 23 + 1 + + + UPDDE + UPDDE + 22 + 1 + + + REPDE + REPDE + 20 + 1 + + + CMP4DE + CMP4DE + 19 + 1 + + + CMP3DE + CMP3DE + 18 + 1 + + + CMP2DE + CMP2DE + 17 + 1 + + + CMP1DE + CMP1DE + 16 + 1 + + + DLYPRTIE + DLYPRTIE + 14 + 1 + + + RSTIE + RSTIE + 13 + 1 + + + RSTx2IE + RSTx2IE + 12 + 1 + + + SETx2IE + SETx2IE + 11 + 1 + + + RSTx1IE + RSTx1IE + 10 + 1 + + + SET1xIE + SET1xIE + 9 + 1 + + + CPT2IE + CPT2IE + 8 + 1 + + + CPT1IE + CPT1IE + 7 + 1 + + + UPDIE + UPDIE + 6 + 1 + + + REPIE + REPIE + 4 + 1 + + + CMP4IE + CMP4IE + 3 + 1 + + + CMP3IE + CMP3IE + 2 + 1 + + + CMP2IE + CMP2IE + 1 + 1 + + + CMP1IE + CMP1IE + 0 + 1 + + + + + CNTAR + CNTAR + Timerx Counter Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTx + Timerx Counter value + 0 + 16 + + + + + PERAR + PERAR + Timerx Period Register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + PERx + Timerx Period value + 0 + 16 + + + + + REPAR + REPAR + Timerx Repetition Register + 0x18 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition counter value + 0 + 8 + + + + + CMP1AR + CMP1AR + Timerx Compare 1 Register + 0x1C + 0x20 + read-write + 0x00000000 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP1CAR + CMP1CAR + Timerx Compare 1 Compound Register + 0x20 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition value (aliased from HRTIM_REPx register) + 16 + 8 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP2AR + CMP2AR + Timerx Compare 2 Register + 0x24 + 0x20 + read-write + 0x00000000 + + + CMP2x + Timerx Compare 2 value + 0 + 16 + + + + + CMP3AR + CMP3AR + Timerx Compare 3 Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CMP3x + Timerx Compare 3 value + 0 + 16 + + + + + CMP4AR + CMP4AR + Timerx Compare 4 Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CMP4x + Timerx Compare 4 value + 0 + 16 + + + + + CPT1AR + CPT1AR + Timerx Capture 1 Register + 0x30 + 0x20 + read-only + 0x00000000 + + + CPT1x + Timerx Capture 1 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + CPT2AR + CPT2AR + Timerx Capture 2 Register + 0x34 + 0x20 + read-only + 0x00000000 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + CPT2x + Timerx Capture 2 value + 0 + 16 + + + + + DTAR + DTAR + Timerx Deadtime Register + 0x38 + 0x20 + read-write + 0x00000000 + + + DTFLKx + Deadtime Falling Lock + 31 + 1 + + + DTFSLKx + Deadtime Falling Sign Lock + 30 + 1 + + + SDTFx + Sign Deadtime Falling value + 25 + 1 + + + DTFx + Deadtime Falling value + 16 + 9 + + + DTRLKx + Deadtime Rising Lock + 15 + 1 + + + DTRSLKx + Deadtime Rising Sign Lock + 14 + 1 + + + DTPRSC + Deadtime Prescaler + 10 + 3 + + + SDTRx + Sign Deadtime Rising value + 9 + 1 + + + DTRx + Deadtime Rising value + 0 + 9 + + + + + SETA1R + SETA1R + Timerx Output1 Set Register + 0x3C + 0x20 + read-write + 0x00000000 + + + UPDATE + Registers update (transfer preload to active) + 31 + 1 + + + EXTEVNT10 + External Event 10 + 30 + 1 + + + EXTEVNT9 + External Event 9 + 29 + 1 + + + EXTEVNT8 + External Event 8 + 28 + 1 + + + EXTEVNT7 + External Event 7 + 27 + 1 + + + EXTEVNT6 + External Event 6 + 26 + 1 + + + EXTEVNT5 + External Event 5 + 25 + 1 + + + EXTEVNT4 + External Event 4 + 24 + 1 + + + EXTEVNT3 + External Event 3 + 23 + 1 + + + EXTEVNT2 + External Event 2 + 22 + 1 + + + EXTEVNT1 + External Event 1 + 21 + 1 + + + TIMEVNT9 + Timer Event 9 + 20 + 1 + + + TIMEVNT8 + Timer Event 8 + 19 + 1 + + + TIMEVNT7 + Timer Event 7 + 18 + 1 + + + TIMEVNT6 + Timer Event 6 + 17 + 1 + + + TIMEVNT5 + Timer Event 5 + 16 + 1 + + + TIMEVNT4 + Timer Event 4 + 15 + 1 + + + TIMEVNT3 + Timer Event 3 + 14 + 1 + + + TIMEVNT2 + Timer Event 2 + 13 + 1 + + + TIMEVNT1 + Timer Event 1 + 12 + 1 + + + MSTCMP4 + Master Compare 4 + 11 + 1 + + + MSTCMP3 + Master Compare 3 + 10 + 1 + + + MSTCMP2 + Master Compare 2 + 9 + 1 + + + MSTCMP1 + Master Compare 1 + 8 + 1 + + + MSTPER + Master Period + 7 + 1 + + + CMP4 + Timer A compare 4 + 6 + 1 + + + CMP3 + Timer A compare 3 + 5 + 1 + + + CMP2 + Timer A compare 2 + 4 + 1 + + + CMP1 + Timer A compare 1 + 3 + 1 + + + PER + Timer A Period + 2 + 1 + + + RESYNC + Timer A resynchronizaton + 1 + 1 + + + SST + Software Set trigger + 0 + 1 + + + + + RSTA1R + RSTA1R + Timerx Output1 Reset Register + 0x40 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + SETA2R + SETA2R + Timerx Output2 Set Register + 0x44 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SST + SST + 0 + 1 + + + + + RSTA2R + RSTA2R + Timerx Output2 Reset Register + 0x48 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + EEFAR1 + EEFAR1 + Timerx External Event Filtering Register 1 + 0x4C + 0x20 + read-write + 0x00000000 + + + EE5FLTR + External Event 5 filter + 25 + 4 + + + EE5LTCH + External Event 5 latch + 24 + 1 + + + EE4FLTR + External Event 4 filter + 19 + 4 + + + EE4LTCH + External Event 4 latch + 18 + 1 + + + EE3FLTR + External Event 3 filter + 13 + 4 + + + EE3LTCH + External Event 3 latch + 12 + 1 + + + EE2FLTR + External Event 2 filter + 7 + 4 + + + EE2LTCH + External Event 2 latch + 6 + 1 + + + EE1FLTR + External Event 1 filter + 1 + 4 + + + EE1LTCH + External Event 1 latch + 0 + 1 + + + + + EEFAR2 + EEFAR2 + Timerx External Event Filtering Register 2 + 0x50 + 0x20 + read-write + 0x00000000 + + + EE10FLTR + External Event 10 filter + 25 + 4 + + + EE10LTCH + External Event 10 latch + 24 + 1 + + + EE9FLTR + External Event 9 filter + 19 + 4 + + + EE9LTCH + External Event 9 latch + 18 + 1 + + + EE8FLTR + External Event 8 filter + 13 + 4 + + + EE8LTCH + External Event 8 latch + 12 + 1 + + + EE7FLTR + External Event 7 filter + 7 + 4 + + + EE7LTCH + External Event 7 latch + 6 + 1 + + + EE6FLTR + External Event 6 filter + 1 + 4 + + + EE6LTCH + External Event 6 latch + 0 + 1 + + + + + RSTAR + RSTAR + TimerA Reset Register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIMFCPM2 + Timer F Compare 2 + 31 + 1 + + + TIMECMP4 + Timer E Compare 4 + 30 + 1 + + + TIMECMP2 + Timer E Compare 2 + 29 + 1 + + + TIMECMP1 + Timer E Compare 1 + 28 + 1 + + + TIMDCMP4 + Timer D Compare 4 + 27 + 1 + + + TIMDCMP2 + Timer D Compare 2 + 26 + 1 + + + TIMDCMP1 + Timer D Compare 1 + 25 + 1 + + + TIMCCMP4 + Timer C Compare 4 + 24 + 1 + + + TIMCCMP2 + Timer C Compare 2 + 23 + 1 + + + TIMCCMP1 + Timer C Compare 1 + 22 + 1 + + + TIMBCMP4 + Timer B Compare 4 + 21 + 1 + + + TIMBCMP2 + Timer B Compare 2 + 20 + 1 + + + TIMBCMP1 + Timer B Compare 1 + 19 + 1 + + + EXTEVNT10 + External Event 10 + 18 + 1 + + + EXTEVNT9 + External Event 9 + 17 + 1 + + + EXTEVNT8 + External Event 8 + 16 + 1 + + + EXTEVNT7 + External Event 7 + 15 + 1 + + + EXTEVNT6 + External Event 6 + 14 + 1 + + + EXTEVNT5 + External Event 5 + 13 + 1 + + + EXTEVNT4 + External Event 4 + 12 + 1 + + + EXTEVNT3 + External Event 3 + 11 + 1 + + + EXTEVNT2 + External Event 2 + 10 + 1 + + + EXTEVNT1 + External Event 1 + 9 + 1 + + + MSTCMP4 + Master compare 4 + 8 + 1 + + + MSTCMP3 + Master compare 3 + 7 + 1 + + + MSTCMP2 + Master compare 2 + 6 + 1 + + + MSTCMP1 + Master compare 1 + 5 + 1 + + + MSTPER + Master timer Period + 4 + 1 + + + CMP4 + Timer A compare 4 reset + 3 + 1 + + + CMP2 + Timer A compare 2 reset + 2 + 1 + + + UPDT + Timer A Update reset + 1 + 1 + + + TIMFCMP1 + Timer A Update reset + 0 + 1 + + + + + CHPAR + CHPAR + Timerx Chopper Register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRTPW + STRTPW + 7 + 4 + + + CHPDTY + Timerx chopper duty cycle value + 4 + 3 + + + CHPFRQ + Timerx carrier frequency value + 0 + 4 + + + + + CPT1ACR + CPT1ACR + Timerx Capture 2 Control Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TFCMP2 + TFCMP2 + 15 + 1 + + + TFCMP1 + TFCMP1 + 14 + 1 + + + TF1RST + TF1RST + 13 + 1 + + + TF1SET + TF1SET + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + CPT2ACR + CPT2ACR + CPT2xCR + 0x60 + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TFCMP2 + TFCMP2 + 15 + 1 + + + TFCMP1 + TFCMP1 + 14 + 1 + + + TF1RST + TF1RST + 13 + 1 + + + TF1SET + TF1SET + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + OUTAR + OUTAR + Timerx Output Register + 0x64 + 0x20 + read-write + 0x00000000 + + + DIDL2 + Output 2 Deadtime upon burst mode Idle entry + 23 + 1 + + + CHP2 + Output 2 Chopper enable + 22 + 1 + + + FAULT2 + Output 2 Fault state + 20 + 2 + + + IDLES2 + Output 2 Idle State + 19 + 1 + + + IDLEM2 + Output 2 Idle mode + 18 + 1 + + + POL2 + Output 2 polarity + 17 + 1 + + + BIAR + Balanced Idle Automatic Resume + 14 + 1 + + + DLYPRT + Delayed Protection + 10 + 3 + + + DLYPRTEN + Delayed Protection Enable + 9 + 1 + + + DTEN + Deadtime enable + 8 + 1 + + + DIDL1 + Output 1 Deadtime upon burst mode Idle entry + 7 + 1 + + + CHP1 + Output 1 Chopper enable + 6 + 1 + + + FAULT1 + Output 1 Fault state + 4 + 2 + + + IDLES1 + Output 1 Idle State + 3 + 1 + + + IDLEM1 + Output 1 Idle mode + 2 + 1 + + + POL1 + Output 1 polarity + 1 + 1 + + + + + FLTAR + FLTAR + Timerx Fault Register + 0x68 + 0x20 + read-write + 0x00000000 + + + FLTLCK + Fault sources Lock + 31 + 1 + + + FLT6EN + Fault 6 enable + 5 + 1 + + + FLT5EN + Fault 5 enable + 4 + 1 + + + FLT4EN + Fault 4 enable + 3 + 1 + + + FLT3EN + Fault 3 enable + 2 + 1 + + + FLT2EN + Fault 2 enable + 1 + 1 + + + FLT1EN + Fault 1 enable + 0 + 1 + + + + + TIMACR2 + TIMACR2 + HRTIM Timerx Control Register 2 + 0x6C + 0x20 + read-write + 0x00000000 + + + TRGHLF + Triggered-half mode + 20 + 1 + + + GTCMP3 + Greater than Compare 3 PWM mode + 17 + 1 + + + GTCMP1 + Greater than Compare 1 PWM mode + 16 + 1 + + + FEROM + Fault and Event Roll-Over Mode + 14 + 2 + + + BMROM + Burst Mode Roll-Over Mode + 12 + 2 + + + ADROM + ADC Roll-Over Mode + 10 + 2 + + + OUTROM + Output Roll-Over Mode + 8 + 2 + + + ROM + Roll-Over Mode + 6 + 2 + + + UDM + Up-Down Mode + 4 + 1 + + + DCDR + Dual Channel DAC Reset trigger + 2 + 1 + + + DCDS + Dual Channel DAC Step trigger + 1 + 1 + + + DCDE + Dual Channel DAC trigger enable + 0 + 1 + + + + + AEEFR3 + AEEFR3 + HRTIM Timerx External Event Filtering Register 3 + 0x70 + 0x20 + read-write + 0x00000000 + + + EEVACNT + External Event A counter + 8 + 6 + + + EEVASEL + External Event A Selection + 4 + 4 + + + EEVARSTM + External Event A Reset Mode + 2 + 1 + + + EEVACRES + External Event A Counter Reset + 1 + 1 + + + EEVACE + External Event A Counter Enable + 0 + 1 + + + + + + + HRTIM_TIMB + High Resolution Timer: TIMB + HRTIM + 0x40016900 + + 0x0 + 0x80 + registers + + + HRTIM_TIMB_IRQn + HRTIM_TIMB_IRQn + 69 + + + + TIMBCR + TIMBCR + Timerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + UPDGAT + Update Gating + 28 + 4 + + + PREEN + Preload enable + 27 + 1 + + + DACSYNC + AC Synchronization + 25 + 2 + + + MSTU + Master Timer update + 24 + 1 + + + TEU + TEU + 23 + 1 + + + TDU + TDU + 22 + 1 + + + TCU + TCU + 21 + 1 + + + TAU + TAU + 19 + 1 + + + TxRSTU + Timerx reset update + 18 + 1 + + + TxREPU + Timer x Repetition update + 17 + 1 + + + TFU + TFU + 16 + 1 + + + DELCMP4 + Delayed CMP4 mode + 14 + 2 + + + DELCMP2 + Delayed CMP2 mode + 12 + 2 + + + SYNCSTRTx + Synchronization Starts Timer x + 11 + 1 + + + SYNCRSTx + Synchronization Resets Timer x + 10 + 1 + + + RSYNCU + Re-Synchronized Update + 9 + 1 + + + INTLVD + Interleaved mode + 7 + 2 + + + PSHPLL + Push-Pull mode enable + 6 + 1 + + + HALF + Half mode enable + 5 + 1 + + + RETRIG + Re-triggerable mode + 4 + 1 + + + CONT + Continuous mode + 3 + 1 + + + CK_PSCx + HRTIM Timer x Clock prescaler + 0 + 3 + + + + + TIMBISR + TIMBISR + Timerx Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + O2CPY + Output 2 Copy + 21 + 1 + + + O1CPY + Output 1 Copy + 20 + 1 + + + O2STAT + Output 2 State + 19 + 1 + + + O1STAT + Output 1 State + 18 + 1 + + + IPPSTAT + Idle Push Pull Status + 17 + 1 + + + CPPSTAT + Current Push Pull Status + 16 + 1 + + + DLYPRT + Delayed Protection Flag + 14 + 1 + + + RST + Reset Interrupt Flag + 13 + 1 + + + RSTx2 + Output 2 Reset Interrupt Flag + 12 + 1 + + + SETx2 + Output 2 Set Interrupt Flag + 11 + 1 + + + RSTx1 + Output 1 Reset Interrupt Flag + 10 + 1 + + + SETx1 + Output 1 Set Interrupt Flag + 9 + 1 + + + CPT2 + Capture2 Interrupt Flag + 8 + 1 + + + CPT1 + Capture1 Interrupt Flag + 7 + 1 + + + UPD + Update Interrupt Flag + 6 + 1 + + + REP + Repetition Interrupt Flag + 4 + 1 + + + CMP4 + Compare 4 Interrupt Flag + 3 + 1 + + + CMP3 + Compare 3 Interrupt Flag + 2 + 1 + + + CMP2 + Compare 2 Interrupt Flag + 1 + 1 + + + CMP1 + Compare 1 Interrupt Flag + 0 + 1 + + + + + TIMBICR + TIMBICR + Timerx Interrupt Clear Register + 0x8 + 0x20 + write-only + 0x00000000 + + + DLYPRTC + Delayed Protection Flag Clear + 14 + 1 + + + RSTC + Reset Interrupt flag Clear + 13 + 1 + + + RSTx2C + Output 2 Reset flag Clear + 12 + 1 + + + SET2xC + Output 2 Set flag Clear + 11 + 1 + + + RSTx1C + Output 1 Reset flag Clear + 10 + 1 + + + SET1xC + Output 1 Set flag Clear + 9 + 1 + + + CPT2C + Capture2 Interrupt flag Clear + 8 + 1 + + + CPT1C + Capture1 Interrupt flag Clear + 7 + 1 + + + UPDC + Update Interrupt flag Clear + 6 + 1 + + + REPC + Repetition Interrupt flag Clear + 4 + 1 + + + CMP4C + Compare 4 Interrupt flag Clear + 3 + 1 + + + CMP3C + Compare 3 Interrupt flag Clear + 2 + 1 + + + CMP2C + Compare 2 Interrupt flag Clear + 1 + 1 + + + CMP1C + Compare 1 Interrupt flag Clear + 0 + 1 + + + + + TIMBDIER + TIMBDIER + TIMxDIER + 0xC + 0x20 + read-write + 0x00000000 + + + DLYPRTDE + DLYPRTDE + 30 + 1 + + + RSTDE + RSTDE + 29 + 1 + + + RSTx2DE + RSTx2DE + 28 + 1 + + + SETx2DE + SETx2DE + 27 + 1 + + + RSTx1DE + RSTx1DE + 26 + 1 + + + SET1xDE + SET1xDE + 25 + 1 + + + CPT2DE + CPT2DE + 24 + 1 + + + CPT1DE + CPT1DE + 23 + 1 + + + UPDDE + UPDDE + 22 + 1 + + + REPDE + REPDE + 20 + 1 + + + CMP4DE + CMP4DE + 19 + 1 + + + CMP3DE + CMP3DE + 18 + 1 + + + CMP2DE + CMP2DE + 17 + 1 + + + CMP1DE + CMP1DE + 16 + 1 + + + DLYPRTIE + DLYPRTIE + 14 + 1 + + + RSTIE + RSTIE + 13 + 1 + + + RSTx2IE + RSTx2IE + 12 + 1 + + + SETx2IE + SETx2IE + 11 + 1 + + + RSTx1IE + RSTx1IE + 10 + 1 + + + SET1xIE + SET1xIE + 9 + 1 + + + CPT2IE + CPT2IE + 8 + 1 + + + CPT1IE + CPT1IE + 7 + 1 + + + UPDIE + UPDIE + 6 + 1 + + + REPIE + REPIE + 4 + 1 + + + CMP4IE + CMP4IE + 3 + 1 + + + CMP3IE + CMP3IE + 2 + 1 + + + CMP2IE + CMP2IE + 1 + 1 + + + CMP1IE + CMP1IE + 0 + 1 + + + + + CNTR + CNTR + Timerx Counter Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTx + Timerx Counter value + 0 + 16 + + + + + PERBR + PERBR + Timerx Period Register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + PERx + Timerx Period value + 0 + 16 + + + + + REPBR + REPBR + Timerx Repetition Register + 0x18 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition counter value + 0 + 8 + + + + + CMP1BR + CMP1BR + Timerx Compare 1 Register + 0x1C + 0x20 + read-write + 0x00000000 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP1CBR + CMP1CBR + Timerx Compare 1 Compound Register + 0x20 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition value (aliased from HRTIM_REPx register) + 16 + 8 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP2BR + CMP2BR + Timerx Compare 2 Register + 0x24 + 0x20 + read-write + 0x00000000 + + + CMP2x + Timerx Compare 2 value + 0 + 16 + + + + + CMP3BR + CMP3BR + Timerx Compare 3 Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CMP3x + Timerx Compare 3 value + 0 + 16 + + + + + CMP4BR + CMP4BR + Timerx Compare 4 Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CMP4x + Timerx Compare 4 value + 0 + 16 + + + + + CPT1BR + CPT1BR + Timerx Capture 1 Register + 0x30 + 0x20 + read-only + 0x00000000 + + + CPT1x + Timerx Capture 1 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + CPT2BR + CPT2BR + Timerx Capture 2 Register + 0x34 + 0x20 + read-only + 0x00000000 + + + CPT2x + Timerx Capture 2 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + DTBR + DTBR + Timerx Deadtime Register + 0x38 + 0x20 + read-write + 0x00000000 + + + DTFLKx + Deadtime Falling Lock + 31 + 1 + + + DTFSLKx + Deadtime Falling Sign Lock + 30 + 1 + + + SDTFx + Sign Deadtime Falling value + 25 + 1 + + + DTFx + Deadtime Falling value + 16 + 9 + + + DTRLKx + Deadtime Rising Lock + 15 + 1 + + + DTRSLKx + Deadtime Rising Sign Lock + 14 + 1 + + + DTPRSC + Deadtime Prescaler + 10 + 3 + + + SDTRx + Sign Deadtime Rising value + 9 + 1 + + + DTRx + Deadtime Rising value + 0 + 9 + + + + + SETB1R + SETB1R + Timerx Output1 Set Register + 0x3C + 0x20 + read-write + 0x00000000 + + + UPDATE + Registers update (transfer preload to active) + 31 + 1 + + + EXTEVNT10 + External Event 10 + 30 + 1 + + + EXTEVNT9 + External Event 9 + 29 + 1 + + + EXTEVNT8 + External Event 8 + 28 + 1 + + + EXTEVNT7 + External Event 7 + 27 + 1 + + + EXTEVNT6 + External Event 6 + 26 + 1 + + + EXTEVNT5 + External Event 5 + 25 + 1 + + + EXTEVNT4 + External Event 4 + 24 + 1 + + + EXTEVNT3 + External Event 3 + 23 + 1 + + + EXTEVNT2 + External Event 2 + 22 + 1 + + + EXTEVNT1 + External Event 1 + 21 + 1 + + + TIMEVNT9 + Timer Event 9 + 20 + 1 + + + TIMEVNT8 + Timer Event 8 + 19 + 1 + + + TIMEVNT7 + Timer Event 7 + 18 + 1 + + + TIMEVNT6 + Timer Event 6 + 17 + 1 + + + TIMEVNT5 + Timer Event 5 + 16 + 1 + + + TIMEVNT4 + Timer Event 4 + 15 + 1 + + + TIMEVNT3 + Timer Event 3 + 14 + 1 + + + TIMEVNT2 + Timer Event 2 + 13 + 1 + + + TIMEVNT1 + Timer Event 1 + 12 + 1 + + + MSTCMP4 + Master Compare 4 + 11 + 1 + + + MSTCMP3 + Master Compare 3 + 10 + 1 + + + MSTCMP2 + Master Compare 2 + 9 + 1 + + + MSTCMP1 + Master Compare 1 + 8 + 1 + + + MSTPER + Master Period + 7 + 1 + + + CMP4 + Timer A compare 4 + 6 + 1 + + + CMP3 + Timer A compare 3 + 5 + 1 + + + CMP2 + Timer A compare 2 + 4 + 1 + + + CMP1 + Timer A compare 1 + 3 + 1 + + + PER + Timer A Period + 2 + 1 + + + RESYNC + Timer A resynchronizaton + 1 + 1 + + + SST + Software Set trigger + 0 + 1 + + + + + RSTB1R + RSTB1R + Timerx Output1 Reset Register + 0x40 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + SETB2R + SETB2R + Timerx Output2 Set Register + 0x44 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SST + SST + 0 + 1 + + + + + RSTB2R + RSTB2R + Timerx Output2 Reset Register + 0x48 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + EEFBR1 + EEFBR1 + Timerx External Event Filtering Register 1 + 0x4C + 0x20 + read-write + 0x00000000 + + + EE5FLTR + External Event 5 filter + 25 + 4 + + + EE5LTCH + External Event 5 latch + 24 + 1 + + + EE4FLTR + External Event 4 filter + 19 + 4 + + + EE4LTCH + External Event 4 latch + 18 + 1 + + + EE3FLTR + External Event 3 filter + 13 + 4 + + + EE3LTCH + External Event 3 latch + 12 + 1 + + + EE2FLTR + External Event 2 filter + 7 + 4 + + + EE2LTCH + External Event 2 latch + 6 + 1 + + + EE1FLTR + External Event 1 filter + 1 + 4 + + + EE1LTCH + External Event 1 latch + 0 + 1 + + + + + EEFBR2 + EEFBR2 + Timerx External Event Filtering Register 2 + 0x50 + 0x20 + read-write + 0x00000000 + + + EE10FLTR + External Event 10 filter + 25 + 4 + + + EE10LTCH + External Event 10 latch + 24 + 1 + + + EE9FLTR + External Event 9 filter + 19 + 4 + + + EE9LTCH + External Event 9 latch + 18 + 1 + + + EE8FLTR + External Event 8 filter + 13 + 4 + + + EE8LTCH + External Event 8 latch + 12 + 1 + + + EE7FLTR + External Event 7 filter + 7 + 4 + + + EE7LTCH + External Event 7 latch + 6 + 1 + + + EE6FLTR + External Event 6 filter + 1 + 4 + + + EE6LTCH + External Event 6 latch + 0 + 1 + + + + + RSTBR + RSTBR + TimerA Reset Register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIMFCPM2 + Timer F Compare 2 + 31 + 1 + + + TIMECMP4 + Timer E Compare 4 + 30 + 1 + + + TIMECMP2 + Timer E Compare 2 + 29 + 1 + + + TIMECMP1 + Timer E Compare 1 + 28 + 1 + + + TIMDCMP4 + Timer D Compare 4 + 27 + 1 + + + TIMDCMP2 + Timer D Compare 2 + 26 + 1 + + + TIMDCMP1 + Timer D Compare 1 + 25 + 1 + + + TIMCCMP4 + Timer C Compare 4 + 24 + 1 + + + TIMCCMP2 + Timer C Compare 2 + 23 + 1 + + + TIMCCMP1 + Timer C Compare 1 + 22 + 1 + + + TIMACMP4 + Timer A Compare 4 + 21 + 1 + + + TIMACMP2 + Timer A Compare 2 + 20 + 1 + + + TIMACMP1 + Timer A Compare 1 + 19 + 1 + + + EXTEVNT10 + External Event 10 + 18 + 1 + + + EXTEVNT9 + External Event 9 + 17 + 1 + + + EXTEVNT8 + External Event 8 + 16 + 1 + + + EXTEVNT7 + External Event 7 + 15 + 1 + + + EXTEVNT6 + External Event 6 + 14 + 1 + + + EXTEVNT5 + External Event 5 + 13 + 1 + + + EXTEVNT4 + External Event 4 + 12 + 1 + + + EXTEVNT3 + External Event 3 + 11 + 1 + + + EXTEVNT2 + External Event 2 + 10 + 1 + + + EXTEVNT1 + External Event 1 + 9 + 1 + + + MSTCMP4 + Master compare 4 + 8 + 1 + + + MSTCMP3 + Master compare 3 + 7 + 1 + + + MSTCMP2 + Master compare 2 + 6 + 1 + + + MSTCMP1 + Master compare 1 + 5 + 1 + + + MSTPER + Master timer Period + 4 + 1 + + + CMP4 + Timer A compare 4 reset + 3 + 1 + + + CMP2 + Timer A compare 2 reset + 2 + 1 + + + UPDT + Timer A Update reset + 1 + 1 + + + TIMFCMP1 + Timer A Update reset + 0 + 1 + + + + + CHPBR + CHPBR + Timerx Chopper Register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRTPW + STRTPW + 7 + 4 + + + CHPDTY + Timerx chopper duty cycle value + 4 + 3 + + + CHPFRQ + Timerx carrier frequency value + 0 + 4 + + + + + CPT1BCR + CPT1BCR + Timerx Capture 2 Control Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TFCMP2 + TFCMP2 + 19 + 1 + + + TFCMP1 + TFCMP1 + 18 + 1 + + + TF1RST + TF1RST + 17 + 1 + + + TF1SET + TF1SET + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + CPT2BCR + CPT2BCR + CPT2xCR + 0x60 + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TFCMP2 + TFCMP2 + 19 + 1 + + + TFCMP1 + TFCMP1 + 18 + 1 + + + TF1RST + TF1RST + 17 + 1 + + + TF1SET + TF1SET + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + OUTBR + OUTBR + Timerx Output Register + 0x64 + 0x20 + read-write + 0x00000000 + + + DIDL2 + Output 2 Deadtime upon burst mode Idle entry + 23 + 1 + + + CHP2 + Output 2 Chopper enable + 22 + 1 + + + FAULT2 + Output 2 Fault state + 20 + 2 + + + IDLES2 + Output 2 Idle State + 19 + 1 + + + IDLEM2 + Output 2 Idle mode + 18 + 1 + + + POL2 + Output 2 polarity + 17 + 1 + + + BIAR + Balanced Idle Automatic Resume + 14 + 1 + + + DLYPRT + Delayed Protection + 10 + 3 + + + DLYPRTEN + Delayed Protection Enable + 9 + 1 + + + DTEN + Deadtime enable + 8 + 1 + + + DIDL1 + Output 1 Deadtime upon burst mode Idle entry + 7 + 1 + + + CHP1 + Output 1 Chopper enable + 6 + 1 + + + FAULT1 + Output 1 Fault state + 4 + 2 + + + IDLES1 + Output 1 Idle State + 3 + 1 + + + IDLEM1 + Output 1 Idle mode + 2 + 1 + + + POL1 + Output 1 polarity + 1 + 1 + + + + + FLTBR + FLTBR + Timerx Fault Register + 0x68 + 0x20 + read-write + 0x00000000 + + + FLTLCK + Fault sources Lock + 31 + 1 + + + FLT6EN + Fault 6 enable + 5 + 1 + + + FLT5EN + Fault 5 enable + 4 + 1 + + + FLT4EN + Fault 4 enable + 3 + 1 + + + FLT3EN + Fault 3 enable + 2 + 1 + + + FLT2EN + Fault 2 enable + 1 + 1 + + + FLT1EN + Fault 1 enable + 0 + 1 + + + + + TIMBCR2 + TIMBCR2 + HRTIM Timerx Control Register 2 + 0x6C + 0x20 + read-write + 0x00000000 + + + TRGHLF + Triggered-half mode + 20 + 1 + + + GTCMP3 + Greater than Compare 3 PWM mode + 17 + 1 + + + GTCMP1 + Greater than Compare 1 PWM mode + 16 + 1 + + + FEROM + Fault and Event Roll-Over Mode + 14 + 2 + + + BMROM + Burst Mode Roll-Over Mode + 12 + 2 + + + ADROM + ADC Roll-Over Mode + 10 + 2 + + + OUTROM + Output Roll-Over Mode + 8 + 2 + + + ROM + Roll-Over Mode + 6 + 2 + + + UDM + Up-Down Mode + 4 + 1 + + + DCDR + Dual Channel DAC Reset trigger + 2 + 1 + + + DCDS + Dual Channel DAC Step trigger + 1 + 1 + + + DCDE + Dual Channel DAC trigger enable + 0 + 1 + + + + + BEEFR3 + BEEFR3 + HRTIM Timerx External Event Filtering Register 3 + 0x70 + 0x20 + read-write + 0x00000000 + + + EEVACNT + External Event A counter + 8 + 6 + + + EEVASEL + External Event A Selection + 4 + 4 + + + EEVARSTM + External Event A Reset Mode + 2 + 1 + + + EEVACRES + External Event A Counter Reset + 1 + 1 + + + EEVACE + External Event A Counter Enable + 0 + 1 + + + + + + + HRTIM_TIMC + High Resolution Timer: TIMC + HRTIM + 0x40016980 + + 0x0 + 0x80 + registers + + + HRTIM_TIMC_IRQn + HRTIM_TIMC_IRQn + 70 + + + + TIMCCR + TIMCCR + Timerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + UPDGAT + Update Gating + 28 + 4 + + + PREEN + Preload enable + 27 + 1 + + + DACSYNC + AC Synchronization + 25 + 2 + + + MSTU + Master Timer update + 24 + 1 + + + TEU + TEU + 23 + 1 + + + TDU + TDU + 22 + 1 + + + TBU + TBU + 20 + 1 + + + TAU + TAU + 19 + 1 + + + TxRSTU + Timerx reset update + 18 + 1 + + + TxREPU + Timer x Repetition update + 17 + 1 + + + TFU + TFU + 16 + 1 + + + DELCMP4 + Delayed CMP4 mode + 14 + 2 + + + DELCMP2 + Delayed CMP2 mode + 12 + 2 + + + SYNCSTRTx + Synchronization Starts Timer x + 11 + 1 + + + SYNCRSTx + Synchronization Resets Timer x + 10 + 1 + + + RSYNCU + Re-Synchronized Update + 9 + 1 + + + INTLVD + Interleaved mode + 7 + 2 + + + PSHPLL + Push-Pull mode enable + 6 + 1 + + + HALF + Half mode enable + 5 + 1 + + + RETRIG + Re-triggerable mode + 4 + 1 + + + CONT + Continuous mode + 3 + 1 + + + CK_PSCx + HRTIM Timer x Clock prescaler + 0 + 3 + + + + + TIMCISR + TIMCISR + Timerx Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + O2CPY + Output 2 Copy + 21 + 1 + + + O1CPY + Output 1 Copy + 20 + 1 + + + O2STAT + Output 2 State + 19 + 1 + + + O1STAT + Output 1 State + 18 + 1 + + + IPPSTAT + Idle Push Pull Status + 17 + 1 + + + CPPSTAT + Current Push Pull Status + 16 + 1 + + + DLYPRT + Delayed Protection Flag + 14 + 1 + + + RST + Reset Interrupt Flag + 13 + 1 + + + RSTx2 + Output 2 Reset Interrupt Flag + 12 + 1 + + + SETx2 + Output 2 Set Interrupt Flag + 11 + 1 + + + RSTx1 + Output 1 Reset Interrupt Flag + 10 + 1 + + + SETx1 + Output 1 Set Interrupt Flag + 9 + 1 + + + CPT2 + Capture2 Interrupt Flag + 8 + 1 + + + CPT1 + Capture1 Interrupt Flag + 7 + 1 + + + UPD + Update Interrupt Flag + 6 + 1 + + + REP + Repetition Interrupt Flag + 4 + 1 + + + CMP4 + Compare 4 Interrupt Flag + 3 + 1 + + + CMP3 + Compare 3 Interrupt Flag + 2 + 1 + + + CMP2 + Compare 2 Interrupt Flag + 1 + 1 + + + CMP1 + Compare 1 Interrupt Flag + 0 + 1 + + + + + TIMCICR + TIMCICR + Timerx Interrupt Clear Register + 0x8 + 0x20 + write-only + 0x00000000 + + + DLYPRTC + Delayed Protection Flag Clear + 14 + 1 + + + RSTC + Reset Interrupt flag Clear + 13 + 1 + + + RSTx2C + Output 2 Reset flag Clear + 12 + 1 + + + SET2xC + Output 2 Set flag Clear + 11 + 1 + + + RSTx1C + Output 1 Reset flag Clear + 10 + 1 + + + SET1xC + Output 1 Set flag Clear + 9 + 1 + + + CPT2C + Capture2 Interrupt flag Clear + 8 + 1 + + + CPT1C + Capture1 Interrupt flag Clear + 7 + 1 + + + UPDC + Update Interrupt flag Clear + 6 + 1 + + + REPC + Repetition Interrupt flag Clear + 4 + 1 + + + CMP4C + Compare 4 Interrupt flag Clear + 3 + 1 + + + CMP3C + Compare 3 Interrupt flag Clear + 2 + 1 + + + CMP2C + Compare 2 Interrupt flag Clear + 1 + 1 + + + CMP1C + Compare 1 Interrupt flag Clear + 0 + 1 + + + + + TIMCDIER + TIMCDIER + TIMxDIER + 0xC + 0x20 + read-write + 0x00000000 + + + DLYPRTDE + DLYPRTDE + 30 + 1 + + + RSTDE + RSTDE + 29 + 1 + + + RSTx2DE + RSTx2DE + 28 + 1 + + + SETx2DE + SETx2DE + 27 + 1 + + + RSTx1DE + RSTx1DE + 26 + 1 + + + SET1xDE + SET1xDE + 25 + 1 + + + CPT2DE + CPT2DE + 24 + 1 + + + CPT1DE + CPT1DE + 23 + 1 + + + UPDDE + UPDDE + 22 + 1 + + + REPDE + REPDE + 20 + 1 + + + CMP4DE + CMP4DE + 19 + 1 + + + CMP3DE + CMP3DE + 18 + 1 + + + CMP2DE + CMP2DE + 17 + 1 + + + CMP1DE + CMP1DE + 16 + 1 + + + DLYPRTIE + DLYPRTIE + 14 + 1 + + + RSTIE + RSTIE + 13 + 1 + + + RSTx2IE + RSTx2IE + 12 + 1 + + + SETx2IE + SETx2IE + 11 + 1 + + + RSTx1IE + RSTx1IE + 10 + 1 + + + SET1xIE + SET1xIE + 9 + 1 + + + CPT2IE + CPT2IE + 8 + 1 + + + CPT1IE + CPT1IE + 7 + 1 + + + UPDIE + UPDIE + 6 + 1 + + + REPIE + REPIE + 4 + 1 + + + CMP4IE + CMP4IE + 3 + 1 + + + CMP3IE + CMP3IE + 2 + 1 + + + CMP2IE + CMP2IE + 1 + 1 + + + CMP1IE + CMP1IE + 0 + 1 + + + + + CNTCR + CNTCR + Timerx Counter Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTx + Timerx Counter value + 0 + 16 + + + + + PERCR + PERCR + Timerx Period Register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + PERx + Timerx Period value + 0 + 16 + + + + + REPCR + REPCR + Timerx Repetition Register + 0x18 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition counter value + 0 + 8 + + + + + CMP1CR + CMP1CR + Timerx Compare 1 Register + 0x1C + 0x20 + read-write + 0x00000000 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP1CCR + CMP1CCR + Timerx Compare 1 Compound Register + 0x20 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition value (aliased from HRTIM_REPx register) + 16 + 8 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP2CR + CMP2CR + Timerx Compare 2 Register + 0x24 + 0x20 + read-write + 0x00000000 + + + CMP2x + Timerx Compare 2 value + 0 + 16 + + + + + CMP3CR + CMP3CR + Timerx Compare 3 Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CMP3x + Timerx Compare 3 value + 0 + 16 + + + + + CMP4CR + CMP4CR + Timerx Compare 4 Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CMP4x + Timerx Compare 4 value + 0 + 16 + + + + + CPT1CR + CPT1CR + Timerx Capture 1 Register + 0x30 + 0x20 + read-only + 0x00000000 + + + CPT1x + Timerx Capture 1 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + CPT2CR + CPT2CR + Timerx Capture 2 Register + 0x34 + 0x20 + read-only + 0x00000000 + + + CPT2x + Timerx Capture 2 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + DTCR + DTCR + Timerx Deadtime Register + 0x38 + 0x20 + read-write + 0x00000000 + + + DTFLKx + Deadtime Falling Lock + 31 + 1 + + + DTFSLKx + Deadtime Falling Sign Lock + 30 + 1 + + + SDTFx + Sign Deadtime Falling value + 25 + 1 + + + DTFx + Deadtime Falling value + 16 + 9 + + + DTRLKx + Deadtime Rising Lock + 15 + 1 + + + DTRSLKx + Deadtime Rising Sign Lock + 14 + 1 + + + DTPRSC + Deadtime Prescaler + 10 + 3 + + + SDTRx + Sign Deadtime Rising value + 9 + 1 + + + DTRx + Deadtime Rising value + 0 + 9 + + + + + SETC1R + SETC1R + Timerx Output1 Set Register + 0x3C + 0x20 + read-write + 0x00000000 + + + UPDATE + Registers update (transfer preload to active) + 31 + 1 + + + EXTEVNT10 + External Event 10 + 30 + 1 + + + EXTEVNT9 + External Event 9 + 29 + 1 + + + EXTEVNT8 + External Event 8 + 28 + 1 + + + EXTEVNT7 + External Event 7 + 27 + 1 + + + EXTEVNT6 + External Event 6 + 26 + 1 + + + EXTEVNT5 + External Event 5 + 25 + 1 + + + EXTEVNT4 + External Event 4 + 24 + 1 + + + EXTEVNT3 + External Event 3 + 23 + 1 + + + EXTEVNT2 + External Event 2 + 22 + 1 + + + EXTEVNT1 + External Event 1 + 21 + 1 + + + TIMEVNT9 + Timer Event 9 + 20 + 1 + + + TIMEVNT8 + Timer Event 8 + 19 + 1 + + + TIMEVNT7 + Timer Event 7 + 18 + 1 + + + TIMEVNT6 + Timer Event 6 + 17 + 1 + + + TIMEVNT5 + Timer Event 5 + 16 + 1 + + + TIMEVNT4 + Timer Event 4 + 15 + 1 + + + TIMEVNT3 + Timer Event 3 + 14 + 1 + + + TIMEVNT2 + Timer Event 2 + 13 + 1 + + + TIMEVNT1 + Timer Event 1 + 12 + 1 + + + MSTCMP4 + Master Compare 4 + 11 + 1 + + + MSTCMP3 + Master Compare 3 + 10 + 1 + + + MSTCMP2 + Master Compare 2 + 9 + 1 + + + MSTCMP1 + Master Compare 1 + 8 + 1 + + + MSTPER + Master Period + 7 + 1 + + + CMP4 + Timer A compare 4 + 6 + 1 + + + CMP3 + Timer A compare 3 + 5 + 1 + + + CMP2 + Timer A compare 2 + 4 + 1 + + + CMP1 + Timer A compare 1 + 3 + 1 + + + PER + Timer A Period + 2 + 1 + + + RESYNC + Timer A resynchronizaton + 1 + 1 + + + SST + Software Set trigger + 0 + 1 + + + + + RSTC1R + RSTC1R + Timerx Output1 Reset Register + 0x40 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + SETC2R + SETC2R + Timerx Output2 Set Register + 0x44 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SST + SST + 0 + 1 + + + + + RSTC2R + RSTC2R + Timerx Output2 Reset Register + 0x48 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + EEFCR1 + EEFCR1 + Timerx External Event Filtering Register 1 + 0x4C + 0x20 + read-write + 0x00000000 + + + EE5FLTR + External Event 5 filter + 25 + 4 + + + EE5LTCH + External Event 5 latch + 24 + 1 + + + EE4FLTR + External Event 4 filter + 19 + 4 + + + EE4LTCH + External Event 4 latch + 18 + 1 + + + EE3FLTR + External Event 3 filter + 13 + 4 + + + EE3LTCH + External Event 3 latch + 12 + 1 + + + EE2FLTR + External Event 2 filter + 7 + 4 + + + EE2LTCH + External Event 2 latch + 6 + 1 + + + EE1FLTR + External Event 1 filter + 1 + 4 + + + EE1LTCH + External Event 1 latch + 0 + 1 + + + + + EEFCR2 + EEFCR2 + Timerx External Event Filtering Register 2 + 0x50 + 0x20 + read-write + 0x00000000 + + + EE10FLTR + External Event 10 filter + 25 + 4 + + + EE10LTCH + External Event 10 latch + 24 + 1 + + + EE9FLTR + External Event 9 filter + 19 + 4 + + + EE9LTCH + External Event 9 latch + 18 + 1 + + + EE8FLTR + External Event 8 filter + 13 + 4 + + + EE8LTCH + External Event 8 latch + 12 + 1 + + + EE7FLTR + External Event 7 filter + 7 + 4 + + + EE7LTCH + External Event 7 latch + 6 + 1 + + + EE6FLTR + External Event 6 filter + 1 + 4 + + + EE6LTCH + External Event 6 latch + 0 + 1 + + + + + RSTCR + RSTCR + TimerA Reset Register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIMFCPM2 + Timer F Compare 2 + 31 + 1 + + + TIMECMP4 + Timer E Compare 4 + 30 + 1 + + + TIMECMP2 + Timer E Compare 2 + 29 + 1 + + + TIMECMP1 + Timer E Compare 1 + 28 + 1 + + + TIMDCMP4 + Timer D Compare 4 + 27 + 1 + + + TIMDCMP2 + Timer D Compare 2 + 26 + 1 + + + TIMDCMP1 + Timer D Compare 1 + 25 + 1 + + + TIMBCMP4 + Timer B Compare 4 + 24 + 1 + + + TIMBCMP2 + Timer B Compare 2 + 23 + 1 + + + TIMBCMP1 + Timer B Compare 1 + 22 + 1 + + + TIMACMP4 + Timer A Compare 4 + 21 + 1 + + + TIMACMP2 + Timer A Compare 2 + 20 + 1 + + + TIMACMP1 + Timer A Compare 1 + 19 + 1 + + + EXTEVNT10 + External Event 10 + 18 + 1 + + + EXTEVNT9 + External Event 9 + 17 + 1 + + + EXTEVNT8 + External Event 8 + 16 + 1 + + + EXTEVNT7 + External Event 7 + 15 + 1 + + + EXTEVNT6 + External Event 6 + 14 + 1 + + + EXTEVNT5 + External Event 5 + 13 + 1 + + + EXTEVNT4 + External Event 4 + 12 + 1 + + + EXTEVNT3 + External Event 3 + 11 + 1 + + + EXTEVNT2 + External Event 2 + 10 + 1 + + + EXTEVNT1 + External Event 1 + 9 + 1 + + + MSTCMP4 + Master compare 4 + 8 + 1 + + + MSTCMP3 + Master compare 3 + 7 + 1 + + + MSTCMP2 + Master compare 2 + 6 + 1 + + + MSTCMP1 + Master compare 1 + 5 + 1 + + + MSTPER + Master timer Period + 4 + 1 + + + CMP4 + Timer A compare 4 reset + 3 + 1 + + + CMP2 + Timer A compare 2 reset + 2 + 1 + + + UPDT + Timer A Update reset + 1 + 1 + + + TIMFCMP1 + Timer A Update reset + 0 + 1 + + + + + CHPCR + CHPCR + Timerx Chopper Register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRTPW + STRTPW + 7 + 4 + + + CHPDTY + Timerx chopper duty cycle value + 4 + 3 + + + CHPFRQ + Timerx carrier frequency value + 0 + 4 + + + + + CPT1CCR + CPT1CCR + Timerx Capture 2 Control Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TFCMP2 + TFCMP2 + 23 + 1 + + + TFCMP1 + TFCMP1 + 22 + 1 + + + TF1RST + TF1RST + 21 + 1 + + + TF1SET + TF1SET + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + CPT2CCR + CPT2CCR + CPT2xCR + 0x60 + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TF1CMP2 + TF1CMP2 + 23 + 1 + + + TF1CMP1 + TF1CMP1 + 22 + 1 + + + TF1RST + TF1RST + 21 + 1 + + + TF1SET + TF1SET + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + OUTCR + OUTCR + Timerx Output Register + 0x64 + 0x20 + read-write + 0x00000000 + + + DIDL2 + Output 2 Deadtime upon burst mode Idle entry + 23 + 1 + + + CHP2 + Output 2 Chopper enable + 22 + 1 + + + FAULT2 + Output 2 Fault state + 20 + 2 + + + IDLES2 + Output 2 Idle State + 19 + 1 + + + IDLEM2 + Output 2 Idle mode + 18 + 1 + + + POL2 + Output 2 polarity + 17 + 1 + + + BIAR + Balanced Idle Automatic Resume + 14 + 1 + + + DLYPRT + Delayed Protection + 10 + 3 + + + DLYPRTEN + Delayed Protection Enable + 9 + 1 + + + DTEN + Deadtime enable + 8 + 1 + + + DIDL1 + Output 1 Deadtime upon burst mode Idle entry + 7 + 1 + + + CHP1 + Output 1 Chopper enable + 6 + 1 + + + FAULT1 + Output 1 Fault state + 4 + 2 + + + IDLES1 + Output 1 Idle State + 3 + 1 + + + IDLEM1 + Output 1 Idle mode + 2 + 1 + + + POL1 + Output 1 polarity + 1 + 1 + + + + + FLTCR + FLTCR + Timerx Fault Register + 0x68 + 0x20 + read-write + 0x00000000 + + + FLTLCK + Fault sources Lock + 31 + 1 + + + FLT6EN + Fault 6 enable + 5 + 1 + + + FLT5EN + Fault 5 enable + 4 + 1 + + + FLT4EN + Fault 4 enable + 3 + 1 + + + FLT3EN + Fault 3 enable + 2 + 1 + + + FLT2EN + Fault 2 enable + 1 + 1 + + + FLT1EN + Fault 1 enable + 0 + 1 + + + + + TIMCCR2 + TIMCCR2 + HRTIM Timerx Control Register 2 + 0x6C + 0x20 + read-write + 0x00000000 + + + TRGHLF + Triggered-half mode + 20 + 1 + + + GTCMP3 + Greater than Compare 3 PWM mode + 17 + 1 + + + GTCMP1 + Greater than Compare 1 PWM mode + 16 + 1 + + + FEROM + Fault and Event Roll-Over Mode + 14 + 2 + + + BMROM + Burst Mode Roll-Over Mode + 12 + 2 + + + ADROM + ADC Roll-Over Mode + 10 + 2 + + + OUTROM + Output Roll-Over Mode + 8 + 2 + + + ROM + Roll-Over Mode + 6 + 2 + + + UDM + Up-Down Mode + 4 + 1 + + + DCDR + Dual Channel DAC Reset trigger + 2 + 1 + + + DCDS + Dual Channel DAC Step trigger + 1 + 1 + + + DCDE + Dual Channel DAC trigger enable + 0 + 1 + + + + + CEEFR3 + CEEFR3 + HRTIM Timerx External Event Filtering Register 3 + 0x70 + 0x20 + read-write + 0x00000000 + + + EEVACNT + External Event A counter + 8 + 6 + + + EEVASEL + External Event A Selection + 4 + 4 + + + EEVARSTM + External Event A Reset Mode + 2 + 1 + + + EEVACRES + External Event A Counter Reset + 1 + 1 + + + EEVACE + External Event A Counter Enable + 0 + 1 + + + + + + + HRTIM_TIMD + High Resolution Timer: TIMD + HRTIM + 0x40016A00 + + 0x0 + 0x80 + registers + + + HRTIM_TIMD_IRQn + HRTIM_TIMD_IRQn + 71 + + + + TIMDCR + TIMDCR + Timerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + UPDGAT + Update Gating + 28 + 4 + + + PREEN + Preload enable + 27 + 1 + + + DACSYNC + AC Synchronization + 25 + 2 + + + MSTU + Master Timer update + 24 + 1 + + + TEU + TEU + 23 + 1 + + + TCU + TCU + 21 + 1 + + + TBU + TBU + 20 + 1 + + + TAU + TAU + 19 + 1 + + + TxRSTU + Timerx reset update + 18 + 1 + + + TxREPU + Timer x Repetition update + 17 + 1 + + + TFU + TFU + 16 + 1 + + + DELCMP4 + Delayed CMP4 mode + 14 + 2 + + + DELCMP2 + Delayed CMP2 mode + 12 + 2 + + + SYNCSTRTx + Synchronization Starts Timer x + 11 + 1 + + + SYNCRSTx + Synchronization Resets Timer x + 10 + 1 + + + RSYNCU + Re-Synchronized Update + 9 + 1 + + + INTLVD + Interleaved mode + 7 + 2 + + + PSHPLL + Push-Pull mode enable + 6 + 1 + + + HALF + Half mode enable + 5 + 1 + + + RETRIG + Re-triggerable mode + 4 + 1 + + + CONT + Continuous mode + 3 + 1 + + + CK_PSCx + HRTIM Timer x Clock prescaler + 0 + 3 + + + + + TIMDISR + TIMDISR + Timerx Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + O2CPY + Output 2 Copy + 21 + 1 + + + O1CPY + Output 1 Copy + 20 + 1 + + + O2STAT + Output 2 State + 19 + 1 + + + O1STAT + Output 1 State + 18 + 1 + + + IPPSTAT + Idle Push Pull Status + 17 + 1 + + + CPPSTAT + Current Push Pull Status + 16 + 1 + + + DLYPRT + Delayed Protection Flag + 14 + 1 + + + RST + Reset Interrupt Flag + 13 + 1 + + + RSTx2 + Output 2 Reset Interrupt Flag + 12 + 1 + + + SETx2 + Output 2 Set Interrupt Flag + 11 + 1 + + + RSTx1 + Output 1 Reset Interrupt Flag + 10 + 1 + + + SETx1 + Output 1 Set Interrupt Flag + 9 + 1 + + + CPT2 + Capture2 Interrupt Flag + 8 + 1 + + + CPT1 + Capture1 Interrupt Flag + 7 + 1 + + + UPD + Update Interrupt Flag + 6 + 1 + + + REP + Repetition Interrupt Flag + 4 + 1 + + + CMP4 + Compare 4 Interrupt Flag + 3 + 1 + + + CMP3 + Compare 3 Interrupt Flag + 2 + 1 + + + CMP2 + Compare 2 Interrupt Flag + 1 + 1 + + + CMP1 + Compare 1 Interrupt Flag + 0 + 1 + + + + + TIMDICR + TIMDICR + Timerx Interrupt Clear Register + 0x8 + 0x20 + write-only + 0x00000000 + + + DLYPRTC + Delayed Protection Flag Clear + 14 + 1 + + + RSTC + Reset Interrupt flag Clear + 13 + 1 + + + RSTx2C + Output 2 Reset flag Clear + 12 + 1 + + + SET2xC + Output 2 Set flag Clear + 11 + 1 + + + RSTx1C + Output 1 Reset flag Clear + 10 + 1 + + + SET1xC + Output 1 Set flag Clear + 9 + 1 + + + CPT2C + Capture2 Interrupt flag Clear + 8 + 1 + + + CPT1C + Capture1 Interrupt flag Clear + 7 + 1 + + + UPDC + Update Interrupt flag Clear + 6 + 1 + + + REPC + Repetition Interrupt flag Clear + 4 + 1 + + + CMP4C + Compare 4 Interrupt flag Clear + 3 + 1 + + + CMP3C + Compare 3 Interrupt flag Clear + 2 + 1 + + + CMP2C + Compare 2 Interrupt flag Clear + 1 + 1 + + + CMP1C + Compare 1 Interrupt flag Clear + 0 + 1 + + + + + TIMDDIER + TIMDDIER + TIMxDIER + 0xC + 0x20 + read-write + 0x00000000 + + + DLYPRTDE + DLYPRTDE + 30 + 1 + + + RSTDE + RSTDE + 29 + 1 + + + RSTx2DE + RSTx2DE + 28 + 1 + + + SETx2DE + SETx2DE + 27 + 1 + + + RSTx1DE + RSTx1DE + 26 + 1 + + + SET1xDE + SET1xDE + 25 + 1 + + + CPT2DE + CPT2DE + 24 + 1 + + + CPT1DE + CPT1DE + 23 + 1 + + + UPDDE + UPDDE + 22 + 1 + + + REPDE + REPDE + 20 + 1 + + + CMP4DE + CMP4DE + 19 + 1 + + + CMP3DE + CMP3DE + 18 + 1 + + + CMP2DE + CMP2DE + 17 + 1 + + + CMP1DE + CMP1DE + 16 + 1 + + + DLYPRTIE + DLYPRTIE + 14 + 1 + + + RSTIE + RSTIE + 13 + 1 + + + RSTx2IE + RSTx2IE + 12 + 1 + + + SETx2IE + SETx2IE + 11 + 1 + + + RSTx1IE + RSTx1IE + 10 + 1 + + + SET1xIE + SET1xIE + 9 + 1 + + + CPT2IE + CPT2IE + 8 + 1 + + + CPT1IE + CPT1IE + 7 + 1 + + + UPDIE + UPDIE + 6 + 1 + + + REPIE + REPIE + 4 + 1 + + + CMP4IE + CMP4IE + 3 + 1 + + + CMP3IE + CMP3IE + 2 + 1 + + + CMP2IE + CMP2IE + 1 + 1 + + + CMP1IE + CMP1IE + 0 + 1 + + + + + CNTDR + CNTDR + Timerx Counter Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTx + Timerx Counter value + 0 + 16 + + + + + PERDR + PERDR + Timerx Period Register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + PERx + Timerx Period value + 0 + 16 + + + + + REPDR + REPDR + Timerx Repetition Register + 0x18 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition counter value + 0 + 8 + + + + + CMP1DR + CMP1DR + Timerx Compare 1 Register + 0x1C + 0x20 + read-write + 0x00000000 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP1CDR + CMP1CDR + Timerx Compare 1 Compound Register + 0x20 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition value (aliased from HRTIM_REPx register) + 16 + 8 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP2DR + CMP2DR + Timerx Compare 2 Register + 0x24 + 0x20 + read-write + 0x00000000 + + + CMP2x + Timerx Compare 2 value + 0 + 16 + + + + + CMP3DR + CMP3DR + Timerx Compare 3 Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CMP3x + Timerx Compare 3 value + 0 + 16 + + + + + CMP4DR + CMP4DR + Timerx Compare 4 Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CMP4x + Timerx Compare 4 value + 0 + 16 + + + + + CPT1DR + CPT1DR + Timerx Capture 1 Register + 0x30 + 0x20 + read-only + 0x00000000 + + + CPT1x + Timerx Capture 1 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + CPT2DR + CPT2DR + Timerx Capture 2 Register + 0x34 + 0x20 + read-only + 0x00000000 + + + CPT2x + Timerx Capture 2 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + DTDR + DTDR + Timerx Deadtime Register + 0x38 + 0x20 + read-write + 0x00000000 + + + DTFLKx + Deadtime Falling Lock + 31 + 1 + + + DTFSLKx + Deadtime Falling Sign Lock + 30 + 1 + + + SDTFx + Sign Deadtime Falling value + 25 + 1 + + + DTFx + Deadtime Falling value + 16 + 9 + + + DTRLKx + Deadtime Rising Lock + 15 + 1 + + + DTRSLKx + Deadtime Rising Sign Lock + 14 + 1 + + + DTPRSC + Deadtime Prescaler + 10 + 3 + + + SDTRx + Sign Deadtime Rising value + 9 + 1 + + + DTRx + Deadtime Rising value + 0 + 9 + + + + + SETD1R + SETD1R + Timerx Output1 Set Register + 0x3C + 0x20 + read-write + 0x00000000 + + + UPDATE + Registers update (transfer preload to active) + 31 + 1 + + + EXTEVNT10 + External Event 10 + 30 + 1 + + + EXTEVNT9 + External Event 9 + 29 + 1 + + + EXTEVNT8 + External Event 8 + 28 + 1 + + + EXTEVNT7 + External Event 7 + 27 + 1 + + + EXTEVNT6 + External Event 6 + 26 + 1 + + + EXTEVNT5 + External Event 5 + 25 + 1 + + + EXTEVNT4 + External Event 4 + 24 + 1 + + + EXTEVNT3 + External Event 3 + 23 + 1 + + + EXTEVNT2 + External Event 2 + 22 + 1 + + + EXTEVNT1 + External Event 1 + 21 + 1 + + + TIMEVNT9 + Timer Event 9 + 20 + 1 + + + TIMEVNT8 + Timer Event 8 + 19 + 1 + + + TIMEVNT7 + Timer Event 7 + 18 + 1 + + + TIMEVNT6 + Timer Event 6 + 17 + 1 + + + TIMEVNT5 + Timer Event 5 + 16 + 1 + + + TIMEVNT4 + Timer Event 4 + 15 + 1 + + + TIMEVNT3 + Timer Event 3 + 14 + 1 + + + TIMEVNT2 + Timer Event 2 + 13 + 1 + + + TIMEVNT1 + Timer Event 1 + 12 + 1 + + + MSTCMP4 + Master Compare 4 + 11 + 1 + + + MSTCMP3 + Master Compare 3 + 10 + 1 + + + MSTCMP2 + Master Compare 2 + 9 + 1 + + + MSTCMP1 + Master Compare 1 + 8 + 1 + + + MSTPER + Master Period + 7 + 1 + + + CMP4 + Timer A compare 4 + 6 + 1 + + + CMP3 + Timer A compare 3 + 5 + 1 + + + CMP2 + Timer A compare 2 + 4 + 1 + + + CMP1 + Timer A compare 1 + 3 + 1 + + + PER + Timer A Period + 2 + 1 + + + RESYNC + Timer A resynchronizaton + 1 + 1 + + + SST + Software Set trigger + 0 + 1 + + + + + RSTD1R + RSTD1R + Timerx Output1 Reset Register + 0x40 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + SETD2R + SETD2R + Timerx Output2 Set Register + 0x44 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SST + SST + 0 + 1 + + + + + RSTD2R + RSTD2R + Timerx Output2 Reset Register + 0x48 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + EEFDR1 + EEFDR1 + Timerx External Event Filtering Register 1 + 0x4C + 0x20 + read-write + 0x00000000 + + + EE5FLTR + External Event 5 filter + 25 + 4 + + + EE5LTCH + External Event 5 latch + 24 + 1 + + + EE4FLTR + External Event 4 filter + 19 + 4 + + + EE4LTCH + External Event 4 latch + 18 + 1 + + + EE3FLTR + External Event 3 filter + 13 + 4 + + + EE3LTCH + External Event 3 latch + 12 + 1 + + + EE2FLTR + External Event 2 filter + 7 + 4 + + + EE2LTCH + External Event 2 latch + 6 + 1 + + + EE1FLTR + External Event 1 filter + 1 + 4 + + + EE1LTCH + External Event 1 latch + 0 + 1 + + + + + EEFDR2 + EEFDR2 + Timerx External Event Filtering Register 2 + 0x50 + 0x20 + read-write + 0x00000000 + + + EE10FLTR + External Event 10 filter + 25 + 4 + + + EE10LTCH + External Event 10 latch + 24 + 1 + + + EE9FLTR + External Event 9 filter + 19 + 4 + + + EE9LTCH + External Event 9 latch + 18 + 1 + + + EE8FLTR + External Event 8 filter + 13 + 4 + + + EE8LTCH + External Event 8 latch + 12 + 1 + + + EE7FLTR + External Event 7 filter + 7 + 4 + + + EE7LTCH + External Event 7 latch + 6 + 1 + + + EE6FLTR + External Event 6 filter + 1 + 4 + + + EE6LTCH + External Event 6 latch + 0 + 1 + + + + + RSTDR + RSTDR + TimerA Reset Register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIMFCPM2 + Timer F Compare 2 + 31 + 1 + + + TIMECMP4 + Timer E Compare 4 + 30 + 1 + + + TIMECMP2 + Timer E Compare 2 + 29 + 1 + + + TIMECMP1 + Timer E Compare 1 + 28 + 1 + + + TIMCCMP4 + Timer C Compare 4 + 27 + 1 + + + TIMCCMP2 + Timer C Compare 2 + 26 + 1 + + + TIMCCMP1 + Timer C Compare 1 + 25 + 1 + + + TIMBCMP4 + Timer B Compare 4 + 24 + 1 + + + TIMBCMP2 + Timer B Compare 2 + 23 + 1 + + + TIMBCMP1 + Timer B Compare 1 + 22 + 1 + + + TIMACMP4 + Timer A Compare 4 + 21 + 1 + + + TIMACMP2 + Timer A Compare 2 + 20 + 1 + + + TIMACMP1 + Timer A Compare 1 + 19 + 1 + + + EXTEVNT10 + External Event 10 + 18 + 1 + + + EXTEVNT9 + External Event 9 + 17 + 1 + + + EXTEVNT8 + External Event 8 + 16 + 1 + + + EXTEVNT7 + External Event 7 + 15 + 1 + + + EXTEVNT6 + External Event 6 + 14 + 1 + + + EXTEVNT5 + External Event 5 + 13 + 1 + + + EXTEVNT4 + External Event 4 + 12 + 1 + + + EXTEVNT3 + External Event 3 + 11 + 1 + + + EXTEVNT2 + External Event 2 + 10 + 1 + + + EXTEVNT1 + External Event 1 + 9 + 1 + + + MSTCMP4 + Master compare 4 + 8 + 1 + + + MSTCMP3 + Master compare 3 + 7 + 1 + + + MSTCMP2 + Master compare 2 + 6 + 1 + + + MSTCMP1 + Master compare 1 + 5 + 1 + + + MSTPER + Master timer Period + 4 + 1 + + + CMP4 + Timer A compare 4 reset + 3 + 1 + + + CMP2 + Timer A compare 2 reset + 2 + 1 + + + UPDT + Timer A Update reset + 1 + 1 + + + TIMFCMP1 + Timer A Update reset + 0 + 1 + + + + + CHPDR + CHPDR + Timerx Chopper Register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRTPW + STRTPW + 7 + 4 + + + CHPDTY + Timerx chopper duty cycle value + 4 + 3 + + + CHPFRQ + Timerx carrier frequency value + 0 + 4 + + + + + CPT1DCR + CPT1DCR + Timerx Capture 2 Control Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TFCMP2 + TFCMP2 + 27 + 1 + + + TFCMP1 + TFCMP1 + 26 + 1 + + + TF1RST + TF1RST + 25 + 1 + + + TF1SET + TF1SET + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + CPT2DCR + CPT2DCR + CPT2xCR + 0x60 + 0x20 + read-write + 0x00000000 + + + TECMP2 + Timer E Compare 2 + 31 + 1 + + + TECMP1 + Timer E Compare 1 + 30 + 1 + + + TE1RST + Timer E output 1 Reset + 29 + 1 + + + TE1SET + Timer E output 1 Set + 28 + 1 + + + TFCMP2 + TFCMP2 + 27 + 1 + + + TFCMP1 + TFCMP1 + 26 + 1 + + + TF1RST + TF1RST + 25 + 1 + + + TF1SET + TF1SET + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + OUTDR + OUTDR + Timerx Output Register + 0x64 + 0x20 + read-write + 0x00000000 + + + DIDL2 + Output 2 Deadtime upon burst mode Idle entry + 23 + 1 + + + CHP2 + Output 2 Chopper enable + 22 + 1 + + + FAULT2 + Output 2 Fault state + 20 + 2 + + + IDLES2 + Output 2 Idle State + 19 + 1 + + + IDLEM2 + Output 2 Idle mode + 18 + 1 + + + POL2 + Output 2 polarity + 17 + 1 + + + BIAR + Balanced Idle Automatic Resume + 14 + 1 + + + DLYPRT + Delayed Protection + 10 + 3 + + + DLYPRTEN + Delayed Protection Enable + 9 + 1 + + + DTEN + Deadtime enable + 8 + 1 + + + DIDL1 + Output 1 Deadtime upon burst mode Idle entry + 7 + 1 + + + CHP1 + Output 1 Chopper enable + 6 + 1 + + + FAULT1 + Output 1 Fault state + 4 + 2 + + + IDLES1 + Output 1 Idle State + 3 + 1 + + + IDLEM1 + Output 1 Idle mode + 2 + 1 + + + POL1 + Output 1 polarity + 1 + 1 + + + + + FLTDR + FLTDR + Timerx Fault Register + 0x68 + 0x20 + read-write + 0x00000000 + + + FLTLCK + Fault sources Lock + 31 + 1 + + + FLT6EN + Fault 6 enable + 5 + 1 + + + FLT5EN + Fault 5 enable + 4 + 1 + + + FLT4EN + Fault 4 enable + 3 + 1 + + + FLT3EN + Fault 3 enable + 2 + 1 + + + FLT2EN + Fault 2 enable + 1 + 1 + + + FLT1EN + Fault 1 enable + 0 + 1 + + + + + TIMDCR2 + TIMDCR2 + HRTIM Timerx Control Register 2 + 0x6C + 0x20 + read-write + 0x00000000 + + + TRGHLF + Triggered-half mode + 20 + 1 + + + GTCMP3 + Greater than Compare 3 PWM mode + 17 + 1 + + + GTCMP1 + Greater than Compare 1 PWM mode + 16 + 1 + + + FEROM + Fault and Event Roll-Over Mode + 14 + 2 + + + BMROM + Burst Mode Roll-Over Mode + 12 + 2 + + + ADROM + ADC Roll-Over Mode + 10 + 2 + + + OUTROM + Output Roll-Over Mode + 8 + 2 + + + ROM + Roll-Over Mode + 6 + 2 + + + UDM + Up-Down Mode + 4 + 1 + + + DCDR + Dual Channel DAC Reset trigger + 2 + 1 + + + DCDS + Dual Channel DAC Step trigger + 1 + 1 + + + DCDE + Dual Channel DAC trigger enable + 0 + 1 + + + + + DEEFR3 + DEEFR3 + HRTIM Timerx External Event Filtering Register 3 + 0x70 + 0x20 + read-write + 0x00000000 + + + EEVACNT + External Event A counter + 8 + 6 + + + EEVASEL + External Event A Selection + 4 + 4 + + + EEVARSTM + External Event A Reset Mode + 2 + 1 + + + EEVACRES + External Event A Counter Reset + 1 + 1 + + + EEVACE + External Event A Counter Enable + 0 + 1 + + + + + + + HRTIM_TIME + High Resolution Timer: TIME + HRTIM + 0x40016A80 + + 0x0 + 0x80 + registers + + + + TIMECR + TIMECR + Timerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + UPDGAT + Update Gating + 28 + 4 + + + PREEN + Preload enable + 27 + 1 + + + DACSYNC + AC Synchronization + 25 + 2 + + + MSTU + Master Timer update + 24 + 1 + + + TDU + TDU + 22 + 1 + + + TCU + TCU + 21 + 1 + + + TBU + TBU + 20 + 1 + + + TAU + TAU + 19 + 1 + + + TxRSTU + Timerx reset update + 18 + 1 + + + TxREPU + Timer x Repetition update + 17 + 1 + + + TFU + TFU + 16 + 1 + + + DELCMP4 + Delayed CMP4 mode + 14 + 2 + + + DELCMP2 + Delayed CMP2 mode + 12 + 2 + + + SYNCSTRTx + Synchronization Starts Timer x + 11 + 1 + + + SYNCRSTx + Synchronization Resets Timer x + 10 + 1 + + + RSYNCU + Re-Synchronized Update + 9 + 1 + + + INTLVD + Interleaved mode + 7 + 2 + + + PSHPLL + Push-Pull mode enable + 6 + 1 + + + HALF + Half mode enable + 5 + 1 + + + RETRIG + Re-triggerable mode + 4 + 1 + + + CONT + Continuous mode + 3 + 1 + + + CK_PSCx + HRTIM Timer x Clock prescaler + 0 + 3 + + + + + TIMEISR + TIMEISR + Timerx Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + O2CPY + Output 2 Copy + 21 + 1 + + + O1CPY + Output 1 Copy + 20 + 1 + + + O2STAT + Output 2 State + 19 + 1 + + + O1STAT + Output 1 State + 18 + 1 + + + IPPSTAT + Idle Push Pull Status + 17 + 1 + + + CPPSTAT + Current Push Pull Status + 16 + 1 + + + DLYPRT + Delayed Protection Flag + 14 + 1 + + + RST + Reset Interrupt Flag + 13 + 1 + + + RSTx2 + Output 2 Reset Interrupt Flag + 12 + 1 + + + SETx2 + Output 2 Set Interrupt Flag + 11 + 1 + + + RSTx1 + Output 1 Reset Interrupt Flag + 10 + 1 + + + SETx1 + Output 1 Set Interrupt Flag + 9 + 1 + + + CPT2 + Capture2 Interrupt Flag + 8 + 1 + + + CPT1 + Capture1 Interrupt Flag + 7 + 1 + + + UPD + Update Interrupt Flag + 6 + 1 + + + REP + Repetition Interrupt Flag + 4 + 1 + + + CMP4 + Compare 4 Interrupt Flag + 3 + 1 + + + CMP3 + Compare 3 Interrupt Flag + 2 + 1 + + + CMP2 + Compare 2 Interrupt Flag + 1 + 1 + + + CMP1 + Compare 1 Interrupt Flag + 0 + 1 + + + + + TIMEICR + TIMEICR + Timerx Interrupt Clear Register + 0x8 + 0x20 + write-only + 0x00000000 + + + DLYPRTC + Delayed Protection Flag Clear + 14 + 1 + + + RSTC + Reset Interrupt flag Clear + 13 + 1 + + + RSTx2C + Output 2 Reset flag Clear + 12 + 1 + + + SET2xC + Output 2 Set flag Clear + 11 + 1 + + + RSTx1C + Output 1 Reset flag Clear + 10 + 1 + + + SET1xC + Output 1 Set flag Clear + 9 + 1 + + + CPT2C + Capture2 Interrupt flag Clear + 8 + 1 + + + CPT1C + Capture1 Interrupt flag Clear + 7 + 1 + + + UPDC + Update Interrupt flag Clear + 6 + 1 + + + REPC + Repetition Interrupt flag Clear + 4 + 1 + + + CMP4C + Compare 4 Interrupt flag Clear + 3 + 1 + + + CMP3C + Compare 3 Interrupt flag Clear + 2 + 1 + + + CMP2C + Compare 2 Interrupt flag Clear + 1 + 1 + + + CMP1C + Compare 1 Interrupt flag Clear + 0 + 1 + + + + + TIMEDIER + TIMEDIER + TIMxDIER + 0xC + 0x20 + read-write + 0x00000000 + + + DLYPRTDE + DLYPRTDE + 30 + 1 + + + RSTDE + RSTDE + 29 + 1 + + + RSTx2DE + RSTx2DE + 28 + 1 + + + SETx2DE + SETx2DE + 27 + 1 + + + RSTx1DE + RSTx1DE + 26 + 1 + + + SET1xDE + SET1xDE + 25 + 1 + + + CPT2DE + CPT2DE + 24 + 1 + + + CPT1DE + CPT1DE + 23 + 1 + + + UPDDE + UPDDE + 22 + 1 + + + REPDE + REPDE + 20 + 1 + + + CMP4DE + CMP4DE + 19 + 1 + + + CMP3DE + CMP3DE + 18 + 1 + + + CMP2DE + CMP2DE + 17 + 1 + + + CMP1DE + CMP1DE + 16 + 1 + + + DLYPRTIE + DLYPRTIE + 14 + 1 + + + RSTIE + RSTIE + 13 + 1 + + + RSTx2IE + RSTx2IE + 12 + 1 + + + SETx2IE + SETx2IE + 11 + 1 + + + RSTx1IE + RSTx1IE + 10 + 1 + + + SET1xIE + SET1xIE + 9 + 1 + + + CPT2IE + CPT2IE + 8 + 1 + + + CPT1IE + CPT1IE + 7 + 1 + + + UPDIE + UPDIE + 6 + 1 + + + REPIE + REPIE + 4 + 1 + + + CMP4IE + CMP4IE + 3 + 1 + + + CMP3IE + CMP3IE + 2 + 1 + + + CMP2IE + CMP2IE + 1 + 1 + + + CMP1IE + CMP1IE + 0 + 1 + + + + + CNTER + CNTER + Timerx Counter Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTx + Timerx Counter value + 0 + 16 + + + + + PERER + PERER + Timerx Period Register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + PERx + Timerx Period value + 0 + 16 + + + + + REPER + REPER + Timerx Repetition Register + 0x18 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition counter value + 0 + 8 + + + + + CMP1ER + CMP1ER + Timerx Compare 1 Register + 0x1C + 0x20 + read-write + 0x00000000 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP1CER + CMP1CER + Timerx Compare 1 Compound Register + 0x20 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition value (aliased from HRTIM_REPx register) + 16 + 8 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP2ER + CMP2ER + Timerx Compare 2 Register + 0x24 + 0x20 + read-write + 0x00000000 + + + CMP2x + Timerx Compare 2 value + 0 + 16 + + + + + CMP3ER + CMP3ER + Timerx Compare 3 Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CMP3x + Timerx Compare 3 value + 0 + 16 + + + + + CMP4ER + CMP4ER + Timerx Compare 4 Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CMP4x + Timerx Compare 4 value + 0 + 16 + + + + + CPT1ER + CPT1ER + Timerx Capture 1 Register + 0x30 + 0x20 + read-only + 0x00000000 + + + CPT1x + Timerx Capture 1 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + CPT2ER + CPT2ER + Timerx Capture 2 Register + 0x34 + 0x20 + read-only + 0x00000000 + + + CPT2x + Timerx Capture 2 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + DTER + DTER + Timerx Deadtime Register + 0x38 + 0x20 + read-write + 0x00000000 + + + DTFLKx + Deadtime Falling Lock + 31 + 1 + + + DTFSLKx + Deadtime Falling Sign Lock + 30 + 1 + + + SDTFx + Sign Deadtime Falling value + 25 + 1 + + + DTFx + Deadtime Falling value + 16 + 9 + + + DTRLKx + Deadtime Rising Lock + 15 + 1 + + + DTRSLKx + Deadtime Rising Sign Lock + 14 + 1 + + + DTPRSC + Deadtime Prescaler + 10 + 3 + + + SDTRx + Sign Deadtime Rising value + 9 + 1 + + + DTRx + Deadtime Rising value + 0 + 9 + + + + + SETE1R + SETE1R + Timerx Output1 Set Register + 0x3C + 0x20 + read-write + 0x00000000 + + + UPDATE + Registers update (transfer preload to active) + 31 + 1 + + + EXTEVNT10 + External Event 10 + 30 + 1 + + + EXTEVNT9 + External Event 9 + 29 + 1 + + + EXTEVNT8 + External Event 8 + 28 + 1 + + + EXTEVNT7 + External Event 7 + 27 + 1 + + + EXTEVNT6 + External Event 6 + 26 + 1 + + + EXTEVNT5 + External Event 5 + 25 + 1 + + + EXTEVNT4 + External Event 4 + 24 + 1 + + + EXTEVNT3 + External Event 3 + 23 + 1 + + + EXTEVNT2 + External Event 2 + 22 + 1 + + + EXTEVNT1 + External Event 1 + 21 + 1 + + + TIMEVNT9 + Timer Event 9 + 20 + 1 + + + TIMEVNT8 + Timer Event 8 + 19 + 1 + + + TIMEVNT7 + Timer Event 7 + 18 + 1 + + + TIMEVNT6 + Timer Event 6 + 17 + 1 + + + TIMEVNT5 + Timer Event 5 + 16 + 1 + + + TIMEVNT4 + Timer Event 4 + 15 + 1 + + + TIMEVNT3 + Timer Event 3 + 14 + 1 + + + TIMEVNT2 + Timer Event 2 + 13 + 1 + + + TIMEVNT1 + Timer Event 1 + 12 + 1 + + + MSTCMP4 + Master Compare 4 + 11 + 1 + + + MSTCMP3 + Master Compare 3 + 10 + 1 + + + MSTCMP2 + Master Compare 2 + 9 + 1 + + + MSTCMP1 + Master Compare 1 + 8 + 1 + + + MSTPER + Master Period + 7 + 1 + + + CMP4 + Timer A compare 4 + 6 + 1 + + + CMP3 + Timer A compare 3 + 5 + 1 + + + CMP2 + Timer A compare 2 + 4 + 1 + + + CMP1 + Timer A compare 1 + 3 + 1 + + + PER + Timer A Period + 2 + 1 + + + RESYNC + Timer A resynchronizaton + 1 + 1 + + + SST + Software Set trigger + 0 + 1 + + + + + RSTE1R + RSTE1R + Timerx Output1 Reset Register + 0x40 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + SETE2R + SETE2R + Timerx Output2 Set Register + 0x44 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SST + SST + 0 + 1 + + + + + RSTE2R + RSTE2R + Timerx Output2 Reset Register + 0x48 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + EEFER1 + EEFER1 + Timerx External Event Filtering Register 1 + 0x4C + 0x20 + read-write + 0x00000000 + + + EE5FLTR + External Event 5 filter + 25 + 4 + + + EE5LTCH + External Event 5 latch + 24 + 1 + + + EE4FLTR + External Event 4 filter + 19 + 4 + + + EE4LTCH + External Event 4 latch + 18 + 1 + + + EE3FLTR + External Event 3 filter + 13 + 4 + + + EE3LTCH + External Event 3 latch + 12 + 1 + + + EE2FLTR + External Event 2 filter + 7 + 4 + + + EE2LTCH + External Event 2 latch + 6 + 1 + + + EE1FLTR + External Event 1 filter + 1 + 4 + + + EE1LTCH + External Event 1 latch + 0 + 1 + + + + + EEFER2 + EEFER2 + Timerx External Event Filtering Register 2 + 0x50 + 0x20 + read-write + 0x00000000 + + + EE10FLTR + External Event 10 filter + 25 + 4 + + + EE10LTCH + External Event 10 latch + 24 + 1 + + + EE9FLTR + External Event 9 filter + 19 + 4 + + + EE9LTCH + External Event 9 latch + 18 + 1 + + + EE8FLTR + External Event 8 filter + 13 + 4 + + + EE8LTCH + External Event 8 latch + 12 + 1 + + + EE7FLTR + External Event 7 filter + 7 + 4 + + + EE7LTCH + External Event 7 latch + 6 + 1 + + + EE6FLTR + External Event 6 filter + 1 + 4 + + + EE6LTCH + External Event 6 latch + 0 + 1 + + + + + RSTER + RSTER + TimerA Reset Register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIMFCPM2 + Timer F Compare 2 + 31 + 1 + + + TIMDCMP4 + Timer D Compare 4 + 30 + 1 + + + TIMDCMP2 + Timer D Compare 2 + 29 + 1 + + + TIMDCMP1 + Timer D Compare 1 + 28 + 1 + + + TIMCCMP4 + Timer C Compare 4 + 27 + 1 + + + TIMCCMP2 + Timer C Compare 2 + 26 + 1 + + + TIMCCMP1 + Timer C Compare 1 + 25 + 1 + + + TIMBCMP4 + Timer B Compare 4 + 24 + 1 + + + TIMBCMP2 + Timer B Compare 2 + 23 + 1 + + + TIMBCMP1 + Timer B Compare 1 + 22 + 1 + + + TIMACMP4 + Timer A Compare 4 + 21 + 1 + + + TIMACMP2 + Timer A Compare 2 + 20 + 1 + + + TIMACMP1 + Timer A Compare 1 + 19 + 1 + + + EXTEVNT10 + External Event 10 + 18 + 1 + + + EXTEVNT9 + External Event 9 + 17 + 1 + + + EXTEVNT8 + External Event 8 + 16 + 1 + + + EXTEVNT7 + External Event 7 + 15 + 1 + + + EXTEVNT6 + External Event 6 + 14 + 1 + + + EXTEVNT5 + External Event 5 + 13 + 1 + + + EXTEVNT4 + External Event 4 + 12 + 1 + + + EXTEVNT3 + External Event 3 + 11 + 1 + + + EXTEVNT2 + External Event 2 + 10 + 1 + + + EXTEVNT1 + External Event 1 + 9 + 1 + + + MSTCMP4 + Master compare 4 + 8 + 1 + + + MSTCMP3 + Master compare 3 + 7 + 1 + + + MSTCMP2 + Master compare 2 + 6 + 1 + + + MSTCMP1 + Master compare 1 + 5 + 1 + + + MSTPER + Master timer Period + 4 + 1 + + + CMP4 + Timer A compare 4 reset + 3 + 1 + + + CMP2 + Timer A compare 2 reset + 2 + 1 + + + UPDT + Timer A Update reset + 1 + 1 + + + TIMFCMP1 + Timer A Update reset + 0 + 1 + + + + + CHPER + CHPER + Timerx Chopper Register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRTPW + STRTPW + 7 + 4 + + + CHPDTY + Timerx chopper duty cycle value + 4 + 3 + + + CHPFRQ + Timerx carrier frequency value + 0 + 4 + + + + + CPT1ECR + CPT1ECR + Timerx Capture 2 Control Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TFCMP2 + TFCMP2 + 31 + 1 + + + TFCMP1 + TFCMP1 + 30 + 1 + + + TF1RST + TF1RST + 29 + 1 + + + TF1SET + TF1SET + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + CPT2ECR + CPT2ECR + CPT2xCR + 0x60 + 0x20 + read-write + 0x00000000 + + + TFCMP2 + TFCMP2 + 31 + 1 + + + TFCMP1 + TFCMP1 + 30 + 1 + + + TF1RST + TF1RST + 29 + 1 + + + TF1SET + TF1SET + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + OUTER + OUTER + Timerx Output Register + 0x64 + 0x20 + read-write + 0x00000000 + + + DIDL2 + Output 2 Deadtime upon burst mode Idle entry + 23 + 1 + + + CHP2 + Output 2 Chopper enable + 22 + 1 + + + FAULT2 + Output 2 Fault state + 20 + 2 + + + IDLES2 + Output 2 Idle State + 19 + 1 + + + IDLEM2 + Output 2 Idle mode + 18 + 1 + + + POL2 + Output 2 polarity + 17 + 1 + + + BIAR + Balanced Idle Automatic Resume + 14 + 1 + + + DLYPRT + Delayed Protection + 10 + 3 + + + DLYPRTEN + Delayed Protection Enable + 9 + 1 + + + DTEN + Deadtime enable + 8 + 1 + + + DIDL1 + Output 1 Deadtime upon burst mode Idle entry + 7 + 1 + + + CHP1 + Output 1 Chopper enable + 6 + 1 + + + FAULT1 + Output 1 Fault state + 4 + 2 + + + IDLES1 + Output 1 Idle State + 3 + 1 + + + IDLEM1 + Output 1 Idle mode + 2 + 1 + + + POL1 + Output 1 polarity + 1 + 1 + + + + + FLTER + FLTER + Timerx Fault Register + 0x68 + 0x20 + read-write + 0x00000000 + + + FLTLCK + Fault sources Lock + 31 + 1 + + + FLT6EN + Fault 6 enable + 5 + 1 + + + FLT5EN + Fault 5 enable + 4 + 1 + + + FLT4EN + Fault 4 enable + 3 + 1 + + + FLT3EN + Fault 3 enable + 2 + 1 + + + FLT2EN + Fault 2 enable + 1 + 1 + + + FLT1EN + Fault 1 enable + 0 + 1 + + + + + TIMECR2 + TIMECR2 + HRTIM Timerx Control Register 2 + 0x6C + 0x20 + read-write + 0x00000000 + + + TRGHLF + Triggered-half mode + 20 + 1 + + + GTCMP3 + Greater than Compare 3 PWM mode + 17 + 1 + + + GTCMP1 + Greater than Compare 1 PWM mode + 16 + 1 + + + FEROM + Fault and Event Roll-Over Mode + 14 + 2 + + + BMROM + Burst Mode Roll-Over Mode + 12 + 2 + + + ADROM + ADC Roll-Over Mode + 10 + 2 + + + OUTROM + Output Roll-Over Mode + 8 + 2 + + + ROM + Roll-Over Mode + 6 + 2 + + + UDM + Up-Down Mode + 4 + 1 + + + DCDR + Dual Channel DAC Reset trigger + 2 + 1 + + + DCDS + Dual Channel DAC Step trigger + 1 + 1 + + + DCDE + Dual Channel DAC trigger enable + 0 + 1 + + + + + EEEFR3 + EEEFR3 + HRTIM Timerx External Event Filtering Register 3 + 0x70 + 0x20 + read-write + 0x00000000 + + + EEVACNT + External Event A counter + 8 + 6 + + + EEVASEL + External Event A Selection + 4 + 4 + + + EEVARSTM + External Event A Reset Mode + 2 + 1 + + + EEVACRES + External Event A Counter Reset + 1 + 1 + + + EEVACE + External Event A Counter Enable + 0 + 1 + + + + + + + HRTIM_TIMF + High Resolution Timer: TIMF + HRTIM + 0x40016B00 + + 0x0 + 0x80 + registers + + + HRTIM_TIME_IRQn + HRTIM_TIME_IRQn + 72 + + + HRTIM_TIMF_IRQn + HRTIM_TIMF_IRQn + 74 + + + + TIMFCR + TIMFCR + Timerx Control Register + 0x0 + 0x20 + read-write + 0x00000000 + + + UPDGAT + Update Gating + 28 + 4 + + + PREEN + Preload enable + 27 + 1 + + + DACSYNC + AC Synchronization + 25 + 2 + + + MSTU + Master Timer update + 24 + 1 + + + TDU + TDU + 22 + 1 + + + TCU + TCU + 21 + 1 + + + TBU + TBU + 20 + 1 + + + TAU + TAU + 19 + 1 + + + TxRSTU + Timerx reset update + 18 + 1 + + + TxREPU + Timer x Repetition update + 17 + 1 + + + DELCMP4 + Delayed CMP4 mode + 14 + 2 + + + DELCMP2 + Delayed CMP2 mode + 12 + 2 + + + SYNCSTRTx + Synchronization Starts Timer x + 11 + 1 + + + SYNCRSTx + Synchronization Resets Timer x + 10 + 1 + + + RSYNCU + Re-Synchronized Update + 9 + 1 + + + INTLVD + Interleaved mode + 7 + 2 + + + PSHPLL + Push-Pull mode enable + 6 + 1 + + + HALF + Half mode enable + 5 + 1 + + + RETRIG + Re-triggerable mode + 4 + 1 + + + CONT + Continuous mode + 3 + 1 + + + CK_PSCx + HRTIM Timer x Clock prescaler + 0 + 3 + + + + + TIMFISR + TIMFISR + Timerx Interrupt Status Register + 0x4 + 0x20 + read-only + 0x00000000 + + + O2CPY + Output 2 Copy + 21 + 1 + + + O1CPY + Output 1 Copy + 20 + 1 + + + O2STAT + Output 2 State + 19 + 1 + + + O1STAT + Output 1 State + 18 + 1 + + + IPPSTAT + Idle Push Pull Status + 17 + 1 + + + CPPSTAT + Current Push Pull Status + 16 + 1 + + + DLYPRT + Delayed Protection Flag + 14 + 1 + + + RST + Reset Interrupt Flag + 13 + 1 + + + RSTx2 + Output 2 Reset Interrupt Flag + 12 + 1 + + + SETx2 + Output 2 Set Interrupt Flag + 11 + 1 + + + RSTx1 + Output 1 Reset Interrupt Flag + 10 + 1 + + + SETx1 + Output 1 Set Interrupt Flag + 9 + 1 + + + CPT2 + Capture2 Interrupt Flag + 8 + 1 + + + CPT1 + Capture1 Interrupt Flag + 7 + 1 + + + UPD + Update Interrupt Flag + 6 + 1 + + + REP + Repetition Interrupt Flag + 4 + 1 + + + CMP4 + Compare 4 Interrupt Flag + 3 + 1 + + + CMP3 + Compare 3 Interrupt Flag + 2 + 1 + + + CMP2 + Compare 2 Interrupt Flag + 1 + 1 + + + CMP1 + Compare 1 Interrupt Flag + 0 + 1 + + + + + TIMFICR + TIMFICR + Timerx Interrupt Clear Register + 0x8 + 0x20 + write-only + 0x00000000 + + + DLYPRTC + Delayed Protection Flag Clear + 14 + 1 + + + RSTC + Reset Interrupt flag Clear + 13 + 1 + + + RSTx2C + Output 2 Reset flag Clear + 12 + 1 + + + SET2xC + Output 2 Set flag Clear + 11 + 1 + + + RSTx1C + Output 1 Reset flag Clear + 10 + 1 + + + SET1xC + Output 1 Set flag Clear + 9 + 1 + + + CPT2C + Capture2 Interrupt flag Clear + 8 + 1 + + + CPT1C + Capture1 Interrupt flag Clear + 7 + 1 + + + UPDC + Update Interrupt flag Clear + 6 + 1 + + + REPC + Repetition Interrupt flag Clear + 4 + 1 + + + CMP4C + Compare 4 Interrupt flag Clear + 3 + 1 + + + CMP3C + Compare 3 Interrupt flag Clear + 2 + 1 + + + CMP2C + Compare 2 Interrupt flag Clear + 1 + 1 + + + CMP1C + Compare 1 Interrupt flag Clear + 0 + 1 + + + + + TIMFDIER + TIMFDIER + TIMxDIER + 0xC + 0x20 + read-write + 0x00000000 + + + DLYPRTDE + DLYPRTDE + 30 + 1 + + + RSTDE + RSTDE + 29 + 1 + + + RSTx2DE + RSTx2DE + 28 + 1 + + + SETx2DE + SETx2DE + 27 + 1 + + + RSTx1DE + RSTx1DE + 26 + 1 + + + SET1xDE + SET1xDE + 25 + 1 + + + CPT2DE + CPT2DE + 24 + 1 + + + CPT1DE + CPT1DE + 23 + 1 + + + UPDDE + UPDDE + 22 + 1 + + + REPDE + REPDE + 20 + 1 + + + CMP4DE + CMP4DE + 19 + 1 + + + CMP3DE + CMP3DE + 18 + 1 + + + CMP2DE + CMP2DE + 17 + 1 + + + CMP1DE + CMP1DE + 16 + 1 + + + DLYPRTIE + DLYPRTIE + 14 + 1 + + + RSTIE + RSTIE + 13 + 1 + + + RSTx2IE + RSTx2IE + 12 + 1 + + + SETx2IE + SETx2IE + 11 + 1 + + + RSTx1IE + RSTx1IE + 10 + 1 + + + SET1xIE + SET1xIE + 9 + 1 + + + CPT2IE + CPT2IE + 8 + 1 + + + CPT1IE + CPT1IE + 7 + 1 + + + UPDIE + UPDIE + 6 + 1 + + + REPIE + REPIE + 4 + 1 + + + CMP4IE + CMP4IE + 3 + 1 + + + CMP3IE + CMP3IE + 2 + 1 + + + CMP2IE + CMP2IE + 1 + 1 + + + CMP1IE + CMP1IE + 0 + 1 + + + + + CNTFR + CNTFR + Timerx Counter Register + 0x10 + 0x20 + read-write + 0x00000000 + + + CNTx + Timerx Counter value + 0 + 16 + + + + + PERFR + PERFR + Timerx Period Register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + PERx + Timerx Period value + 0 + 16 + + + + + REPFR + REPFR + Timerx Repetition Register + 0x18 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition counter value + 0 + 8 + + + + + CMP1FR + CMP1FR + Timerx Compare 1 Register + 0x1C + 0x20 + read-write + 0x00000000 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP1CFR + CMP1CFR + Timerx Compare 1 Compound Register + 0x20 + 0x20 + read-write + 0x00000000 + + + REPx + Timerx Repetition value (aliased from HRTIM_REPx register) + 16 + 8 + + + CMP1x + Timerx Compare 1 value + 0 + 16 + + + + + CMP2FR + CMP2FR + Timerx Compare 2 Register + 0x24 + 0x20 + read-write + 0x00000000 + + + CMP2x + Timerx Compare 2 value + 0 + 16 + + + + + CMP3FR + CMP3FR + Timerx Compare 3 Register + 0x28 + 0x20 + read-write + 0x00000000 + + + CMP3x + Timerx Compare 3 value + 0 + 16 + + + + + CMP4FR + CMP4FR + Timerx Compare 4 Register + 0x2C + 0x20 + read-write + 0x00000000 + + + CMP4x + Timerx Compare 4 value + 0 + 16 + + + + + CPT1FR + CPT1FR + Timerx Capture 1 Register + 0x30 + 0x20 + read-only + 0x00000000 + + + CPT1x + Timerx Capture 1 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + CPT2FR + CPT2FR + Timerx Capture 2 Register + 0x34 + 0x20 + read-only + 0x00000000 + + + CPT2x + Timerx Capture 2 value + 0 + 16 + + + DIR + Timerx Capture 1 Direction status + 16 + 1 + + + + + DTFR + DTFR + Timerx Deadtime Register + 0x38 + 0x20 + read-write + 0x00000000 + + + DTFLKx + Deadtime Falling Lock + 31 + 1 + + + DTFSLKx + Deadtime Falling Sign Lock + 30 + 1 + + + SDTFx + Sign Deadtime Falling value + 25 + 1 + + + DTFx + Deadtime Falling value + 16 + 9 + + + DTRLKx + Deadtime Rising Lock + 15 + 1 + + + DTRSLKx + Deadtime Rising Sign Lock + 14 + 1 + + + DTPRSC + Deadtime Prescaler + 10 + 3 + + + SDTRx + Sign Deadtime Rising value + 9 + 1 + + + DTRx + Deadtime Rising value + 0 + 9 + + + + + SETF1R + SETF1R + Timerx Output1 Set Register + 0x3C + 0x20 + read-write + 0x00000000 + + + UPDATE + Registers update (transfer preload to active) + 31 + 1 + + + EXTEVNT10 + External Event 10 + 30 + 1 + + + EXTEVNT9 + External Event 9 + 29 + 1 + + + EXTEVNT8 + External Event 8 + 28 + 1 + + + EXTEVNT7 + External Event 7 + 27 + 1 + + + EXTEVNT6 + External Event 6 + 26 + 1 + + + EXTEVNT5 + External Event 5 + 25 + 1 + + + EXTEVNT4 + External Event 4 + 24 + 1 + + + EXTEVNT3 + External Event 3 + 23 + 1 + + + EXTEVNT2 + External Event 2 + 22 + 1 + + + EXTEVNT1 + External Event 1 + 21 + 1 + + + TIMEVNT9 + Timer Event 9 + 20 + 1 + + + TIMEVNT8 + Timer Event 8 + 19 + 1 + + + TIMEVNT7 + Timer Event 7 + 18 + 1 + + + TIMEVNT6 + Timer Event 6 + 17 + 1 + + + TIMEVNT5 + Timer Event 5 + 16 + 1 + + + TIMEVNT4 + Timer Event 4 + 15 + 1 + + + TIMEVNT3 + Timer Event 3 + 14 + 1 + + + TIMEVNT2 + Timer Event 2 + 13 + 1 + + + TIMEVNT1 + Timer Event 1 + 12 + 1 + + + MSTCMP4 + Master Compare 4 + 11 + 1 + + + MSTCMP3 + Master Compare 3 + 10 + 1 + + + MSTCMP2 + Master Compare 2 + 9 + 1 + + + MSTCMP1 + Master Compare 1 + 8 + 1 + + + MSTPER + Master Period + 7 + 1 + + + CMP4 + Timer A compare 4 + 6 + 1 + + + CMP3 + Timer A compare 3 + 5 + 1 + + + CMP2 + Timer A compare 2 + 4 + 1 + + + CMP1 + Timer A compare 1 + 3 + 1 + + + PER + Timer A Period + 2 + 1 + + + RESYNC + Timer A resynchronizaton + 1 + 1 + + + SST + Software Set trigger + 0 + 1 + + + + + RSTE1R + RSTE1R + Timerx Output1 Reset Register + 0x40 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + SETF2R + SETF2R + Timerx Output2 Set Register + 0x44 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SST + SST + 0 + 1 + + + + + RSTF2R + RSTF2R + Timerx Output2 Reset Register + 0x48 + 0x20 + read-write + 0x00000000 + + + UPDATE + UPDATE + 31 + 1 + + + EXTEVNT10 + EXTEVNT10 + 30 + 1 + + + EXTEVNT9 + EXTEVNT9 + 29 + 1 + + + EXTEVNT8 + EXTEVNT8 + 28 + 1 + + + EXTEVNT7 + EXTEVNT7 + 27 + 1 + + + EXTEVNT6 + EXTEVNT6 + 26 + 1 + + + EXTEVNT5 + EXTEVNT5 + 25 + 1 + + + EXTEVNT4 + EXTEVNT4 + 24 + 1 + + + EXTEVNT3 + EXTEVNT3 + 23 + 1 + + + EXTEVNT2 + EXTEVNT2 + 22 + 1 + + + EXTEVNT1 + EXTEVNT1 + 21 + 1 + + + TIMEVNT9 + TIMEVNT9 + 20 + 1 + + + TIMEVNT8 + TIMEVNT8 + 19 + 1 + + + TIMEVNT7 + TIMEVNT7 + 18 + 1 + + + TIMEVNT6 + TIMEVNT6 + 17 + 1 + + + TIMEVNT5 + TIMEVNT5 + 16 + 1 + + + TIMEVNT4 + TIMEVNT4 + 15 + 1 + + + TIMEVNT3 + TIMEVNT3 + 14 + 1 + + + TIMEVNT2 + TIMEVNT2 + 13 + 1 + + + TIMEVNT1 + TIMEVNT1 + 12 + 1 + + + MSTCMP4 + MSTCMP4 + 11 + 1 + + + MSTCMP3 + MSTCMP3 + 10 + 1 + + + MSTCMP2 + MSTCMP2 + 9 + 1 + + + MSTCMP1 + MSTCMP1 + 8 + 1 + + + MSTPER + MSTPER + 7 + 1 + + + CMP4 + CMP4 + 6 + 1 + + + CMP3 + CMP3 + 5 + 1 + + + CMP2 + CMP2 + 4 + 1 + + + CMP1 + CMP1 + 3 + 1 + + + PER + PER + 2 + 1 + + + RESYNC + RESYNC + 1 + 1 + + + SRT + SRT + 0 + 1 + + + + + EEFFR1 + EEFFR1 + Timerx External Event Filtering Register 1 + 0x4C + 0x20 + read-write + 0x00000000 + + + EE5FLTR + External Event 5 filter + 25 + 4 + + + EE5LTCH + External Event 5 latch + 24 + 1 + + + EE4FLTR + External Event 4 filter + 19 + 4 + + + EE4LTCH + External Event 4 latch + 18 + 1 + + + EE3FLTR + External Event 3 filter + 13 + 4 + + + EE3LTCH + External Event 3 latch + 12 + 1 + + + EE2FLTR + External Event 2 filter + 7 + 4 + + + EE2LTCH + External Event 2 latch + 6 + 1 + + + EE1FLTR + External Event 1 filter + 1 + 4 + + + EE1LTCH + External Event 1 latch + 0 + 1 + + + + + EEFFR2 + EEFFR2 + Timerx External Event Filtering Register 2 + 0x50 + 0x20 + read-write + 0x00000000 + + + EE10FLTR + External Event 10 filter + 25 + 4 + + + EE10LTCH + External Event 10 latch + 24 + 1 + + + EE9FLTR + External Event 9 filter + 19 + 4 + + + EE9LTCH + External Event 9 latch + 18 + 1 + + + EE8FLTR + External Event 8 filter + 13 + 4 + + + EE8LTCH + External Event 8 latch + 12 + 1 + + + EE7FLTR + External Event 7 filter + 7 + 4 + + + EE7LTCH + External Event 7 latch + 6 + 1 + + + EE6FLTR + External Event 6 filter + 1 + 4 + + + EE6LTCH + External Event 6 latch + 0 + 1 + + + + + RSTFR + RSTFR + TimerA Reset Register + 0x54 + 0x20 + read-write + 0x00000000 + + + TIMFCPM2 + Timer F Compare 2 + 31 + 1 + + + TIMDCMP4 + Timer D Compare 4 + 30 + 1 + + + TIMDCMP2 + Timer D Compare 2 + 29 + 1 + + + TIMDCMP1 + Timer D Compare 1 + 28 + 1 + + + TIMCCMP4 + Timer C Compare 4 + 27 + 1 + + + TIMCCMP2 + Timer C Compare 2 + 26 + 1 + + + TIMCCMP1 + Timer C Compare 1 + 25 + 1 + + + TIMBCMP4 + Timer B Compare 4 + 24 + 1 + + + TIMBCMP2 + Timer B Compare 2 + 23 + 1 + + + TIMBCMP1 + Timer B Compare 1 + 22 + 1 + + + TIMACMP4 + Timer A Compare 4 + 21 + 1 + + + TIMACMP2 + Timer A Compare 2 + 20 + 1 + + + TIMACMP1 + Timer A Compare 1 + 19 + 1 + + + EXTEVNT10 + External Event 10 + 18 + 1 + + + EXTEVNT9 + External Event 9 + 17 + 1 + + + EXTEVNT8 + External Event 8 + 16 + 1 + + + EXTEVNT7 + External Event 7 + 15 + 1 + + + EXTEVNT6 + External Event 6 + 14 + 1 + + + EXTEVNT5 + External Event 5 + 13 + 1 + + + EXTEVNT4 + External Event 4 + 12 + 1 + + + EXTEVNT3 + External Event 3 + 11 + 1 + + + EXTEVNT2 + External Event 2 + 10 + 1 + + + EXTEVNT1 + External Event 1 + 9 + 1 + + + MSTCMP4 + Master compare 4 + 8 + 1 + + + MSTCMP3 + Master compare 3 + 7 + 1 + + + MSTCMP2 + Master compare 2 + 6 + 1 + + + MSTCMP1 + Master compare 1 + 5 + 1 + + + MSTPER + Master timer Period + 4 + 1 + + + CMP4 + Timer A compare 4 reset + 3 + 1 + + + CMP2 + Timer A compare 2 reset + 2 + 1 + + + UPDT + Timer A Update reset + 1 + 1 + + + TIMFCMP1 + Timer A Update reset + 0 + 1 + + + + + CHPFR + CHPFR + Timerx Chopper Register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRTPW + STRTPW + 7 + 4 + + + CHPDTY + Timerx chopper duty cycle value + 4 + 3 + + + CHPFRQ + Timerx carrier frequency value + 0 + 4 + + + + + CPT1FCR + CPT1FCR + Timerx Capture 2 Control Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TECMP2 + TECMP2 + 31 + 1 + + + TECMP1 + TECMP1 + 30 + 1 + + + TE1RST + TE1RST + 29 + 1 + + + TE1SET + TE1SET + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + CPT2FCR + CPT2FCR + CPT2xCR + 0x60 + 0x20 + read-write + 0x00000000 + + + TECMP2 + TECMP2 + 31 + 1 + + + TECMP1 + TECMP1 + 30 + 1 + + + TE1RST + TE1RST + 29 + 1 + + + TE1SET + TE1SET + 28 + 1 + + + TDCMP2 + Timer D Compare 2 + 27 + 1 + + + TDCMP1 + Timer D Compare 1 + 26 + 1 + + + TD1RST + Timer D output 1 Reset + 25 + 1 + + + TD1SET + Timer D output 1 Set + 24 + 1 + + + TCCMP2 + Timer C Compare 2 + 23 + 1 + + + TCCMP1 + Timer C Compare 1 + 22 + 1 + + + TC1RST + Timer C output 1 Reset + 21 + 1 + + + TC1SET + Timer C output 1 Set + 20 + 1 + + + TBCMP2 + Timer B Compare 2 + 19 + 1 + + + TBCMP1 + Timer B Compare 1 + 18 + 1 + + + TB1RST + Timer B output 1 Reset + 17 + 1 + + + TB1SET + Timer B output 1 Set + 16 + 1 + + + TACMP2 + Timer A Compare 2 + 15 + 1 + + + TACMP1 + Timer A Compare 1 + 14 + 1 + + + TA1RST + Timer A output 1 Reset + 13 + 1 + + + TA1SET + Timer A output 1 Set + 12 + 1 + + + EXEV10CPT + External Event 10 Capture + 11 + 1 + + + EXEV9CPT + External Event 9 Capture + 10 + 1 + + + EXEV8CPT + External Event 8 Capture + 9 + 1 + + + EXEV7CPT + External Event 7 Capture + 8 + 1 + + + EXEV6CPT + External Event 6 Capture + 7 + 1 + + + EXEV5CPT + External Event 5 Capture + 6 + 1 + + + EXEV4CPT + External Event 4 Capture + 5 + 1 + + + EXEV3CPT + External Event 3 Capture + 4 + 1 + + + EXEV2CPT + External Event 2 Capture + 3 + 1 + + + EXEV1CPT + External Event 1 Capture + 2 + 1 + + + UDPCPT + Update Capture + 1 + 1 + + + SWCPT + Software Capture + 0 + 1 + + + + + OUTFR + OUTFR + Timerx Output Register + 0x64 + 0x20 + read-write + 0x00000000 + + + DIDL2 + Output 2 Deadtime upon burst mode Idle entry + 23 + 1 + + + CHP2 + Output 2 Chopper enable + 22 + 1 + + + FAULT2 + Output 2 Fault state + 20 + 2 + + + IDLES2 + Output 2 Idle State + 19 + 1 + + + IDLEM2 + Output 2 Idle mode + 18 + 1 + + + POL2 + Output 2 polarity + 17 + 1 + + + BIAR + Balanced Idle Automatic Resume + 14 + 1 + + + DLYPRT + Delayed Protection + 10 + 3 + + + DLYPRTEN + Delayed Protection Enable + 9 + 1 + + + DTEN + Deadtime enable + 8 + 1 + + + DIDL1 + Output 1 Deadtime upon burst mode Idle entry + 7 + 1 + + + CHP1 + Output 1 Chopper enable + 6 + 1 + + + FAULT1 + Output 1 Fault state + 4 + 2 + + + IDLES1 + Output 1 Idle State + 3 + 1 + + + IDLEM1 + Output 1 Idle mode + 2 + 1 + + + POL1 + Output 1 polarity + 1 + 1 + + + + + FLTFR + FLTFR + Timerx Fault Register + 0x68 + 0x20 + read-write + 0x00000000 + + + FLTLCK + Fault sources Lock + 31 + 1 + + + FLT6EN + Fault 6 enable + 5 + 1 + + + FLT5EN + Fault 5 enable + 4 + 1 + + + FLT4EN + Fault 4 enable + 3 + 1 + + + FLT3EN + Fault 3 enable + 2 + 1 + + + FLT2EN + Fault 2 enable + 1 + 1 + + + FLT1EN + Fault 1 enable + 0 + 1 + + + + + TIMFCR2 + TIMFCR2 + HRTIM Timerx Control Register 2 + 0x6C + 0x20 + read-write + 0x00000000 + + + TRGHLF + Triggered-half mode + 20 + 1 + + + GTCMP3 + Greater than Compare 3 PWM mode + 17 + 1 + + + GTCMP1 + Greater than Compare 1 PWM mode + 16 + 1 + + + FEROM + Fault and Event Roll-Over Mode + 14 + 2 + + + BMROM + Burst Mode Roll-Over Mode + 12 + 2 + + + ADROM + ADC Roll-Over Mode + 10 + 2 + + + OUTROM + Output Roll-Over Mode + 8 + 2 + + + ROM + Roll-Over Mode + 6 + 2 + + + UDM + Up-Down Mode + 4 + 1 + + + DCDR + Dual Channel DAC Reset trigger + 2 + 1 + + + DCDS + Dual Channel DAC Step trigger + 1 + 1 + + + DCDE + Dual Channel DAC trigger enable + 0 + 1 + + + + + FEEFR3 + FEEFR3 + HRTIM Timerx External Event Filtering Register 3 + 0x70 + 0x20 + read-write + 0x00000000 + + + EEVACNT + External Event A counter + 8 + 6 + + + EEVASEL + External Event A Selection + 4 + 4 + + + EEVARSTM + External Event A Reset Mode + 2 + 1 + + + EEVACRES + External Event A Counter Reset + 1 + 1 + + + EEVACE + External Event A Counter Enable + 0 + 1 + + + + + + + HRTIM_Common + High Resolution Timer: Common functions + HRTIM + 0x40016B80 + + 0x0 + 0x91 + registers + + + HRTIM_TIM_FLT_IRQn + HRTIM_TIM_FLT_IRQn + 73 + + + + CR1 + CR1 + Control Register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + AD4USRC + ADC Trigger 4 Update Source + 25 + 3 + + + AD3USRC + ADC Trigger 3 Update Source + 22 + 3 + + + AD2USRC + ADC Trigger 2 Update Source + 19 + 3 + + + AD1USRC + ADC Trigger 1 Update Source + 16 + 3 + + + TFUDIS + Timer f Update Disable + 6 + 1 + + + TEUDIS + Timer E Update Disable + 5 + 1 + + + TDUDIS + Timer D Update Disable + 4 + 1 + + + TCUDIS + Timer C Update Disable + 3 + 1 + + + TBUDIS + Timer B Update Disable + 2 + 1 + + + TAUDIS + Timer A Update Disable + 1 + 1 + + + MUDIS + Master Update Disable + 0 + 1 + + + + + CR2 + CR2 + Control Register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + SWPF + Swap Timer F outputs + 21 + 1 + + + SWPE + Swap Timer E outputs + 20 + 1 + + + SWPD + Swap Timer D outputs + 19 + 1 + + + SWPC + Swap Timer C outputs + 18 + 1 + + + SWPB + Swap Timer B outputs + 17 + 1 + + + SWPA + Swap Timer A outputs + 16 + 1 + + + TFRST + Timer f counter software reset + 14 + 1 + + + TERST + Timer E counter software reset + 13 + 1 + + + TDRST + Timer D counter software reset + 12 + 1 + + + TCRST + Timer C counter software reset + 11 + 1 + + + TBRST + Timer B counter software reset + 10 + 1 + + + TARST + Timer A counter software reset + 9 + 1 + + + MRST + Master Counter software reset + 8 + 1 + + + TFSWU + Timer f Software Update + 6 + 1 + + + TESWU + Timer E Software Update + 5 + 1 + + + TDSWU + Timer D Software Update + 4 + 1 + + + TCSWU + Timer C Software Update + 3 + 1 + + + TBSWU + Timer B Software Update + 2 + 1 + + + TASWU + Timer A Software update + 1 + 1 + + + MSWU + Master Timer Software update + 0 + 1 + + + + + ISR + ISR + Interrupt Status Register + 0x8 + 0x20 + read-only + 0x00000000 + + + BMPER + Burst mode Period Interrupt Flag + 17 + 1 + + + DLLRDY + DLL Ready Interrupt Flag + 16 + 1 + + + FLT6 + Fault 6 Interrupt Flag + 6 + 1 + + + SYSFLT + System Fault Interrupt Flag + 5 + 1 + + + FLT5 + Fault 5 Interrupt Flag + 4 + 1 + + + FLT4 + Fault 4 Interrupt Flag + 3 + 1 + + + FLT3 + Fault 3 Interrupt Flag + 2 + 1 + + + FLT2 + Fault 2 Interrupt Flag + 1 + 1 + + + FLT1 + Fault 1 Interrupt Flag + 0 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0xC + 0x20 + write-only + 0x00000000 + + + BMPERC + Burst mode period flag Clear + 17 + 1 + + + DLLRDYC + DLL Ready Interrupt flag Clear + 16 + 1 + + + FLT6C + Fault 6 Interrupt Flag Clear + 6 + 1 + + + SYSFLTC + System Fault Interrupt Flag Clear + 5 + 1 + + + FLT5C + Fault 5 Interrupt Flag Clear + 4 + 1 + + + FLT4C + Fault 4 Interrupt Flag Clear + 3 + 1 + + + FLT3C + Fault 3 Interrupt Flag Clear + 2 + 1 + + + FLT2C + Fault 2 Interrupt Flag Clear + 1 + 1 + + + FLT1C + Fault 1 Interrupt Flag Clear + 0 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x10 + 0x20 + read-write + 0x00000000 + + + BMPERIE + Burst mode period Interrupt Enable + 17 + 1 + + + DLLRDYIE + DLL Ready Interrupt Enable + 16 + 1 + + + FLT6IE + Fault 6 Interrupt Enable + 6 + 1 + + + SYSFLTE + System Fault Interrupt Enable + 5 + 1 + + + FLT5IE + Fault 5 Interrupt Enable + 4 + 1 + + + FLT4IE + Fault 4 Interrupt Enable + 3 + 1 + + + FLT3IE + Fault 3 Interrupt Enable + 2 + 1 + + + FLT2IE + Fault 2 Interrupt Enable + 1 + 1 + + + FLT1IE + Fault 1 Interrupt Enable + 0 + 1 + + + + + OENR + OENR + Output Enable Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TF2ODS + Timer F Output 2 disable status + 11 + 1 + + + TF1ODS + Timer F Output 1 disable status + 10 + 1 + + + TE2OEN + Timer E Output 2 Enable + 9 + 1 + + + TE1OEN + Timer E Output 1 Enable + 8 + 1 + + + TD2OEN + Timer D Output 2 Enable + 7 + 1 + + + TD1OEN + Timer D Output 1 Enable + 6 + 1 + + + TC2OEN + Timer C Output 2 Enable + 5 + 1 + + + TC1OEN + Timer C Output 1 Enable + 4 + 1 + + + TB2OEN + Timer B Output 2 Enable + 3 + 1 + + + TB1OEN + Timer B Output 1 Enable + 2 + 1 + + + TA2OEN + Timer A Output 2 Enable + 1 + 1 + + + TA1OEN + Timer A Output 1 Enable + 0 + 1 + + + + + ODISR + ODISR + ODISR + 0x18 + 0x20 + write-only + 0x00000000 + + + TF2ODIS + TF2ODIS + 11 + 1 + + + TF1ODIS + TF1ODIS + 10 + 1 + + + TE2ODIS + TE2ODIS + 9 + 1 + + + TE1ODIS + TE1ODIS + 8 + 1 + + + TD2ODIS + TD2ODIS + 7 + 1 + + + TD1ODIS + TD1ODIS + 6 + 1 + + + TC2ODIS + TC2ODIS + 5 + 1 + + + TC1ODIS + TC1ODIS + 4 + 1 + + + TB2ODIS + TB2ODIS + 3 + 1 + + + TB1ODIS + TB1ODIS + 2 + 1 + + + TA2ODIS + TA2ODIS + 1 + 1 + + + TA1ODIS + TA1ODIS + 0 + 1 + + + + + ODSR + ODSR + Output Disable Status Register + 0x1C + 0x20 + read-only + 0x00000000 + + + TF2ODS + TF2ODS + 11 + 1 + + + TF1ODS + TF1ODS + 10 + 1 + + + TE2ODS + Timer E Output 2 disable status + 9 + 1 + + + TE1ODS + Timer E Output 1 disable status + 8 + 1 + + + TD2ODS + Timer D Output 2 disable status + 7 + 1 + + + TD1ODS + Timer D Output 1 disable status + 6 + 1 + + + TC2ODS + Timer C Output 2 disable status + 5 + 1 + + + TC1ODS + Timer C Output 1 disable status + 4 + 1 + + + TB2ODS + Timer B Output 2 disable status + 3 + 1 + + + TB1ODS + Timer B Output 1 disable status + 2 + 1 + + + TA2ODS + Timer A Output 2 disable status + 1 + 1 + + + TA1ODS + Timer A Output 1 disable status + 0 + 1 + + + + + BMCR + BMCR + Burst Mode Control Register + 0x20 + 0x20 + read-write + 0x00000000 + + + BMSTAT + Burst Mode Status + 31 + 1 + + + TFBM + Timer f Burst Mode + 22 + 1 + + + TEBM + Timer E Burst Mode + 21 + 1 + + + TDBM + Timer D Burst Mode + 20 + 1 + + + TCBM + Timer C Burst Mode + 19 + 1 + + + TBBM + Timer B Burst Mode + 18 + 1 + + + TABM + Timer A Burst Mode + 17 + 1 + + + MTBM + Master Timer Burst Mode + 16 + 1 + + + BMPREN + Burst Mode Preload Enable + 10 + 1 + + + BMPRSC + Burst Mode Prescaler + 6 + 4 + + + BMCLK + Burst Mode Clock source + 2 + 4 + + + BMOM + Burst Mode operating mode + 1 + 1 + + + BME + Burst Mode enable + 0 + 1 + + + + + BMTRG + BMTRG + BMTRG + 0x24 + 0x20 + read-write + 0x00000000 + + + OCHPEV + OCHPEV + 31 + 1 + + + EEV8 + EEV8 + 30 + 1 + + + EEV7 + EEV7 + 29 + 1 + + + TDEEV8 + TDEEV8 + 28 + 1 + + + TDEEV7 + TDEEV7 + 27 + 1 + + + TECMP2 + TECMP2 + 26 + 1 + + + TECMP1 + TECMP1 + 25 + 1 + + + TEREP + TEREP + 24 + 1 + + + TERST + TERST + 23 + 1 + + + TDCMP2 + TDCMP2 + 22 + 1 + + + TDCMP1 + TDCMP1 + 21 + 1 + + + TDREP + TDREP + 20 + 1 + + + TDRST + TDRST + 19 + 1 + + + TCCMP2 + TCCMP2 + 18 + 1 + + + TCCMP1 + TCCMP1 + 17 + 1 + + + TCREP + TCREP + 16 + 1 + + + TCRST + TCRST + 15 + 1 + + + TBCMP2 + TBCMP2 + 14 + 1 + + + TBCMP1 + TBCMP1 + 13 + 1 + + + TBREP + TBREP + 12 + 1 + + + TBRST + TBRST + 11 + 1 + + + TACMP2 + TACMP2 + 10 + 1 + + + TACMP1 + TACMP1 + 9 + 1 + + + TAREP + TAREP + 8 + 1 + + + TARST + TARST + 7 + 1 + + + MSTCMP4 + MSTCMP4 + 6 + 1 + + + MSTCMP3 + MSTCMP3 + 5 + 1 + + + MSTCMP2 + MSTCMP2 + 4 + 1 + + + MSTCMP1 + MSTCMP1 + 3 + 1 + + + MSTREP + MSTREP + 2 + 1 + + + MSTRST + MSTRST + 1 + 1 + + + SW + SW + 0 + 1 + + + + + BMCMPR + BMCMPR + BMCMPR + 0x28 + 0x20 + read-write + 0x00000000 + + + BMCMP + BMCMP + 0 + 16 + + + + + BMPER + BMPER + Burst Mode Period Register + 0x2C + 0x20 + read-write + 0x00000000 + + + BMPER + Burst mode Period + 0 + 16 + + + + + EECR1 + EECR1 + Timer External Event Control Register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + EE5FAST + External Event 5 Fast mode + 29 + 1 + + + EE5SNS + External Event 5 Sensitivity + 27 + 2 + + + EE5POL + External Event 5 Polarity + 26 + 1 + + + EE5SRC + External Event 5 Source + 24 + 2 + + + EE4FAST + External Event 4 Fast mode + 23 + 1 + + + EE4SNS + External Event 4 Sensitivity + 21 + 2 + + + EE4POL + External Event 4 Polarity + 20 + 1 + + + EE4SRC + External Event 4 Source + 18 + 2 + + + EE3FAST + External Event 3 Fast mode + 17 + 1 + + + EE3SNS + External Event 3 Sensitivity + 15 + 2 + + + EE3POL + External Event 3 Polarity + 14 + 1 + + + EE3SRC + External Event 3 Source + 12 + 2 + + + EE2FAST + External Event 2 Fast mode + 11 + 1 + + + EE2SNS + External Event 2 Sensitivity + 9 + 2 + + + EE2POL + External Event 2 Polarity + 8 + 1 + + + EE2SRC + External Event 2 Source + 6 + 2 + + + EE1FAST + External Event 1 Fast mode + 5 + 1 + + + EE1SNS + External Event 1 Sensitivity + 3 + 2 + + + EE1POL + External Event 1 Polarity + 2 + 1 + + + EE1SRC + External Event 1 Source + 0 + 2 + + + + + EECR2 + EECR2 + Timer External Event Control Register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + EE6SRC + EE6SRC + 0 + 2 + + + EE6POL + EE6POL + 2 + 1 + + + EE6SNS + EE6SNS + 3 + 2 + + + EE7SRC + EE7SRC + 6 + 2 + + + EE7POL + EE7POL + 8 + 1 + + + EE7SNS + EE7SNS + 9 + 2 + + + EE8SRC + EE8SRC + 12 + 2 + + + EE8POL + EE8POL + 14 + 1 + + + EE8SNS + EE8SNS + 15 + 2 + + + EE9SRC + EE9SRC + 18 + 2 + + + EE9POL + EE9POL + 20 + 1 + + + EE9SNS + EE9SNS + 21 + 2 + + + EE10SRC + EE10SRC + 24 + 2 + + + EE10POL + EE10POL + 26 + 1 + + + EE10SNS + EE10SNS + 27 + 2 + + + + + EECR3 + EECR3 + Timer External Event Control Register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + EE6F + EE6F + 0 + 4 + + + EE7F + EE7F + 6 + 4 + + + EE8F + EE8F + 12 + 4 + + + EE9F + EE9F + 18 + 4 + + + EE10F + EE10F + 24 + 4 + + + EEVSD + EEVSD + 30 + 2 + + + + + ADC1R + ADC1R + ADC Trigger 1 Register + 0x3C + 0x20 + read-write + 0x00000000 + + + AD1TEPER + ADC trigger 1 on Timer E Period + 31 + 1 + + + AD1TEC4 + ADC trigger 1 on Timer E compare 4 + 30 + 1 + + + AD1TEC3 + ADC trigger 1 on Timer E compare 3 + 29 + 1 + + + AD1TEC2 + ADC trigger 1 on Timer E compare 2 + 28 + 1 + + + AD1TDPER + ADC trigger 1 on Timer D Period + 27 + 1 + + + AD1TDC4 + ADC trigger 1 on Timer D compare 4 + 26 + 1 + + + AD1TDC3 + ADC trigger 1 on Timer D compare 3 + 25 + 1 + + + AD1TDC2 + ADC trigger 1 on Timer D compare 2 + 24 + 1 + + + AD1TCPER + ADC trigger 1 on Timer C Period + 23 + 1 + + + AD1TCC4 + ADC trigger 1 on Timer C compare 4 + 22 + 1 + + + AD1TCC3 + ADC trigger 1 on Timer C compare 3 + 21 + 1 + + + AD1TCC2 + ADC trigger 1 on Timer C compare 2 + 20 + 1 + + + AD1TBRST + ADC trigger 1 on Timer B Reset + 19 + 1 + + + AD1TBPER + ADC trigger 1 on Timer B Period + 18 + 1 + + + AD1TBC4 + ADC trigger 1 on Timer B compare 4 + 17 + 1 + + + AD1TBC3 + ADC trigger 1 on Timer B compare 3 + 16 + 1 + + + AD1TBC2 + ADC trigger 1 on Timer B compare 2 + 15 + 1 + + + AD1TARST + ADC trigger 1 on Timer A Reset + 14 + 1 + + + AD1TAPER + ADC trigger 1 on Timer A Period + 13 + 1 + + + AD1TAC4 + ADC trigger 1 on Timer A compare 4 + 12 + 1 + + + AD1TAC3 + ADC trigger 1 on Timer A compare 3 + 11 + 1 + + + AD1TAC2 + ADC trigger 1 on Timer A compare 2 + 10 + 1 + + + AD1EEV5 + ADC trigger 1 on External Event 5 + 9 + 1 + + + AD1EEV4 + ADC trigger 1 on External Event 4 + 8 + 1 + + + AD1EEV3 + ADC trigger 1 on External Event 3 + 7 + 1 + + + AD1EEV2 + ADC trigger 1 on External Event 2 + 6 + 1 + + + AD1EEV1 + ADC trigger 1 on External Event 1 + 5 + 1 + + + AD1MPER + ADC trigger 1 on Master Period + 4 + 1 + + + AD1MC4 + ADC trigger 1 on Master Compare 4 + 3 + 1 + + + AD1MC3 + ADC trigger 1 on Master Compare 3 + 2 + 1 + + + AD1MC2 + ADC trigger 1 on Master Compare 2 + 1 + 1 + + + AD1MC1 + ADC trigger 1 on Master Compare 1 + 0 + 1 + + + + + ADC2R + ADC2R + ADC Trigger 2 Register + 0x40 + 0x20 + read-write + 0x00000000 + + + AD2TERST + ADC trigger 2 on Timer E Reset + 31 + 1 + + + AD2TEC4 + ADC trigger 2 on Timer E compare 4 + 30 + 1 + + + AD2TEC3 + ADC trigger 2 on Timer E compare 3 + 29 + 1 + + + AD2TEC2 + ADC trigger 2 on Timer E compare 2 + 28 + 1 + + + AD2TDRST + ADC trigger 2 on Timer D Reset + 27 + 1 + + + AD2TDPER + ADC trigger 2 on Timer D Period + 26 + 1 + + + AD2TDC4 + ADC trigger 2 on Timer D compare 4 + 25 + 1 + + + AD2TDC3 + ADC trigger 2 on Timer D compare 3 + 24 + 1 + + + AD2TDC2 + ADC trigger 2 on Timer D compare 2 + 23 + 1 + + + AD2TCRST + ADC trigger 2 on Timer C Reset + 22 + 1 + + + AD2TCPER + ADC trigger 2 on Timer C Period + 21 + 1 + + + AD2TCC4 + ADC trigger 2 on Timer C compare 4 + 20 + 1 + + + AD2TCC3 + ADC trigger 2 on Timer C compare 3 + 19 + 1 + + + AD2TCC2 + ADC trigger 2 on Timer C compare 2 + 18 + 1 + + + AD2TBPER + ADC trigger 2 on Timer B Period + 17 + 1 + + + AD2TBC4 + ADC trigger 2 on Timer B compare 4 + 16 + 1 + + + AD2TBC3 + ADC trigger 2 on Timer B compare 3 + 15 + 1 + + + AD2TBC2 + ADC trigger 2 on Timer B compare 2 + 14 + 1 + + + AD2TAPER + ADC trigger 2 on Timer A Period + 13 + 1 + + + AD2TAC4 + ADC trigger 2 on Timer A compare 4 + 12 + 1 + + + AD2TAC3 + ADC trigger 2 on Timer A compare 3 + 11 + 1 + + + AD2TAC2 + ADC trigger 2 on Timer A compare 2 + 10 + 1 + + + AD2EEV10 + ADC trigger 2 on External Event 10 + 9 + 1 + + + AD2EEV9 + ADC trigger 2 on External Event 9 + 8 + 1 + + + AD2EEV8 + ADC trigger 2 on External Event 8 + 7 + 1 + + + AD2EEV7 + ADC trigger 2 on External Event 7 + 6 + 1 + + + AD2EEV6 + ADC trigger 2 on External Event 6 + 5 + 1 + + + AD2MPER + ADC trigger 2 on Master Period + 4 + 1 + + + AD2MC4 + ADC trigger 2 on Master Compare 4 + 3 + 1 + + + AD2MC3 + ADC trigger 2 on Master Compare 3 + 2 + 1 + + + AD2MC2 + ADC trigger 2 on Master Compare 2 + 1 + 1 + + + AD2MC1 + ADC trigger 2 on Master Compare 1 + 0 + 1 + + + + + ADC3R + ADC3R + ADC Trigger 3 Register + 0x44 + 0x20 + read-write + 0x00000000 + + + AD1TEPER + AD1TEPER + 31 + 1 + + + AD1TEC4 + AD1TEC4 + 30 + 1 + + + AD1TEC3 + AD1TEC3 + 29 + 1 + + + AD1TEC2 + AD1TEC2 + 28 + 1 + + + AD1TDPER + AD1TDPER + 27 + 1 + + + AD1TDC4 + AD1TDC4 + 26 + 1 + + + AD1TDC3 + AD1TDC3 + 25 + 1 + + + AD1TDC2 + AD1TDC2 + 24 + 1 + + + AD1TCPER + AD1TCPER + 23 + 1 + + + AD1TCC4 + AD1TCC4 + 22 + 1 + + + AD1TCC3 + AD1TCC3 + 21 + 1 + + + AD1TCC2 + AD1TCC2 + 20 + 1 + + + AD1TBRST + AD1TBRST + 19 + 1 + + + AD1TBPER + AD1TBPER + 18 + 1 + + + AD1TBC4 + AD1TBC4 + 17 + 1 + + + AD1TBC3 + AD1TBC3 + 16 + 1 + + + AD1TBC2 + AD1TBC2 + 15 + 1 + + + AD1TARST + AD1TARST + 14 + 1 + + + AD1TAPER + AD1TAPER + 13 + 1 + + + AD1TAC4 + AD1TAC4 + 12 + 1 + + + AD1TAC3 + AD1TAC3 + 11 + 1 + + + AD1TAC2 + AD1TAC2 + 10 + 1 + + + AD1EEV5 + AD1EEV5 + 9 + 1 + + + AD1EEV4 + AD1EEV4 + 8 + 1 + + + AD1EEV3 + AD1EEV3 + 7 + 1 + + + AD1EEV2 + AD1EEV2 + 6 + 1 + + + AD1EEV1 + AD1EEV1 + 5 + 1 + + + AD1MPER + AD1MPER + 4 + 1 + + + AD1MC4 + AD1MC4 + 3 + 1 + + + AD1MC3 + AD1MC3 + 2 + 1 + + + AD1MC2 + AD1MC2 + 1 + 1 + + + AD1MC1 + AD1MC1 + 0 + 1 + + + + + ADC4R + ADC4R + ADC Trigger 4 Register + 0x48 + 0x20 + read-write + 0x00000000 + + + AD2TERST + AD2TERST + 31 + 1 + + + AD2TEC4 + AD2TEC4 + 30 + 1 + + + AD2TEC3 + AD2TEC3 + 29 + 1 + + + AD2TEC2 + AD2TEC2 + 28 + 1 + + + AD2TDRST + AD2TDRST + 27 + 1 + + + AD2TDPER + AD2TDPER + 26 + 1 + + + AD2TDC4 + AD2TDC4 + 25 + 1 + + + AD2TDC3 + AD2TDC3 + 24 + 1 + + + AD2TDC2 + AD2TDC2 + 23 + 1 + + + AD2TCRST + AD2TCRST + 22 + 1 + + + AD2TCPER + AD2TCPER + 21 + 1 + + + AD2TCC4 + AD2TCC4 + 20 + 1 + + + AD2TCC3 + AD2TCC3 + 19 + 1 + + + AD2TCC2 + AD2TCC2 + 18 + 1 + + + AD2TBPER + AD2TBPER + 17 + 1 + + + AD2TBC4 + AD2TBC4 + 16 + 1 + + + AD2TBC3 + AD2TBC3 + 15 + 1 + + + AD2TBC2 + AD2TBC2 + 14 + 1 + + + AD2TAPER + AD2TAPER + 13 + 1 + + + AD2TAC4 + AD2TAC4 + 12 + 1 + + + AD2TAC3 + AD2TAC3 + 11 + 1 + + + AD2TAC2 + AD2TAC2 + 10 + 1 + + + AD2EEV10 + AD2EEV10 + 9 + 1 + + + AD2EEV9 + AD2EEV9 + 8 + 1 + + + AD2EEV8 + AD2EEV8 + 7 + 1 + + + AD2EEV7 + AD2EEV7 + 6 + 1 + + + AD2EEV6 + AD2EEV6 + 5 + 1 + + + AD2MPER + AD2MPER + 4 + 1 + + + AD2MC4 + AD2MC4 + 3 + 1 + + + AD2MC3 + AD2MC3 + 2 + 1 + + + AD2MC2 + AD2MC2 + 1 + 1 + + + AD2MC1 + AD2MC1 + 0 + 1 + + + + + DLLCR + DLLCR + DLL Control Register + 0x4C + 0x20 + read-write + 0x00000000 + + + CALRTE + DLL Calibration rate + 2 + 2 + + + CALEN + DLL Calibration Enable + 1 + 1 + + + CAL + DLL Calibration Start + 0 + 1 + + + + + FLTINR1 + FLTINR1 + HRTIM Fault Input Register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + FLT4LCK + FLT4LCK + 31 + 1 + + + FLT4F + FLT4F + 27 + 4 + + + FLT4SRC + FLT4SRC + 26 + 1 + + + FLT4P + FLT4P + 25 + 1 + + + FLT4E + FLT4E + 24 + 1 + + + FLT3LCK + FLT3LCK + 23 + 1 + + + FLT3F + FLT3F + 19 + 4 + + + FLT3SRC + FLT3SRC + 18 + 1 + + + FLT3P + FLT3P + 17 + 1 + + + FLT3E + FLT3E + 16 + 1 + + + FLT2LCK + FLT2LCK + 15 + 1 + + + FLT2F + FLT2F + 11 + 4 + + + FLT2SRC + FLT2SRC + 10 + 1 + + + FLT2P + FLT2P + 9 + 1 + + + FLT2E + FLT2E + 8 + 1 + + + FLT1LCK + FLT1LCK + 7 + 1 + + + FLT1F + FLT1F + 3 + 4 + + + FLT1SRC + FLT1SRC + 2 + 1 + + + FLT1P + FLT1P + 1 + 1 + + + FLT1E + FLT1E + 0 + 1 + + + + + FLTINR2 + FLTINR2 + HRTIM Fault Input Register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + FLTSD + FLTSD + 24 + 2 + + + FLT6SRC_1 + FLT6SRC + 21 + 1 + + + FLT5SRC_1 + FLT5SRC_1 + 20 + 1 + + + FLT4SRC_1 + FLT4SRC_1 + 19 + 1 + + + FLT3SRC_1 + FLT3SRC_1 + 18 + 1 + + + FLT2SRC_1 + FLT2SRC_1 + 17 + 1 + + + FLT1SRC_1 + FLT1SRC_1 + 16 + 1 + + + FLT6LCK + FLT6LCK + 15 + 1 + + + FLT6F + FLT6F + 11 + 4 + + + FLT6SRC_0 + FLT6F + 10 + 1 + + + FLT6P + FLT6P + 9 + 1 + + + FLT6E + FLT6E + 8 + 1 + + + FLT5LCK + FLT5LCK + 7 + 1 + + + FLT5F + FLT5F + 3 + 4 + + + FLT5SRC + FLT5SRC + 2 + 1 + + + FLT5P + FLT5P + 1 + 1 + + + FLT5E + FLT5E + 0 + 1 + + + + + BDMUPDR + BDMUPDR + BDMUPDR + 0x58 + 0x20 + read-write + 0x00000000 + + + MCMP4 + MCMP4 + 9 + 1 + + + MCMP3 + MCMP3 + 8 + 1 + + + MCMP2 + MCMP2 + 7 + 1 + + + MCMP1 + MCMP1 + 6 + 1 + + + MREP + MREP + 5 + 1 + + + MPER + MPER + 4 + 1 + + + MCNT + MCNT + 3 + 1 + + + MDIER + MDIER + 2 + 1 + + + MICR + MICR + 1 + 1 + + + MCR + MCR + 0 + 1 + + + + + BDTAUPR + BDTAUPR + Burst DMA Timerx update Register + 0x5C + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTBUPR + BDTBUPR + Burst DMA Timerx update Register + 0x60 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTCUPR + BDTCUPR + Burst DMA Timerx update Register + 0x64 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTDUPR + BDTDUPR + Burst DMA Timerx update Register + 0x68 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTEUPR + BDTEUPR + Burst DMA Timerx update Register + 0x6C + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDTFUPR + BDTFUPR + Burst DMA Timerx update Register + 0x74 + 0x20 + read-write + 0x00000000 + + + TIMxEEFR3 + TIMxEEFR3 + 22 + 1 + + + TIMxCR2 + TIMxCR2 + 21 + 1 + + + TIMxFLTR + HRTIM_FLTxR register update enable + 20 + 1 + + + TIMxOUTR + HRTIM_OUTxR register update enable + 19 + 1 + + + TIMxCHPR + HRTIM_CHPxR register update enable + 18 + 1 + + + TIMxRSTR + HRTIM_RSTxR register update enable + 17 + 1 + + + TIMxEEFR2 + HRTIM_EEFxR2 register update enable + 16 + 1 + + + TIMxEEFR1 + HRTIM_EEFxR1 register update enable + 15 + 1 + + + TIMxRST2R + HRTIM_RST2xR register update enable + 14 + 1 + + + TIMxSET2R + HRTIM_SET2xR register update enable + 13 + 1 + + + TIMxRST1R + HRTIM_RST1xR register update enable + 12 + 1 + + + TIMxSET1R + HRTIM_SET1xR register update enable + 11 + 1 + + + TIMx_DTxR + HRTIM_DTxR register update enable + 10 + 1 + + + TIMxCMP4 + HRTIM_CMP4xR register update enable + 9 + 1 + + + TIMxCMP3 + HRTIM_CMP3xR register update enable + 8 + 1 + + + TIMxCMP2 + HRTIM_CMP2xR register update enable + 7 + 1 + + + TIMxCMP1 + HRTIM_CMP1xR register update enable + 6 + 1 + + + TIMxREP + HRTIM_REPxR register update enable + 5 + 1 + + + TIMxPER + HRTIM_PERxR register update enable + 4 + 1 + + + TIMxCNT + HRTIM_CNTxR register update enable + 3 + 1 + + + TIMxDIER + HRTIM_TIMxDIER register update enable + 2 + 1 + + + TIMxICR + HRTIM_TIMxICR register update enable + 1 + 1 + + + TIMxCR + HRTIM_TIMxCR register update enable + 0 + 1 + + + + + BDMADR + BDMADR + Burst DMA Data Register + 0x70 + 0x20 + write-only + 0x00000000 + + + BDMADR + Burst DMA Data register + 0 + 32 + + + + + ADCER + ADCER + HRTIM ADC Extended Trigger Register + 0x78 + 0x20 + read-write + 0x00000000 + + + ADC10TRG + ADC10TRG + 26 + 5 + + + ADC9TRG + ADC9TRG + 21 + 5 + + + ADC8TRG + ADC8TRG + 16 + 5 + + + ADC7TRG + ADC7TRG + 10 + 5 + + + ADC6TRG + ADC6TRG + 5 + 5 + + + ADC5TRG + ADC5TRG + 0 + 5 + + + + + ADCUR + ADCUR + HRTIM ADC Trigger Update Register + 0x7C + 0x20 + read-write + 0x00000000 + + + AD10USRC + AD10USRC + 20 + 3 + + + AD9USRC + AD9USRC + 16 + 3 + + + AD8USRC + AD8USRC + 12 + 3 + + + AD7USRC + AD7USRC + 8 + 3 + + + AD6USRC + AD6USRC + 4 + 3 + + + AD5USRC + AD5USRC + 0 + 3 + + + + + ADCPS1 + ADCPS1 + HRTIM ADC Post Scaler Register 1 + 0x80 + 0x20 + read-write + 0x00000000 + + + ADC5PSC + ADC5PSC + 24 + 5 + + + ADC4PSC + ADC4PSC + 18 + 5 + + + ADC3PSC + ADC3PSC + 12 + 5 + + + ADC2PSC + ADC2PSC + 6 + 5 + + + ADC1PSC + ADC1PSC + 0 + 5 + + + + + ADCPS2 + ADCPS2 + HRTIM ADC Post Scaler Register 2 + 0x84 + 0x20 + read-write + 0x00000000 + + + ADC10PSC + ADC10PSC + 24 + 5 + + + ADC9PSC + ADC9PSC + 18 + 5 + + + ADC8PSC + ADC8PSC + 12 + 5 + + + ADC7PSC + ADC7PSC + 6 + 5 + + + ADC6PSC + ADC6PSC + 0 + 5 + + + + + FLTINR3 + FLTINR3 + HRTIM Fault Input Register 3 + 0x88 + 0x20 + read-write + 0x00000000 + + + FLT4RSTM + FLT4RSTM + 31 + 1 + + + FLT4CRES + FLT4CRES + 30 + 1 + + + FLT4CNT + FLT4CNT + 26 + 4 + + + FLT4BLKS + FLT4BLKS + 25 + 1 + + + FLT4BLKE + FLT4BLKE + 24 + 1 + + + FLT3RSTM + FLT3RSTM + 23 + 1 + + + FLT3CRES + FLT3CRES + 22 + 1 + + + FLT3CNT + FLT3CNT + 18 + 4 + + + FLT3BLKS + FLT3BLKS + 17 + 1 + + + FLT3BLKE + FLT3BLKE + 16 + 1 + + + FLT2RSTM + FLT2RSTM + 15 + 1 + + + FLT2CRES + FLT2CRES + 14 + 1 + + + FLT2CNT + FLT2CNT + 10 + 4 + + + FLT2BLKS + FLT2BLKS + 9 + 1 + + + FLT2BLKE + FLT2BLKE + 8 + 1 + + + FLT1RSTM + FLT1RSTM + 7 + 1 + + + FLT1CRES + FLT1CRES + 6 + 1 + + + FLT1CNT + FLT1CNT + 2 + 4 + + + FLT1BLKS + FLT1BLKS + 1 + 1 + + + FLT1BLKE + FLT1BLKE + 0 + 1 + + + + + FLTINR4 + FLTINR4 + HRTIM Fault Input Register 4 + 0x8C + 0x20 + read-write + 0x00000000 + + + FLT6RSTM + FLT6RSTM + 15 + 1 + + + FLT6CRES + FLT6CRES + 14 + 1 + + + FLT6CNT + FLT6CNT + 10 + 4 + + + FLT6BLKS + FLT6BLKS + 9 + 1 + + + FLT6BLKE + FLT6BLKE + 8 + 1 + + + FLT5RSTM + FLT5RSTM + 7 + 1 + + + FLT5CRES + FLT5CRES + 6 + 1 + + + FLT5CNT + FLT5CNT + 2 + 4 + + + FLT5BLKS + FLT5BLKS + 1 + 1 + + + FLT5BLKE + FLT5BLKE + 0 + 1 + + + + + + + QUADSPI + QuadSPI interface + QUADSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QUADSPI + QUADSPI + 95 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 24 + 8 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt enable + 19 + 1 + + + FTIE + FIFO threshold interrupt enable + 18 + 1 + + + TCIE + Transfer complete interrupt enable + 17 + 1 + + + TEIE + Transfer error interrupt enable + 16 + 1 + + + FTHRES + IFO threshold level + 8 + 5 + + + FSEL + FSEL + 7 + 1 + + + DFM + DFM + 6 + 1 + + + SSHIFT + Sample shift + 4 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR + DCR + device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + FSIZE + FLASH memory size + 16 + 5 + + + CSHT + Chip select high time + 8 + 3 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FLEVEL + FIFO level + 8 + 5 + + + BUSY + Busy + 5 + 1 + + + TOF + Timeout flag + 4 + 1 + + + SMF + Status match flag + 3 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + TEF + Transfer error flag + 0 + 1 + + + + + FCR + FCR + flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTOF + Clear timeout flag + 4 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTCF + Clear transfer complete flag + 1 + 1 + + + CTEF + Clear transfer error flag + 0 + 1 + + + + + DLR + DLR + data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + communication configuration register + 0x14 + 0x20 + read-write + 0x00000000 + + + DDRM + Double data rate mode + 31 + 1 + + + SIOO + Send instruction only once mode + 28 + 1 + + + FMODE + Functional mode + 26 + 2 + + + DMODE + Data mode + 24 + 2 + + + DCYC + Number of dummy cycles + 18 + 5 + + + ABSIZE + Alternate bytes size + 16 + 2 + + + ABMODE + Alternate bytes mode + 14 + 2 + + + ADSIZE + Address size + 12 + 2 + + + ADMODE + Address mode + 10 + 2 + + + IMODE + Instruction mode + 8 + 2 + + + INSTRUCTION + Instruction + 0 + 8 + + + + + AR + AR + address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Address + 0 + 32 + + + + + ABR + ABR + ABR + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + DR + DR + data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PSMKR + PSMKR + polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask + 0 + 32 + + + + + PSMAR + PSMAR + polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match + 0 + 32 + + + + + PIR + PIR + polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval + 0 + 16 + + + + + LPTR + LPTR + low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period + 0 + 16 + + + + + + + DAC1 + Digital-to-analog converter + DAC + 0x50000800 + + 0x0 + 0x400 + registers + + + + DAC_CR + DAC_CR + DAC control register + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1. + 0 + 1 + + + TEN1 + DAC channel1 trigger enable + 1 + 1 + + + TSEL1 + DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 2 + 4 + + + WAVE1 + DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled). + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable This bit is set and cleared by software. + 12 + 1 + + + DMAUDRIE1 + DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software. + 13 + 1 + + + CEN1 + DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 14 + 1 + + + EN2 + DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2. + 16 + 1 + + + TEN2 + DAC channel2 trigger enable + 17 + 1 + + + TSEL2 + DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled). + 18 + 4 + + + WAVE2 + DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095 + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable This bit is set and cleared by software. + 28 + 1 + + + DMAUDRIE2 + DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software. + 29 + 1 + + + CEN2 + DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored. + 30 + 1 + + + + + DAC_SWTRGR + DAC_SWTRGR + DAC software trigger register + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register. + 0 + 1 + + + SWTRIG2 + DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register. + 1 + 1 + + + SWTRIGB1 + DAC channel1 software trigger B + 16 + 1 + + + SWTRIGB2 + DAC channel2 software trigger B + 17 + 1 + + + + + DAC_DHR12R1 + DAC_DHR12R1 + DAC channel1 12-bit right-aligned data holding register + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC1DHRB + DAC channel1 12-bit right-aligned data B + 16 + 12 + + + + + DAC_DHR12L1 + DAC_DHR12L1 + DAC channel1 12-bit left aligned data holding register + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC1DHRB + DAC channel1 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R1 + DAC_DHR8R1 + DAC channel1 8-bit right aligned data holding register + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC1DHRB + DAC channel1 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12R2 + DAC_DHR12R2 + DAC channel2 12-bit right aligned data holding register + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 0 + 12 + + + DACC2DHRB + DAC channel2 12-bit right-aligned data + 16 + 12 + + + + + DAC_DHR12L2 + DAC_DHR12L2 + DAC channel2 12-bit left aligned data holding register + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2. + 4 + 12 + + + DACC2DHRB + DAC channel2 12-bit left-aligned data B + 20 + 12 + + + + + DAC_DHR8R2 + DAC_DHR8R2 + DAC channel2 8-bit right-aligned data holding register + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 0 + 8 + + + DACC2DHRB + DAC channel2 8-bit right-aligned data + 8 + 8 + + + + + DAC_DHR12RD + DAC_DHR12RD + Dual DAC 12-bit right-aligned data holding register + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 16 + 12 + + + + + DAC_DHR12LD + DAC_DHR12LD + DUAL DAC 12-bit left aligned data holding register + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1. + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2. + 20 + 12 + + + + + DAC_DHR8RD + DAC_DHR8RD + DUAL DAC 8-bit right aligned data holding register + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1. + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2. + 8 + 8 + + + + + DAC_DOR1 + DAC_DOR1 + DAC channel1 data output register + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output These bits are read-only, they contain data output for DAC channel1. + 0 + 12 + + + DACC1DORB + DAC channel1 data output + 16 + 12 + + + + + DAC_DOR2 + DAC_DOR2 + DAC channel2 data output register + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output These bits are read-only, they contain data output for DAC channel2. + 0 + 12 + + + DACC2DORB + DAC channel2 data output + 16 + 12 + + + + + DAC_SR + DAC_SR + DAC status register + 0x34 + 0x20 + 0x00000000 + + + DAC1RDY + DAC channel1 ready status bit + 11 + 1 + read-write + + + DORSTAT1 + DAC channel1 output register status bit + 12 + 1 + read-write + + + DMAUDR1 + DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 13 + 1 + read-write + + + CAL_FLAG1 + DAC Channel 1 calibration offset status This bit is set and cleared by hardware + 14 + 1 + read-only + + + BWST1 + DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization). + 15 + 1 + read-only + + + DAC2RDY + DAC channel 2 ready status bit + 27 + 1 + read-write + + + DORSTAT2 + DAC channel 2 output register status bit + 28 + 1 + read-write + + + DMAUDR2 + DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). + 29 + 1 + read-write + + + CAL_FLAG2 + DAC Channel 2 calibration offset status This bit is set and cleared by hardware + 30 + 1 + read-only + + + BWST2 + DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization). + 31 + 1 + read-only + + + + + DAC_CCR + DAC_CCR + DAC calibration control register + 0x38 + 0x20 + read-write + 0x00000000 + + + OTRIM1 + DAC Channel 1 offset trimming value + 0 + 5 + + + OTRIM2 + DAC Channel 2 offset trimming value + 16 + 5 + + + + + DAC_MCR + DAC_MCR + DAC mode control register + 0x3C + 0x20 + read-write + 0x00000000 + + + MODE1 + DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode + 0 + 3 + + + DMADOUBLE1 + DAC Channel1 DMA double data mode + 8 + 1 + + + SINFORMAT1 + Enable signed format for DAC channel1 + 9 + 1 + + + HFSEL + High frequency interface mode selection + 14 + 2 + + + MODE2 + DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode + 16 + 3 + + + DMADOUBLE2 + DAC Channel2 DMA double data mode + 24 + 1 + + + SINFORMAT2 + Enable signed format for DAC channel2 + 25 + 1 + + + + + DAC_SHSR1 + DAC_SHSR1 + DAC Sample and Hold sample time register 1 + 0x40 + 0x20 + read-write + 0x00000000 + + + TSAMPLE1 + DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHSR2 + DAC_SHSR2 + DAC Sample and Hold sample time register 2 + 0x44 + 0x20 + read-write + 0x00000000 + + + TSAMPLE2 + DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored. + 0 + 10 + + + + + DAC_SHHR + DAC_SHHR + DAC Sample and Hold hold time register + 0x48 + 0x20 + read-write + 0x00010001 + + + THOLD1 + DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI + 0 + 10 + + + THOLD2 + DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI + 16 + 10 + + + + + DAC_SHRR + DAC_SHRR + DAC Sample and Hold refresh time register + 0x4C + 0x20 + read-write + 0x00010001 + + + TREFRESH1 + DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 0 + 8 + + + TREFRESH2 + DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI + 16 + 8 + + + + + DAC_STR1 + DAC_STR1 + Sawtooth register + 0x58 + 0x20 + read-write + 0x00000000 + + + STRSTDATA1 + DAC Channel 1 Sawtooth reset value + 0 + 12 + + + STDIR1 + DAC Channel1 Sawtooth direction setting + 12 + 1 + + + STINCDATA1 + DAC CH1 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STR2 + DAC_STR2 + Sawtooth register + 0x5C + 0x20 + read-write + 0x00000000 + + + STRSTDATA2 + DAC Channel 2 Sawtooth reset value + 0 + 12 + + + STDIR2 + DAC Channel2 Sawtooth direction setting + 12 + 1 + + + STINCDATA2 + DAC CH2 Sawtooth increment value (12.4 bit format) + 16 + 16 + + + + + DAC_STMODR + DAC_STMODR + Sawtooth Mode register + 0x60 + 0x20 + read-write + 0x00000000 + + + STRSTTRIGSEL1 + DAC Channel 1 Sawtooth Reset trigger selection + 0 + 4 + + + STINCTRIGSEL1 + DAC Channel 1 Sawtooth Increment trigger selection + 8 + 4 + + + STRSTTRIGSEL2 + DAC Channel 1 Sawtooth Reset trigger selection + 16 + 4 + + + STINCTRIGSEL2 + DAC Channel 2 Sawtooth Increment trigger selection + 24 + 4 + + + + + + + DAC2 + 0x50000C00 + + + DAC3 + 0x50001000 + + + DAC4 + 0x50001400 + + + ADC1 + Analog-to-Digital Converter + ADC + 0x50000000 + + 0x0 + 0xD0 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x20000000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + JQDIS + Injected Queue disable + 31 + 1 + + + AWD1CH + Analog watchdog 1 channel selection + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + ALIGN + ALIGN + 15 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + External trigger selection for regular group + 5 + 5 + + + RES + RES + 3 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPTRIG + SMPTRIG + 27 + 1 + + + BULB + BULB + 26 + 1 + + + SWTRIG + SWTRIG + 25 + 1 + + + GCOMP + GCOMP + 16 + 1 + + + ROVSM + EXTEN + 10 + 1 + + + TROVS + Triggered Regular Oversampling + 9 + 1 + + + OVSS + ALIGN + 5 + 4 + + + OVSR + RES + 2 + 3 + + + JOVSE + DMACFG + 1 + 1 + + + ROVSE + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMPPLUS + Addition of one clock cycle to the sampling time + 31 + 1 + + + SMP0 + SMP0 + 0 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + AWDFILT + AWDFILT + 12 + 3 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x00FF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + Regular channel sequence length + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular Data converted + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 27 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ1 + JSQ1 + 9 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 19 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 19 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + Differential mode for channels 0 + 0 + 1 + read-only + + + DIFSEL_1_18 + Differential mode for channels 15 to 1 + 1 + 18 + read-write + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + GCOMP + GCOMP + Gain compensation Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + GCOMPCOEFF + GCOMPCOEFF + 0 + 14 + + + + + + + ADC2 + 0x50000100 + + + ADC3 + Analog-to-Digital Converter + ADC + 0x50000400 + + 0x0 + 0xD0 + registers + + + ADC3 + ADC3 + 47 + + + + ISR + ISR + interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + JQOVF + JQOVF + 10 + 1 + + + AWD3 + AWD3 + 9 + 1 + + + AWD2 + AWD2 + 8 + 1 + + + AWD1 + AWD1 + 7 + 1 + + + JEOS + JEOS + 6 + 1 + + + JEOC + JEOC + 5 + 1 + + + OVR + OVR + 4 + 1 + + + EOS + EOS + 3 + 1 + + + EOC + EOC + 2 + 1 + + + EOSMP + EOSMP + 1 + 1 + + + ADRDY + ADRDY + 0 + 1 + + + + + IER + IER + interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + JQOVFIE + JQOVFIE + 10 + 1 + + + AWD3IE + AWD3IE + 9 + 1 + + + AWD2IE + AWD2IE + 8 + 1 + + + AWD1IE + AWD1IE + 7 + 1 + + + JEOSIE + JEOSIE + 6 + 1 + + + JEOCIE + JEOCIE + 5 + 1 + + + OVRIE + OVRIE + 4 + 1 + + + EOSIE + EOSIE + 3 + 1 + + + EOCIE + EOCIE + 2 + 1 + + + EOSMPIE + EOSMPIE + 1 + 1 + + + ADRDYIE + ADRDYIE + 0 + 1 + + + + + CR + CR + control register + 0x8 + 0x20 + read-write + 0x20002000 + + + ADCAL + ADCAL + 31 + 1 + + + ADCALDIF + ADCALDIF + 30 + 1 + + + DEEPPWD + DEEPPWD + 29 + 1 + + + ADVREGEN + ADVREGEN + 28 + 1 + + + JADSTP + JADSTP + 5 + 1 + + + ADSTP + ADSTP + 4 + 1 + + + JADSTART + JADSTART + 3 + 1 + + + ADSTART + ADSTART + 2 + 1 + + + ADDIS + ADDIS + 1 + 1 + + + ADEN + ADEN + 0 + 1 + + + + + CFGR + CFGR + configuration register + 0xC + 0x20 + read-write + 0x80000000 + + + JQDIS + Injected Queue disable + 31 + 1 + + + AWDCH1CH + AWDCH1CH + 26 + 5 + + + JAUTO + JAUTO + 25 + 1 + + + JAWD1EN + JAWD1EN + 24 + 1 + + + AWD1EN + AWD1EN + 23 + 1 + + + AWD1SGL + AWD1SGL + 22 + 1 + + + JQM + JQM + 21 + 1 + + + JDISCEN + JDISCEN + 20 + 1 + + + DISCNUM + DISCNUM + 17 + 3 + + + DISCEN + DISCEN + 16 + 1 + + + ALIGN + ALIGN + 15 + 1 + + + AUTDLY + AUTDLY + 14 + 1 + + + CONT + CONT + 13 + 1 + + + OVRMOD + OVRMOD + 12 + 1 + + + EXTEN + EXTEN + 10 + 2 + + + EXTSEL + EXTSEL + 6 + 4 + + + ALIGN_5 + ALIGN_5 + 5 + 1 + + + RES + RES + 3 + 2 + + + DMACFG + DMACFG + 1 + 1 + + + DMAEN + DMAEN + 0 + 1 + + + + + CFGR2 + CFGR2 + configuration register + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPTRIG + SMPTRIG + 27 + 1 + + + BULB + BULB + 26 + 1 + + + SWTRIG + SWTRIG + 25 + 1 + + + GCOMP + GCOMP + 16 + 1 + + + ROVSM + EXTEN + 10 + 1 + + + TROVS + Triggered Regular Oversampling + 9 + 1 + + + OVSS + ALIGN + 5 + 4 + + + OVSR + RES + 2 + 3 + + + JOVSE + DMACFG + 1 + 1 + + + ROVSE + DMAEN + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP9 + SMP9 + 27 + 3 + + + SMP8 + SMP8 + 24 + 3 + + + SMP7 + SMP7 + 21 + 3 + + + SMP6 + SMP6 + 18 + 3 + + + SMP5 + SMP5 + 15 + 3 + + + SMP4 + SMP4 + 12 + 3 + + + SMP3 + SMP3 + 9 + 3 + + + SMP2 + SMP2 + 6 + 3 + + + SMP1 + SMP1 + 3 + 3 + + + SMPPLUS + Addition of one clock cycle to the sampling time + 31 + 1 + + + SMP0 + SMP0 + 0 + 3 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + SMP18 + SMP18 + 24 + 3 + + + SMP17 + SMP17 + 21 + 3 + + + SMP16 + SMP16 + 18 + 3 + + + SMP15 + SMP15 + 15 + 3 + + + SMP14 + SMP14 + 12 + 3 + + + SMP13 + SMP13 + 9 + 3 + + + SMP12 + SMP12 + 6 + 3 + + + SMP11 + SMP11 + 3 + 3 + + + SMP10 + SMP10 + 0 + 3 + + + + + TR1 + TR1 + watchdog threshold register 1 + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT1 + HT1 + 16 + 12 + + + AWDFILT + AWDFILT + 12 + 3 + + + LT1 + LT1 + 0 + 12 + + + + + TR2 + TR2 + watchdog threshold register + 0x24 + 0x20 + read-write + 0x00FF0000 + + + HT2 + HT2 + 16 + 8 + + + LT2 + LT2 + 0 + 8 + + + + + TR3 + TR3 + watchdog threshold register 3 + 0x28 + 0x20 + read-write + 0x00FF0000 + + + HT3 + HT3 + 16 + 8 + + + LT3 + LT3 + 0 + 8 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ4 + SQ4 + 24 + 5 + + + SQ3 + SQ3 + 18 + 5 + + + SQ2 + SQ2 + 12 + 5 + + + SQ1 + SQ1 + 6 + 5 + + + L + Regular channel sequence length + 0 + 4 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ9 + SQ9 + 24 + 5 + + + SQ8 + SQ8 + 18 + 5 + + + SQ7 + SQ7 + 12 + 5 + + + SQ6 + SQ6 + 6 + 5 + + + SQ5 + SQ5 + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x38 + 0x20 + read-write + 0x00000000 + + + SQ14 + SQ14 + 24 + 5 + + + SQ13 + SQ13 + 18 + 5 + + + SQ12 + SQ12 + 12 + 5 + + + SQ11 + SQ11 + 6 + 5 + + + SQ10 + SQ10 + 0 + 5 + + + + + SQR4 + SQR4 + regular sequence register 4 + 0x3C + 0x20 + read-write + 0x00000000 + + + SQ16 + SQ16 + 6 + 5 + + + SQ15 + SQ15 + 0 + 5 + + + + + DR + DR + regular Data Register + 0x40 + 0x20 + read-only + 0x00000000 + + + RDATA + Regular Data converted + 0 + 16 + + + + + JSQR + JSQR + injected sequence register + 0x4C + 0x20 + read-write + 0x00000000 + + + JSQ4 + JSQ4 + 27 + 5 + + + JSQ3 + JSQ3 + 21 + 5 + + + JSQ2 + JSQ2 + 15 + 5 + + + JSQ1 + JSQ1 + 9 + 5 + + + JEXTEN + JEXTEN + 7 + 2 + + + JEXTSEL + JEXTSEL + 2 + 5 + + + JL + JL + 0 + 2 + + + + + OFR1 + OFR1 + offset register 1 + 0x60 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR2 + OFR2 + offset register 2 + 0x64 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR3 + OFR3 + offset register 3 + 0x68 + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + OFR4 + OFR4 + offset register 4 + 0x6C + 0x20 + read-write + 0x00000000 + + + OFFSET1_EN + OFFSET1_EN + 31 + 1 + + + OFFSET1_CH + OFFSET1_CH + 26 + 5 + + + SATEN + SATEN + 25 + 1 + + + OFFSETPOS + OFFSETPOS + 24 + 1 + + + OFFSET1 + OFFSET1 + 0 + 12 + + + + + JDR1 + JDR1 + injected data register 1 + 0x80 + 0x20 + read-only + 0x00000000 + + + JDATA1 + JDATA1 + 0 + 16 + + + + + JDR2 + JDR2 + injected data register 2 + 0x84 + 0x20 + read-only + 0x00000000 + + + JDATA2 + JDATA2 + 0 + 16 + + + + + JDR3 + JDR3 + injected data register 3 + 0x88 + 0x20 + read-only + 0x00000000 + + + JDATA3 + JDATA3 + 0 + 16 + + + + + JDR4 + JDR4 + injected data register 4 + 0x8C + 0x20 + read-only + 0x00000000 + + + JDATA4 + JDATA4 + 0 + 16 + + + + + AWD2CR + AWD2CR + Analog Watchdog 2 Configuration Register + 0xA0 + 0x20 + read-write + 0x00000000 + + + AWD2CH + AWD2CH + 0 + 19 + + + + + AWD3CR + AWD3CR + Analog Watchdog 3 Configuration Register + 0xA4 + 0x20 + read-write + 0x00000000 + + + AWD3CH + AWD3CH + 0 + 19 + + + + + DIFSEL + DIFSEL + Differential Mode Selection Register 2 + 0xB0 + 0x20 + 0x00000000 + + + DIFSEL_0 + Differential mode for channels 0 + 0 + 1 + read-only + + + DIFSEL_1_18 + Differential mode for channels 15 to 1 + 1 + 18 + read-write + + + + + CALFACT + CALFACT + Calibration Factors + 0xB4 + 0x20 + read-write + 0x00000000 + + + CALFACT_D + CALFACT_D + 16 + 7 + + + CALFACT_S + CALFACT_S + 0 + 7 + + + + + GCOMP + GCOMP + Gain compensation Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + GCOMPCOEFF + GCOMPCOEFF + 0 + 14 + + + + + + + ADC4 + 0x50000500 + + ADC4 + ADC4 + 61 + + + + ADC5 + 0x50000600 + + ADC5 + ADC5 + 62 + + + + ADC12_Common + Analog-to-Digital Converter + ADC + 0x50000300 + + 0x0 + 0x11 + registers + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + ADDRDY_MST + ADDRDY_MST + 0 + 1 + + + EOSMP_MST + EOSMP_MST + 1 + 1 + + + EOC_MST + EOC_MST + 2 + 1 + + + EOS_MST + EOS_MST + 3 + 1 + + + OVR_MST + OVR_MST + 4 + 1 + + + JEOC_MST + JEOC_MST + 5 + 1 + + + JEOS_MST + JEOS_MST + 6 + 1 + + + AWD1_MST + AWD1_MST + 7 + 1 + + + AWD2_MST + AWD2_MST + 8 + 1 + + + AWD3_MST + AWD3_MST + 9 + 1 + + + JQOVF_MST + JQOVF_MST + 10 + 1 + + + ADRDY_SLV + ADRDY_SLV + 16 + 1 + + + EOSMP_SLV + EOSMP_SLV + 17 + 1 + + + EOC_SLV + End of regular conversion of the slave ADC + 18 + 1 + + + EOS_SLV + End of regular sequence flag of the slave ADC + 19 + 1 + + + OVR_SLV + Overrun flag of the slave ADC + 20 + 1 + + + JEOC_SLV + End of injected conversion flag of the slave ADC + 21 + 1 + + + JEOS_SLV + End of injected sequence flag of the slave ADC + 22 + 1 + + + AWD1_SLV + Analog watchdog 1 flag of the slave ADC + 23 + 1 + + + AWD2_SLV + Analog watchdog 2 flag of the slave ADC + 24 + 1 + + + AWD3_SLV + Analog watchdog 3 flag of the slave ADC + 25 + 1 + + + JQOVF_SLV + Injected Context Queue Overflow flag of the slave ADC + 26 + 1 + + + + + CCR + CCR + ADC common control register + 0x8 + 0x20 + read-write + 0x00000000 + + + DUAL + Dual ADC mode selection + 0 + 5 + + + DELAY + Delay between 2 sampling phases + 8 + 4 + + + DMACFG + DMA configuration (for multi-ADC mode) + 13 + 1 + + + MDMA + Direct memory access mode for multi ADC mode + 14 + 2 + + + CKMODE + ADC clock mode + 16 + 2 + + + VREFEN + VREFINT enable + 22 + 1 + + + VSENSESEL + VTS selection + 23 + 1 + + + VBATSEL + VBAT selection + 24 + 1 + + + PRESC + ADC prescaler + 18 + 4 + + + + + CDR + CDR + ADC common regular data register for dual and triple modes + 0xC + 0x20 + read-only + 0x00000000 + + + RDATA_SLV + Regular data of the slave ADC + 16 + 16 + + + RDATA_MST + Regular data of the master ADC + 0 + 16 + + + + + + + ADC345_Common + 0x50000700 + + + FMAC + Filter Math Accelerator + FMAC + 0x40021400 + + 0x0 + 0xC00 + registers + + + FMAC + FMAC + 101 + + + + X1BUFCFG + X1BUFCFG + FMAC X1 Buffer Configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + X1_BASE + X1_BASE + 0 + 8 + + + X1_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + FULL_WM + FULL_WM + 24 + 2 + + + + + X2BUFCFG + X2BUFCFG + FMAC X2 Buffer Configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + X2_BASE + X1_BASE + 0 + 8 + + + X2_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + + + YBUFCFG + YBUFCFG + FMAC Y Buffer Configuration register + 0x8 + 0x20 + read-write + 0x00000000 + + + Y_BASE + X1_BASE + 0 + 8 + + + Y_BUF_SIZE + X1_BUF_SIZE + 8 + 8 + + + EMPTY_WM + EMPTY_WM + 24 + 2 + + + + + PARAM + PARAM + FMAC Parameter register + 0xC + 0x20 + read-write + 0x00000000 + + + START + START + 31 + 1 + + + FUNC + FUNC + 24 + 7 + + + R + R + 16 + 8 + + + Q + Q + 8 + 8 + + + P + P + 0 + 8 + + + + + CR + CR + FMAC Control register + 0x10 + 0x20 + read-write + 0x00000000 + + + RESET + RESET + 16 + 1 + + + CLIPEN + CLIPEN + 15 + 1 + + + DMAWEN + DMAWEN + 9 + 1 + + + DMAREN + DMAREN + 8 + 1 + + + SATIEN + SATIEN + 4 + 1 + + + UNFLIEN + UNFLIEN + 3 + 1 + + + OVFLIEN + OVFLIEN + 2 + 1 + + + WIEN + WIEN + 1 + 1 + + + RIEN + RIEN + 0 + 1 + + + + + SR + SR + FMAC Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + YEMPTY + YEMPTY + 0 + 1 + + + X1FULL + X1FULL + 1 + 1 + + + OVFL + OVFL + 8 + 1 + + + UNFL + UNFL + 9 + 1 + + + SAT + SAT + 10 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x18 + 0x20 + write-only + 0x00000000 + + + WDATA + WDATA + 0 + 16 + + + + + RDATA + RDATA + FMAC Read Data register + 0x1C + 0x20 + read-only + 0x00000000 + + + RDATA + RDATA + 0 + 16 + + + + + + + CORDIC + CORDIC Co-processor + CORDIC + 0x40020C00 + + 0x0 + 0x400 + registers + + + Cordic + Cordic + 100 + + + + CSR + CSR + CORDIC Control Status register + 0x0 + 0x20 + read-write + 0x00000000 + + + FUNC + FUNC + 0 + 4 + + + PRECISION + PRECISION + 4 + 4 + + + SCALE + SCALE + 8 + 3 + + + IEN + IEN + 16 + 1 + + + DMAREN + DMAREN + 17 + 1 + + + DMAWEN + DMAWEN + 18 + 1 + + + NRES + NRES + 19 + 1 + + + NARGS + NARGS + 20 + 1 + + + RESSIZE + RESSIZE + 21 + 1 + + + ARGSIZE + ARGSIZE + 22 + 1 + + + RRDY + RRDY + 31 + 1 + + + + + WDATA + WDATA + FMAC Write Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + ARG + ARG + 0 + 32 + + + + + RDATA + RDATA + FMAC Read Data register + 0x8 + 0x20 + read-only + 0x00000000 + + + RES + RES + 0 + 32 + + + + + + + SAI + Serial audio interface + SAI + 0x40015400 + + 0x0 + 0x400 + registers + + + SAI + SAI + 76 + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCKEN + MCKEN + 27 + 1 + + + OSR + OSR + 26 + 1 + + + MCJDIV + Master clock divider + 20 + 6 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization offset + 18 + 1 + + + FSPOL + Frame synchronization polarity + 17 + 1 + + + FSDEF + Frame synchronization definition + 16 + 1 + + + FSALL + Frame synchronization active level length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt enable + 4 + 1 + + + FREQIE + FIFO request interrupt enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt enable + 2 + 1 + + + MUTEDET + Mute detection interrupt enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-write + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit is read only + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + LFSDET + Clear late frame synchronization detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PDMCR + PDMCR + PDM control register + 0x44 + 0x20 + read-write + 0x00000000 + + + PDMEN + PDMEN + 0 + 1 + + + MICNBR + MICNBR + 4 + 2 + + + CKEN1 + CKEN1 + 8 + 1 + + + CKEN2 + CKEN2 + 9 + 1 + + + CKEN3 + CKEN3 + 10 + 1 + + + CKEN4 + CKEN4 + 11 + 1 + + + + + PDMDLY + PDMDLY + PDM delay register + 0x48 + 0x20 + read-write + 0x00000000 + + + DLYM1L + DLYM1L + 0 + 3 + + + DLYM1R + DLYM1R + 4 + 3 + + + DLYM2L + DLYM2L + 8 + 3 + + + DLYM2R + DLYM2R + 12 + 3 + + + DLYM3L + DLYM3L + 16 + 3 + + + DLYM3R + DLYM3R + 20 + 3 + + + DLYM4L + DLYM4L + 24 + 3 + + + DLYM4R + DLYM4R + 28 + 3 + + + + + + + TAMP + Tamper and backup registers + TAMP + 0x40002400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0xFFFF0000 + + + TAMP1E + TAMP1E + 0 + 1 + + + TAMP2E + TAMP2E + 1 + 1 + + + TAMP3E + TAMP2E + 2 + 1 + + + ITAMP3E + ITAMP3E + 18 + 1 + + + ITAMP4E + ITAMP4E + 19 + 1 + + + ITAMP5E + ITAMP5E + 20 + 1 + + + ITAMP6E + ITAMP6E + 21 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + TAMP1NOER + TAMP1NOER + 0 + 1 + + + TAMP2NOER + TAMP2NOER + 1 + 1 + + + TAMP3NOER + TAMP3NOER + 2 + 1 + + + TAMP1MSK + TAMP1MSK + 16 + 1 + + + TAMP2MSK + TAMP2MSK + 17 + 1 + + + TAMP3MSK + TAMP3MSK + 18 + 1 + + + TAMP1TRG + TAMP1TRG + 24 + 1 + + + TAMP2TRG + TAMP2TRG + 25 + 1 + + + TAMP3TRG + TAMP3TRG + 26 + 1 + + + + + FLTCR + FLTCR + TAMP filter control register + 0xC + 0x20 + read-write + 0x00000000 + + + TAMPFREQ + TAMPFREQ + 0 + 3 + + + TAMPFLT + TAMPFLT + 3 + 2 + + + TAMPPRCH + TAMPPRCH + 5 + 2 + + + TAMPPUDIS + TAMPPUDIS + 7 + 1 + + + + + IER + IER + TAMP interrupt enable register + 0x2C + 0x20 + read-write + 0x00000000 + + + TAMP1IE + TAMP1IE + 0 + 1 + + + TAMP2IE + TAMP2IE + 1 + 1 + + + TAMP3IE + TAMP3IE + 2 + 1 + + + ITAMP3IE + ITAMP3IE + 18 + 1 + + + ITAMP4IE + ITAMP4IE + 19 + 1 + + + ITAMP5IE + ITAMP5IE + 20 + 1 + + + ITAMP6IE + ITAMP6IE + 21 + 1 + + + + + SR + SR + TAMP status register + 0x30 + 0x20 + read-only + 0x00000000 + + + TAMP1F + TAMP1F + 0 + 1 + + + TAMP2F + TAMP2F + 1 + 1 + + + TAMP3F + TAMP3F + 2 + 1 + + + ITAMP3F + ITAMP3F + 18 + 1 + + + ITAMP4F + ITAMP4F + 19 + 1 + + + ITAMP5F + ITAMP5F + 20 + 1 + + + ITAMP6F + ITAMP6F + 21 + 1 + + + + + MISR + MISR + TAMP masked interrupt status register + 0x34 + 0x20 + read-only + 0x00000000 + + + TAMP1MF + TAMP1MF: + 0 + 1 + + + TAMP2MF + TAMP2MF + 1 + 1 + + + TAMP3MF + TAMP3MF + 2 + 1 + + + ITAMP3MF + ITAMP3MF + 18 + 1 + + + ITAMP4MF + ITAMP4MF + 19 + 1 + + + ITAMP5MF + ITAMP5MF + 20 + 1 + + + ITAMP6MF + ITAMP6MF + 21 + 1 + + + + + SCR + SCR + TAMP status clear register + 0x3C + 0x20 + read-write + 0x00000000 + + + CTAMP1F + CTAMP1F + 0 + 1 + + + CTAMP2F + CTAMP2F + 1 + 1 + + + CTAMP3F + CTAMP3F + 2 + 1 + + + CITAMP3F + CITAMP3F + 18 + 1 + + + CITAMP4F + CITAMP4F + 19 + 1 + + + CITAMP5F + CITAMP5F + 20 + 1 + + + CITAMP6F + CITAMP6F + 21 + 1 + + + + + BKP0R + BKP0R + TAMP backup register + 0x100 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + TAMP backup register + 0x104 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + TAMP backup register + 0x108 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + TAMP backup register + 0x10C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + TAMP backup register + 0x110 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + TAMP backup register + 0x114 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + TAMP backup register + 0x118 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + TAMP backup register + 0x11C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + TAMP backup register + 0x120 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + TAMP backup register + 0x124 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + TAMP backup register + 0x128 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + TAMP backup register + 0x12C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + TAMP backup register + 0x130 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + TAMP backup register + 0x134 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + TAMP backup register + 0x138 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + TAMP backup register + 0x13C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + TAMP backup register + 0x140 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + TAMP backup register + 0x144 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + TAMP backup register + 0x148 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + TAMP backup register + 0x14C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP20R + BKP20R + TAMP backup register + 0x150 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP21R + BKP21R + TAMP backup register + 0x154 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP22R + BKP22R + TAMP backup register + 0x158 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP23R + BKP23R + TAMP backup register + 0x15C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP24R + BKP24R + TAMP backup register + 0x160 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP25R + BKP25R + TAMP backup register + 0x164 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP26R + BKP26R + TAMP backup register + 0x168 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP27R + BKP27R + TAMP backup register + 0x16C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP28R + BKP28R + TAMP backup register + 0x170 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP29R + BKP29R + TAMP backup register + 0x174 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP30R + BKP30R + TAMP backup register + 0x178 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP31R + BKP31R + TAMP backup register + 0x17C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + FPU + Floting point unit + FPU + 0xE000EF34 + + 0x0 + 0xD + registers + + + FPU + Floating point unit interrupt + 81 + + + + FPCCR + FPCCR + Floating-point context control register + 0x0 + 0x20 + read-write + 0x00000000 + + + LSPACT + LSPACT + 0 + 1 + + + USER + USER + 1 + 1 + + + THREAD + THREAD + 3 + 1 + + + HFRDY + HFRDY + 4 + 1 + + + MMRDY + MMRDY + 5 + 1 + + + BFRDY + BFRDY + 6 + 1 + + + MONRDY + MONRDY + 8 + 1 + + + LSPEN + LSPEN + 30 + 1 + + + ASPEN + ASPEN + 31 + 1 + + + + + FPCAR + FPCAR + Floating-point context address register + 0x4 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Location of unpopulated floating-point + 3 + 29 + + + + + FPSCR + FPSCR + Floating-point status control register + 0x8 + 0x20 + read-write + 0x00000000 + + + IOC + Invalid operation cumulative exception bit + 0 + 1 + + + DZC + Division by zero cumulative exception bit. + 1 + 1 + + + OFC + Overflow cumulative exception bit + 2 + 1 + + + UFC + Underflow cumulative exception bit + 3 + 1 + + + IXC + Inexact cumulative exception bit + 4 + 1 + + + IDC + Input denormal cumulative exception bit. + 7 + 1 + + + RMode + Rounding Mode control field + 22 + 2 + + + FZ + Flush-to-zero mode control bit: + 24 + 1 + + + DN + Default NaN mode control bit + 25 + 1 + + + AHP + Alternative half-precision control bit + 26 + 1 + + + V + Overflow condition code flag + 28 + 1 + + + C + Carry condition code flag + 29 + 1 + + + Z + Zero condition code flag + 30 + 1 + + + N + Negative condition code flag + 31 + 1 + + + + + + + MPU + Memory protection unit + MPU + 0xE000E084 + + 0x0 + 0x15 + registers + + + + TYPER + TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction regions + 16 + 8 + + + + + CTRL + CTRL + MPU control register + 0x4 + 0x20 + read-write + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to default memory map + 2 + 1 + + + + + RNR + RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + RBAR + RBAR + MPU region base address register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + RASR + RASR + MPU region attribute and size register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable bit + 28 + 1 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CTRL + CTRL + SysTick control and status register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD + LOAD + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + SKEW + SKEW flag: Indicates whether the TENMS value is exact + 30 + 1 + + + NOREF + NOREF flag. Reads as zero + 31 + 1 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler 4 + 0 + 8 + + + PRI_5 + Priority of system handler 5 + 8 + 8 + + + PRI_6 + Priority of system handler 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler 14 + 16 + 8 + + + PRI_15 + Priority of system handler 15 + 24 + 8 + + + + + SHCSR + SHCSR + System handler control and state register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active bit + 10 + 1 + + + SYSTICKACT + SysTick exception active bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + Instruction access violation flag + 1 + 1 + + + MUNSTKERR + Memory manager fault on unstacking for a return from exception + 3 + 1 + + + MSTKERR + Memory manager fault on stacking for exception entry. + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + Memory Management Fault Address Register (MMAR) valid flag + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage fault + 18 + 1 + + + NOCP + No coprocessor usage fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + AFSR + AFSR + Auxiliary fault status register + 0x3C + 0x20 + read-write + 0x00000000 + + + IMPDEF + Implementation defined + 0 + 32 + + + + + + + NVIC + Nested Vectored Interrupt Controller + NVIC + 0xE000E100 + + 0x0 + 0x400 + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER2 + ISER2 + Interrupt Set-Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER3 + ISER3 + Interrupt Set-Enable Register + 0xC + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER2 + ICER2 + Interrupt Clear-Enable Register + 0x88 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER3 + ICER3 + Interrupt Clear-Enable Register + 0x8C + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR2 + ISPR2 + Interrupt Set-Pending Register + 0x108 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR3 + ISPR3 + Interrupt Set-Pending Register + 0x10C + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR2 + ICPR2 + Interrupt Clear-Pending Register + 0x188 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR3 + ICPR3 + Interrupt Clear-Pending Register + 0x18C + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR2 + IABR2 + Interrupt Active Bit Register + 0x208 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR3 + IABR3 + Interrupt Active Bit Register + 0x20C + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR15 + IPR15 + Interrupt Priority Register + 0x33C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR16 + IPR16 + Interrupt Priority Register + 0x340 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR17 + IPR17 + Interrupt Priority Register + 0x344 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR18 + IPR18 + Interrupt Priority Register + 0x348 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR19 + IPR19 + Interrupt Priority Register + 0x34C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR20 + IPR20 + Interrupt Priority Register + 0x350 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR21 + IPR21 + Interrupt Priority Register + 0x354 + 0x20 + read-write + 0x00000000 + + + IPR22 + IPR22 + Interrupt Priority Register + 0x358 + 0x20 + read-write + 0x00000000 + + + IPR23 + IPR23 + Interrupt Priority Register + 0x35C + 0x20 + read-write + 0x00000000 + + + IPR24 + IPR24 + Interrupt Priority Register + 0x360 + 0x20 + read-write + 0x00000000 + + + IPR25 + IPR25 + Interrupt Priority Register + 0x364 + 0x20 + read-write + 0x00000000 + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + FPU_CPACR + Floating point unit CPACR + FPU + 0xE000ED88 + + 0x0 + 0x5 + registers + + + + CPACR + CPACR + Coprocessor access control register + 0x0 + 0x20 + read-write + 0x0000000 + + + CP + CP + 20 + 4 + + + + + + + SCB_ACTLR + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISMCYCINT + DISMCYCINT + 0 + 1 + + + DISDEFWBUF + DISDEFWBUF + 1 + 1 + + + DISFOLD + DISFOLD + 2 + 1 + + + DISFPCA + DISFPCA + 8 + 1 + + + DISOOFP + DISOOFP + 9 + 1 + + + + + + + FDCAN + FDCAN + FDCAN + 0x4000A400 + + 0x0 + 0x400 + registers + + + + CREL + CREL + FDCAN Core Release Register + 0x0 + 0x20 + read-only + 0x32141218 + + + DAY + DAY + 0 + 8 + + + MON + MON + 8 + 8 + + + YEAR + YEAR + 16 + 4 + + + SUBSTEP + SUBSTEP + 20 + 4 + + + STEP + STEP + 24 + 4 + + + REL + REL + 28 + 4 + + + + + ENDN + ENDN + FDCAN Core Release Register + 0x4 + 0x20 + read-only + 0x87654321 + + + ETV + ETV + 0 + 32 + + + + + DBTP + DBTP + This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point. + 0xC + 0x20 + 0x00000A33 + + + DSJW + DSJW + 0 + 4 + read-write + + + DTSEG2 + DTSEG2 + 4 + 4 + read-write + + + DTSEG1 + DTSEG1 + 8 + 5 + read-write + + + DBRP + DBRP + 16 + 5 + read-write + + + TDC + TDC + 23 + 1 + read-write + + + + + TEST + TEST + Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus. + 0x10 + 0x20 + 0x00000000 + + + LBCK + LBCK + 4 + 1 + read-write + + + TX + TX + 5 + 2 + read-write + + + RX + RX + 7 + 1 + read-only + + + + + RWD + RWD + The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock. + 0x14 + 0x20 + 0x00000000 + + + WDC + WDC + 0 + 8 + read-write + + + WDV + WDV + 8 + 8 + read-only + + + + + CCCR + CCCR + For details about setting and resetting of single bits see Software initialization. + 0x18 + 0x20 + 0x00000001 + + + INIT + INIT + 0 + 1 + read-write + + + CCE + CCE + 1 + 1 + read-write + + + ASM + ASM + 2 + 1 + read-write + + + CSA + CSA + 3 + 1 + read-only + + + CSR + CSR + 4 + 1 + read-write + + + MON + MON + 5 + 1 + read-write + + + DAR + DAR + 6 + 1 + read-write + + + TEST + TEST + 7 + 1 + read-write + + + FDOE + FDOE + 8 + 1 + read-write + + + BRSE + BRSE + 9 + 1 + read-write + + + PXHD + PXHD + 12 + 1 + read-write + + + EFBI + EFBI + 13 + 1 + read-write + + + TXP + TXP + 14 + 1 + read-write + + + NISO + NISO + 15 + 1 + read-write + + + + + NBTP + NBTP + FDCAN_NBTP + 0x1C + 0x20 + read-write + 0x06000A03 + + + NTSEG2 + NTSEG2 + 0 + 7 + + + NTSEG1 + NTSEG1 + 8 + 8 + + + NBRP + NBRP + 16 + 9 + + + NSJW + NSJW + 25 + 7 + + + + + TSCC + TSCC + FDCAN Timestamp Counter Configuration Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TSS + TSS + 0 + 2 + + + TCP + TCP + 16 + 4 + + + + + TSCV + TSCV + FDCAN Timestamp Counter Value Register + 0x24 + 0x20 + read-only + 0x00000000 + + + TSC + TSC + 0 + 16 + + + + + TOCC + TOCC + FDCAN Timeout Counter Configuration Register + 0x28 + 0x20 + 0xFFFF0000 + + + ETOC + ETOC + 0 + 1 + read-write + + + TOS + TOS + 1 + 2 + read-write + + + TOP + TOP + 16 + 16 + read-write + + + + + TOCV + TOCV + FDCAN Timeout Counter Value Register + 0x2C + 0x20 + read-only + 0x0000FFFF + + + TOC + TOC + 0 + 16 + + + + + ECR + ECR + FDCAN Error Counter Register + 0x40 + 0x20 + read-only + 0x00000000 + + + TEC + TEC + 0 + 8 + + + REC + TREC + 8 + 7 + + + RP + RP + 15 + 1 + + + CEL + CEL + 16 + 8 + + + + + PSR + PSR + FDCAN Protocol Status Register + 0x44 + 0x20 + 0x00000707 + + + LEC + LEC + 0 + 3 + read-write + + + ACT + ACT + 3 + 2 + read-only + + + EP + EP + 5 + 1 + read-only + + + EW + EW + 6 + 1 + read-only + + + BO + BO + 7 + 1 + read-only + + + DLEC + DLEC + 8 + 3 + read-write + + + RESI + RESI + 11 + 1 + read-write + + + RBRS + RBRS + 12 + 1 + read-write + + + REDL + REDL + 13 + 1 + read-write + + + PXE + PXE + 14 + 1 + read-write + + + TDCV + TDCV + 16 + 7 + read-write + + + + + TDCR + TDCR + FDCAN Transmitter Delay Compensation Register + 0x48 + 0x20 + read-write + 0x00000000 + + + TDCF + TDCF + 0 + 7 + + + TDCO + TDCO + 8 + 7 + + + + + IR + IR + The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. + 0x50 + 0x20 + read-write + 0x00000000 + + + RF0N + RF0N + 0 + 1 + + + RF0F + RF0F + 1 + 1 + + + RF0L + RF0L + 2 + 1 + + + RF1N + RF1N + 3 + 1 + + + RF1F + RF1F + 4 + 1 + + + RF1L + RF1L + 5 + 1 + + + HPM + HPM + 6 + 1 + + + TC + TC + 7 + 1 + + + TCF + TCF + 8 + 1 + + + TFE + TFE + 9 + 1 + + + TEFN + TEFN + 10 + 1 + + + TEFF + TEFF + 11 + 1 + + + TEFL + TEFL + 12 + 1 + + + TSW + TSW + 13 + 1 + + + MRAF + MRAF + 14 + 1 + + + TOO + TOO + 15 + 1 + + + ELO + ELO + 16 + 1 + + + EP + EP + 17 + 1 + + + EW + EW + 18 + 1 + + + BO + BO + 19 + 1 + + + WDI + WDI + 20 + 1 + + + PEA + PEA + 21 + 1 + + + PED + PED + 22 + 1 + + + ARA + ARA + 23 + 1 + + + + + IE + IE + The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. + 0x54 + 0x20 + read-write + 0x00000000 + + + RF0NE + RF0NE + 0 + 1 + + + RF0FE + RF0FE + 1 + 1 + + + RF0LE + RF0LE + 2 + 1 + + + RF1NE + RF1NE + 3 + 1 + + + RF1FE + RF1FE + 4 + 1 + + + RF1LE + RF1LE + 5 + 1 + + + HPME + HPME + 6 + 1 + + + TCE + TCE + 7 + 1 + + + TCFE + TCFE + 8 + 1 + + + TFEE + TFEE + 9 + 1 + + + TEFNE + TEFNE + 10 + 1 + + + TEFFE + TEFFE + 11 + 1 + + + TEFLE + TEFLE + 12 + 1 + + + TSWE + TSWE + 13 + 1 + + + MRAFE + MRAFE + 14 + 1 + + + TOOE + TOOE + 15 + 1 + + + ELOE + ELOE + 16 + 1 + + + EPE + EPE + 17 + 1 + + + EWE + EWE + 18 + 1 + + + BOE + BOE + 19 + 1 + + + WDIE + WDIE + 20 + 1 + + + PEAE + PEAE + 21 + 1 + + + PEDE + PEDE + 22 + 1 + + + ARAE + ARAE + 23 + 1 + + + + + ILS + ILS + The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]. + 0x58 + 0x20 + read-write + 0x00000000 + + + RxFIFO0 + RxFIFO0 + 0 + 1 + + + RxFIFO1 + RxFIFO1 + 1 + 1 + + + SMSG + SMSG + 2 + 1 + + + TFERR + TFERR + 3 + 1 + + + MISC + MISC + 4 + 1 + + + BERR + BERR + 5 + 1 + + + PERR + PERR + 6 + 1 + + + + + ILE + ILE + Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1. + 0x5C + 0x20 + read-write + 0x00000000 + + + EINT0 + EINT0 + 0 + 1 + + + EINT1 + EINT1 + 1 + 1 + + + + + RXGFC + RXGFC + Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path. + 0x80 + 0x20 + 0x00000000 + + + RRFE + RRFE + 0 + 1 + read-write + + + RRFS + RRFS + 1 + 1 + read-write + + + ANFE + ANFE + 2 + 2 + read-write + + + ANFS + ANFS + 4 + 2 + read-write + + + F1OM + F1OM + 8 + 1 + read-write + + + F0OM + F0OM + 9 + 1 + read-write + + + LSS + LSS + 16 + 5 + read-write + + + LSE + LSE + 24 + 4 + read-write + + + + + XIDAM + XIDAM + FDCAN Extended ID and Mask Register + 0x84 + 0x20 + read-write + 0x1FFFFFFF + + + EIDM + EIDM + 0 + 29 + + + + + HPMS + HPMS + This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages. + 0x88 + 0x20 + read-only + 0x00000000 + + + BIDX + BIDX + 0 + 3 + + + MSI + MSI + 6 + 2 + + + FIDX + FIDX + 8 + 5 + + + FLST + FLST + 15 + 1 + + + + + RXF0S + RXF0S + FDCAN Rx FIFO 0 Status Register + 0x90 + 0x20 + read-only + 0x00000000 + + + F0FL + F0FL + 0 + 4 + + + F0GI + F0GI + 8 + 2 + + + F0PI + F0PI + 16 + 2 + + + F0F + F0F + 24 + 1 + + + RF0L + RF0L + 25 + 1 + + + + + RXF0A + RXF0A + CAN Rx FIFO 0 Acknowledge Register + 0x94 + 0x20 + read-write + 0x00000000 + + + F0AI + F0AI + 0 + 3 + + + + + RXF1S + RXF1S + FDCAN Rx FIFO 1 Status Register + 0x98 + 0x20 + read-only + 0x00000000 + + + F1FL + F1FL + 0 + 4 + + + F1GI + F1GI + 8 + 2 + + + F1PI + F1PI + 16 + 2 + + + F1F + F1F + 24 + 1 + + + RF1L + RF1L + 25 + 1 + + + + + RXF1A + RXF1A + FDCAN Rx FIFO 1 Acknowledge Register + 0x9C + 0x20 + read-write + 0x00000000 + + + F1AI + F1AI + 0 + 3 + + + + + TXBC + TXBC + FDCAN Tx Buffer Configuration Register + 0xC0 + 0x20 + read-write + 0x00000000 + + + TFQM + TFQM + 24 + 1 + + + + + TXFQS + TXFQS + The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated). + 0xC4 + 0x20 + read-only + 0x00000003 + + + TFFL + TFFL + 0 + 3 + + + TFGI + TFGI + 8 + 2 + + + TFQPI + TFQPI + 16 + 2 + + + TFQF + TFQF + 21 + 1 + + + + + TXBRP + TXBRP + FDCAN Tx Buffer Request Pending Register + 0xC8 + 0x20 + read-only + 0x00000000 + + + TRP + TRP + 0 + 3 + + + + + TXBAR + TXBAR + FDCAN Tx Buffer Add Request Register + 0xCC + 0x20 + read-write + 0x00000000 + + + AR + AR + 0 + 3 + + + + + TXBCR + TXBCR + FDCAN Tx Buffer Cancellation Request Register + 0xD0 + 0x20 + read-write + 0x00000000 + + + CR + CR + 0 + 3 + + + + + TXBTO + TXBTO + FDCAN Tx Buffer Transmission Occurred Register + 0xD4 + 0x20 + read-only + 0x00000000 + + + TO + TO + 0 + 3 + + + + + TXBCF + TXBCF + FDCAN Tx Buffer Cancellation Finished Register + 0xD8 + 0x20 + read-only + 0x00000000 + + + CF + CF + 0 + 3 + + + + + TXBTIE + TXBTIE + FDCAN Tx Buffer Transmission Interrupt Enable Register + 0xDC + 0x20 + read-write + 0x00000000 + + + TIE + TIE + 0 + 3 + + + + + TXBCIE + TXBCIE + FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register + 0xE0 + 0x20 + read-write + 0x00000000 + + + CFIE + CFIE + 0 + 3 + + + + + TXEFS + TXEFS + FDCAN Tx Event FIFO Status Register + 0xE4 + 0x20 + read-only + 0x00000000 + + + EFFL + EFFL + 0 + 3 + + + EFGI + EFGI + 8 + 2 + + + EFPI + EFPI + 16 + 2 + + + EFF + EFF + 24 + 1 + + + TEFL + TEFL + 25 + 1 + + + + + TXEFA + TXEFA + FDCAN Tx Event FIFO Acknowledge Register + 0xE8 + 0x20 + read-write + 0x00000000 + + + EFAI + EFAI + 0 + 2 + + + + + CKDIV + CKDIV + FDCAN CFG clock divider register + 0x100 + 0x20 + read-write + 0x00000000 + + + PDIV + input clock divider. the APB clock could be divided prior to be used by the CAN sub + 0 + 4 + + + + + + + FDCAN1 + 0x40006400 + + fdcan1_intr1_it + FDCAN1 interrupt + 21 + + + fdcan1_intr0_it + FDCAN1 interrupt + 22 + + + + FDCAN2 + 0x40006800 + + FDCAN2_intr0 + FDCAN2 interrupt + 86 + + + FDCAN2_intr1 + FDCAN2 interrupt + 87 + + + + FDCAN3 + 0x40006C00 + + FDCAN3_intr0 + FDCAN3 interrupt + 88 + + + FDCAN3_intr1 + FDCAN3 interrupt + 89 + + + + UCPD1 + UCPD1 + UCPD + 0x4000A000 + + 0x0 + 0x400 + registers + + + UCPD1 + UCPD1 + 63 + + + + CFG1 + CFG1 + UCPD configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + HBITCLKDIV + HBITCLKDIV + 0 + 6 + + + IFRGAP + IFRGAP + 6 + 5 + + + TRANSWIN + TRANSWIN + 11 + 5 + + + PSC_USBPDCLK + PSC_USBPDCLK + 17 + 3 + + + RXORDSETEN + RXORDSETEN + 20 + 9 + + + TXDMAEN + TXDMAEN + 29 + 1 + + + RXDMAEN + RXDMAEN + 30 + 1 + + + UCPDEN + UCPDEN + 31 + 1 + + + + + CFG2 + CFG2 + UCPD configuration register 2 + 0x4 + 0x20 + read-write + 0x00000000 + + + RXFILTDIS + RXFILTDIS + 0 + 1 + + + RXFILT2N3 + RXFILT2N3 + 1 + 1 + + + FORCECLK + FORCECLK + 2 + 1 + + + WUPEN + WUPEN + 3 + 1 + + + + + CR + CR + UCPD configuration register 2 + 0xC + 0x20 + read-write + 0x00000000 + + + TXMODE + TXMODE + 0 + 2 + + + TXSEND + TXSEND + 2 + 1 + + + TXHRST + TXHRST + 3 + 1 + + + RXMODE + RXMODE + 4 + 1 + + + PHYRXEN + PHYRXEN + 5 + 1 + + + PHYCCSEL + PHYCCSEL + 6 + 1 + + + ANASUBMODE + ANASUBMODE + 7 + 2 + + + ANAMODE + ANAMODE + 9 + 1 + + + CCENABLE + CCENABLE + 10 + 2 + + + FRSRXEN + FRSRXEN + 16 + 1 + + + FRSTX + FRSTX + 17 + 1 + + + RDCH + RDCH + 18 + 1 + + + CC1TCDIS + CC1TCDIS + 20 + 1 + + + CC2TCDIS + CC2TCDIS + 21 + 1 + + + + + IMR + IMR + UCPD Interrupt Mask Register + 0x10 + 0x20 + read-write + 0x00000000 + + + TXISIE + TXISIE + 0 + 1 + + + TXMSGDISCIE + TXMSGDISCIE + 1 + 1 + + + TXMSGSENTIE + TXMSGSENTIE + 2 + 1 + + + TXMSGABTIE + TXMSGABTIE + 3 + 1 + + + HRSTDISCIE + HRSTDISCIE + 4 + 1 + + + HRSTSENTIE + HRSTSENTIE + 5 + 1 + + + TXUNDIE + TXUNDIE + 6 + 1 + + + RXNEIE + RXNEIE + 8 + 1 + + + RXORDDETIE + RXORDDETIE + 9 + 1 + + + RXHRSTDETIE + RXHRSTDETIE + 10 + 1 + + + RXOVRIE + RXOVRIE + 11 + 1 + + + RXMSGENDIE + RXMSGENDIE + 12 + 1 + + + TYPECEVT1IE + TYPECEVT1IE + 14 + 1 + + + TYPECEVT2IE + TYPECEVT2IE + 15 + 1 + + + FRSEVTIE + FRSEVTIE + 20 + 1 + + + + + SR + SR + UCPD Status Register + 0x14 + 0x20 + read-write + 0x00000000 + + + TXIS + TXIS + 0 + 1 + + + TXMSGDISC + TXMSGDISC + 1 + 1 + + + TXMSGSENT + TXMSGSENT + 2 + 1 + + + TXMSGABT + TXMSGABT + 3 + 1 + + + HRSTDISC + HRSTDISC + 4 + 1 + + + HRSTSENT + HRSTSENT + 5 + 1 + + + TXUND + TXUND + 6 + 1 + + + RXNE + RXNE + 8 + 1 + + + RXORDDET + RXORDDET + 9 + 1 + + + RXHRSTDET + RXHRSTDET + 10 + 1 + + + RXOVR + RXOVR + 11 + 1 + + + RXMSGEND + RXMSGEND + 12 + 1 + + + RXERR + RXERR + 13 + 1 + + + TYPECEVT1 + TYPECEVT1 + 14 + 1 + + + TYPECEVT2 + TYPECEVT2 + 15 + 1 + + + TYPEC_VSTATE_CC1 + TYPEC_VSTATE_CC1 + 16 + 2 + + + TYPEC_VSTATE_CC2 + TYPEC_VSTATE_CC2 + 18 + 2 + + + FRSEVT + FRSEVT + 20 + 1 + + + + + ICR + ICR + UCPD Interrupt Clear Register + 0x18 + 0x20 + read-write + 0x00000000 + + + TXMSGDISCCF + TXMSGDISCCF + 1 + 1 + + + TXMSGSENTCF + TXMSGSENTCF + 2 + 1 + + + TXMSGABTCF + TXMSGABTCF + 3 + 1 + + + HRSTDISCCF + HRSTDISCCF + 4 + 1 + + + HRSTSENTCF + HRSTSENTCF + 5 + 1 + + + TXUNDCF + TXUNDCF + 6 + 1 + + + RXORDDETCF + RXORDDETCF + 9 + 1 + + + RXHRSTDETCF + RXHRSTDETCF + 10 + 1 + + + RXOVRCF + RXOVRCF + 11 + 1 + + + RXMSGENDCF + RXMSGENDCF + 12 + 1 + + + TYPECEVT1CF + TYPECEVT1CF + 14 + 1 + + + TYPECEVT2CF + TYPECEVT2CF + 15 + 1 + + + FRSEVTCF + FRSEVTCF + 20 + 1 + + + + + TX_ORDSET + TX_ORDSET + UCPD Tx Ordered Set Type Register + 0x1C + 0x20 + read-write + 0x00000000 + + + TXORDSET + TXORDSET + 0 + 20 + + + + + TX_PAYSZ + TX_PAYSZ + UCPD Tx Paysize Register + 0x20 + 0x20 + read-write + 0x00000000 + + + TXPAYSZ + TXPAYSZ + 0 + 10 + + + + + TXDR + TXDR + UCPD Tx Data Register + 0x24 + 0x20 + read-write + 0x00000000 + + + TXDATA + TXDATA + 0 + 8 + + + + + RX_ORDSET + RX_ORDSET + UCPD Rx Ordered Set Register + 0x28 + 0x20 + read-only + 0x00000000 + + + RXORDSET + RXORDSET + 0 + 3 + + + RXSOP3OF4 + RXSOP3OF4 + 3 + 1 + + + RXSOPKINVALID + RXSOPKINVALID + 4 + 3 + + + + + RX_PAYSZ + RX_PAYSZ + UCPD Rx Paysize Register + 0x2C + 0x20 + read-only + 0x00000000 + + + RXPAYSZ + RXPAYSZ + 0 + 10 + + + + + RXDR + RXDR + UCPD Rx Data Register + 0x30 + 0x20 + read-only + 0x00000000 + + + RXDATA + RXDATA + 0 + 8 + + + + + RX_ORDEXT1 + RX_ORDEXT1 + UCPD Rx Ordered Set Extension Register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + RXSOPX1 + RXSOPX1 + 0 + 20 + + + + + RX_ORDEXT2 + RX_ORDEXT2 + UCPD Rx Ordered Set Extension Register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + RXSOPX2 + RXSOPX2 + 0 + 20 + + + + + + + USB_FS_device + USB_FS_device + USB + 0x40005C00 + + 0x0 + 0x400 + registers + + + + EP0R + EP0R + USB endpoint n register + 0x0 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP1R + EP1R + USB endpoint n register + 0x4 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP2R + EP2R + USB endpoint n register + 0x8 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP3R + EP3R + USB endpoint n register + 0xC + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP4R + EP4R + USB endpoint n register + 0x10 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP5R + EP5R + USB endpoint n register + 0x14 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP6R + EP6R + USB endpoint n register + 0x18 + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + EP7R + EP7R + USB endpoint n register + 0x1C + 0x20 + read-write + 0x00000000 + + + EA + EA + 0 + 4 + + + STAT_TX + STAT_TX + 4 + 2 + + + DTOG_TX + DTOG_TX + 6 + 1 + + + CTR_TX + CTR_TX + 7 + 1 + + + EP_KIND + EP_KIND + 8 + 1 + + + EP_TYPE + EP_TYPE + 9 + 2 + + + SETUP + SETUP + 11 + 1 + + + STAT_RX + STAT_RX + 12 + 2 + + + DTOG_RX + DTOG_RX + 14 + 1 + + + CTR_RX + CTR_RX + 15 + 1 + + + + + CNTR + CNTR + USB control register + 0x40 + 0x20 + read-write + 0x00000000 + + + FRES + FRES + 0 + 1 + + + PDWN + PDWN + 1 + 1 + + + LP_MODE + LP_MODE + 2 + 1 + + + FSUSP + FSUSP + 3 + 1 + + + RESUME + RESUME + 4 + 1 + + + L1RESUME + L1RESUME + 5 + 1 + + + L1REQM + L1REQM + 7 + 1 + + + ESOFM + ESOFM + 8 + 1 + + + SOFM + SOFM + 9 + 1 + + + RESETM + RESETM + 10 + 1 + + + SUSPM + SUSPM + 11 + 1 + + + WKUPM + WKUPM + 12 + 1 + + + ERRM + ERRM + 13 + 1 + + + PMAOVRM + PMAOVRM + 14 + 1 + + + CTRM + CTRM + 15 + 1 + + + + + ISTR + ISTR + USB interrupt status register + 0x44 + 0x20 + read-write + 0x00000000 + + + EP_ID + EP_ID + 0 + 4 + + + DIR + DIR + 4 + 1 + + + L1REQ + L1REQ + 7 + 1 + + + ESOF + ESOF + 8 + 1 + + + SOF + SOF + 9 + 1 + + + RESET + RESET + 10 + 1 + + + SUSP + SUSP + 11 + 1 + + + WKUP + WKUP + 12 + 1 + + + ERR + ERR + 13 + 1 + + + PMAOVR + PMAOVR + 14 + 1 + + + CTR + CTR + 15 + 1 + + + + + FNR + FNR + USB frame number register + 0x48 + 0x20 + read-only + 0x00000000 + + + FN + FN + 0 + 11 + + + LSOF + LSOF + 11 + 2 + + + LCK + LCK + 13 + 1 + + + RXDM + RXDM + 14 + 1 + + + RXDP + RXDP + 15 + 1 + + + + + DADDR + DADDR + USB device address + 0x4C + 0x20 + read-write + 0x00000000 + + + ADD + ADD + 0 + 7 + + + EF + EF + 7 + 1 + + + + + BTABLE + BTABLE + Buffer table address + 0x50 + 0x20 + read-write + 0x00000000 + + + BTABLE + BTABLE + 3 + 13 + + + + + + + CRS + CRS + CRS + 0x40002000 + + 0x0 + 0x400 + registers + + + + CR + CR + CRS control register + 0x0 + 0x20 + 0x00004000 + + + SYNCOKIE + SYNC event OK interrupt enable + 0 + 1 + read-write + + + SYNCWARNIE + SYNC warning interrupt enable + 1 + 1 + read-write + + + ERRIE + Synchronization or trimming error interrupt enable + 2 + 1 + read-write + + + ESYNCIE + Expected SYNC interrupt enable + 3 + 1 + read-write + + + CEN + Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified. + 5 + 1 + read-write + + + AUTOTRIMEN + Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details. + 6 + 1 + read-write + + + SWSYNC + Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware. + 7 + 1 + read-write + + + TRIM + HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only. + 8 + 7 + read-write + + + + + CFGR + CFGR + This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected. + 0x4 + 0x20 + read-write + 0x2022BB7F + + + RELOAD + Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior. + 0 + 16 + + + FELIM + Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation. + 16 + 8 + + + SYNCDIV + SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal. + 24 + 3 + + + SYNCSRC + SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal. + 28 + 2 + + + SYNCPOL + SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source. + 31 + 1 + + + + + ISR + ISR + CRS interrupt and status register + 0x8 + 0x20 + read-only + 0x00000000 + + + SYNCOKF + SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register. + 0 + 1 + + + SYNCWARNF + SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register. + 1 + 1 + + + ERRF + Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits. + 2 + 1 + + + ESYNCF + Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register. + 3 + 1 + + + SYNCERR + SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 8 + 1 + + + SYNCMISS + SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 9 + 1 + + + TRIMOVF + Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register. + 10 + 1 + + + FEDIR + Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target. + 15 + 1 + + + FECAP + Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage. + 16 + 16 + + + + + ICR + ICR + CRS interrupt flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + SYNCOKC + SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register. + 0 + 1 + + + SYNCWARNC + SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register. + 1 + 1 + + + ERRC + Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register. + 2 + 1 + + + ESYNCC + Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register. + 3 + 1 + + + + + + + diff --git a/stm32g474_dac_dma_demo.ioc b/stm32g474_dac_dma_demo.ioc index cf53251..b65394f 100644 --- a/stm32g474_dac_dma_demo.ioc +++ b/stm32g474_dac_dma_demo.ioc @@ -2,18 +2,16 @@ CAD.formats= CAD.pinconfig= CAD.provider= -DAC4.DAC_Channel-DAC_OUT2_Int=DAC_CHANNEL_2 -DAC4.DAC_HighFrequency_OUT1-DAC_OUT1_Int=DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ +DAC4.DAC_HighFrequency_OUT1-DAC_OUT1_Int=DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC DAC4.DAC_Trigger_OUT1-DAC_OUT1_Int=DAC_TRIGGER_T7_TRGO -DAC4.DAC_Trigger_OUT2-DAC_OUT2_Int=DAC_TRIGGER_T7_TRGO -DAC4.IPParameters=DAC_Channel-DAC_OUT2_Int,DAC_HighFrequency_OUT1-DAC_OUT1_Int,DAC_Trigger_OUT1-DAC_OUT1_Int,DAC_Trigger_OUT2-DAC_OUT2_Int +DAC4.IPParameters=DAC_HighFrequency_OUT1-DAC_OUT1_Int,DAC_Trigger_OUT1-DAC_OUT1_Int Dma.DAC4_CH1.0.Direction=DMA_MEMORY_TO_PERIPH Dma.DAC4_CH1.0.EventEnable=DISABLE Dma.DAC4_CH1.0.Instance=DMA1_Channel1 Dma.DAC4_CH1.0.MemDataAlignment=DMA_MDATAALIGN_HALFWORD Dma.DAC4_CH1.0.MemInc=DMA_MINC_ENABLE Dma.DAC4_CH1.0.Mode=DMA_CIRCULAR -Dma.DAC4_CH1.0.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.DAC4_CH1.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD Dma.DAC4_CH1.0.PeriphInc=DMA_PINC_DISABLE Dma.DAC4_CH1.0.Polarity=HAL_DMAMUX_REQ_GEN_RISING Dma.DAC4_CH1.0.Priority=DMA_PRIORITY_LOW @@ -24,26 +22,8 @@ Dma.DAC4_CH1.0.SyncEnable=DISABLE Dma.DAC4_CH1.0.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.DAC4_CH1.0.SyncRequestNumber=1 Dma.DAC4_CH1.0.SyncSignalID=NONE -Dma.DAC4_CH2.1.Direction=DMA_MEMORY_TO_PERIPH -Dma.DAC4_CH2.1.EventEnable=DISABLE -Dma.DAC4_CH2.1.Instance=DMA1_Channel2 -Dma.DAC4_CH2.1.MemDataAlignment=DMA_MDATAALIGN_HALFWORD -Dma.DAC4_CH2.1.MemInc=DMA_MINC_ENABLE -Dma.DAC4_CH2.1.Mode=DMA_CIRCULAR -Dma.DAC4_CH2.1.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD -Dma.DAC4_CH2.1.PeriphInc=DMA_PINC_DISABLE -Dma.DAC4_CH2.1.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.DAC4_CH2.1.Priority=DMA_PRIORITY_LOW -Dma.DAC4_CH2.1.RequestNumber=1 -Dma.DAC4_CH2.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.DAC4_CH2.1.SignalID=NONE -Dma.DAC4_CH2.1.SyncEnable=DISABLE -Dma.DAC4_CH2.1.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.DAC4_CH2.1.SyncRequestNumber=1 -Dma.DAC4_CH2.1.SyncSignalID=NONE Dma.Request0=DAC4_CH1 -Dma.Request1=DAC4_CH2 -Dma.RequestsNb=2 +Dma.RequestsNb=1 File.Version=6 KeepUserPlacement=false LPUART1.BaudRate=115200 @@ -56,23 +36,20 @@ Mcu.IP1=DMA Mcu.IP2=LPUART1 Mcu.IP3=NVIC Mcu.IP4=OPAMP4 -Mcu.IP5=OPAMP5 -Mcu.IP6=RCC -Mcu.IP7=SYS -Mcu.IP8=TIM7 -Mcu.IPNb=9 +Mcu.IP5=RCC +Mcu.IP6=SYS +Mcu.IP7=TIM7 +Mcu.IPNb=8 Mcu.Name=STM32G474R(B-C-E)Tx Mcu.Package=LQFP64 Mcu.Pin0=PC13 Mcu.Pin1=PC14-OSC32_IN -Mcu.Pin10=PA13 -Mcu.Pin11=PA14 -Mcu.Pin12=PB3 -Mcu.Pin13=VP_DAC4_VS_DACI1 -Mcu.Pin14=VP_DAC4_VS_DACI2 -Mcu.Pin15=VP_SYS_VS_Systick -Mcu.Pin16=VP_SYS_VS_DBSignals -Mcu.Pin17=VP_TIM7_VS_ClockSourceINT +Mcu.Pin10=PA14 +Mcu.Pin11=PB3 +Mcu.Pin12=VP_DAC4_VS_DACI1 +Mcu.Pin13=VP_SYS_VS_Systick +Mcu.Pin14=VP_SYS_VS_DBSignals +Mcu.Pin15=VP_TIM7_VS_ClockSourceINT Mcu.Pin2=PC15-OSC32_OUT Mcu.Pin3=PF0-OSC_IN Mcu.Pin4=PF1-OSC_OUT @@ -80,8 +57,8 @@ Mcu.Pin5=PA2 Mcu.Pin6=PA3 Mcu.Pin7=PA5 Mcu.Pin8=PB12 -Mcu.Pin9=PA8 -Mcu.PinsNb=18 +Mcu.Pin9=PA13 +Mcu.PinsNb=16 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32G474RETx @@ -89,7 +66,6 @@ MxCube.Version=6.9.2 MxDb.Version=DB.6.0.92 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DMA1_Channel1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true -NVIC.DMA1_Channel2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.ForceEnableDMAVector=true @@ -100,11 +76,10 @@ NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false +NVIC.TIM7_DAC_IRQn=true\:0\:0\:false\:true\:true\:3\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false OPAMP4.IPParameters=PowerMode OPAMP4.PowerMode=OPAMP_POWERMODE_HIGHSPEED -OPAMP5.IPParameters=PowerMode -OPAMP5.PowerMode=OPAMP_POWERMODE_HIGHSPEED PA13.GPIOParameters=GPIO_Label PA13.GPIO_Label=T_SWDIO PA13.Locked=true @@ -129,8 +104,6 @@ PA5.GPIOParameters=GPIO_Label PA5.GPIO_Label=LD2 [green led] PA5.Locked=true PA5.Signal=GPIO_Output -PA8.Mode=Follower-DAC_OUT2-INP -PA8.Signal=OPAMP5_VOUT PB12.Mode=Follower-DAC_OUT2-INP PB12.Signal=OPAMP4_VOUT PB3.GPIOParameters=GPIO_Label @@ -184,7 +157,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_DAC4_Init-DAC4-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_OPAMP4_Init-OPAMP4-false-HAL-true,7-MX_OPAMP5_Init-OPAMP5-false-HAL-true,8-MX_TIM7_Init-TIM7-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_DAC4_Init-DAC4-false-HAL-true,5-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,6-MX_OPAMP4_Init-OPAMP4-false-HAL-true,7-MX_TIM7_Init-TIM7-false-HAL-true RCC.ADC12Freq_Value=170000000 RCC.ADC345Freq_Value=170000000 RCC.AHBFreq_Value=170000000 @@ -239,13 +212,12 @@ RCC.VCOOutputFreq_Value=340000000 SH.GPXTI13.0=GPIO_EXTI13 SH.GPXTI13.ConfNb=1 TIM7.AutoReloadPreload=TIM_AUTORELOAD_PRELOAD_ENABLE -TIM7.IPParameters=PeriodNoDither,TIM_MasterOutputTrigger,AutoReloadPreload +TIM7.IPParameters=PeriodNoDither,TIM_MasterOutputTrigger,AutoReloadPreload,Prescaler TIM7.PeriodNoDither=170-1 +TIM7.Prescaler=1000 TIM7.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE VP_DAC4_VS_DACI1.Mode=DAC_OUT1_Int VP_DAC4_VS_DACI1.Signal=DAC4_VS_DACI1 -VP_DAC4_VS_DACI2.Mode=DAC_OUT2_Int -VP_DAC4_VS_DACI2.Signal=DAC4_VS_DACI2 VP_SYS_VS_DBSignals.Mode=DisableDeadBatterySignals VP_SYS_VS_DBSignals.Signal=SYS_VS_DBSignals VP_SYS_VS_Systick.Mode=SysTick