462 lines
		
	
	
		
			16 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			462 lines
		
	
	
		
			16 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /**
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|   ******************************************************************************
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|   * @file    stm32f3xx_hal_pwr.c
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|   * @author  MCD Application Team
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|   * @brief   PWR HAL module driver.
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|   *          This file provides firmware functions to manage the following
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|   *          functionalities of the Power Controller (PWR) peripheral:
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|   *           + Initialization/de-initialization functions
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|   *           + Peripheral Control functions
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|   *
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|   @verbatim
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|   ******************************************************************************
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|   * @attention
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|   *
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|   * <h2><center>© Copyright (c) 2016 STMicroelectronics.
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|   * All rights reserved.</center></h2>
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|   *
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|   * This software component is licensed by ST under BSD 3-Clause license,
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|   * the "License"; You may not use this file except in compliance with the
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|   * License. You may obtain a copy of the License at:
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|   *                        opensource.org/licenses/BSD-3-Clause
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|   *
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|   ******************************************************************************
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|   */
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| 
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| /* Includes ------------------------------------------------------------------*/
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| #include "stm32f3xx_hal.h"
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| 
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| /** @addtogroup STM32F3xx_HAL_Driver
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|   * @{
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|   */
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| 
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| /** @defgroup PWR PWR
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|   * @brief PWR HAL module driver
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|   * @{
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|   */
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| 
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| #ifdef HAL_PWR_MODULE_ENABLED
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| 
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| /* Private typedef -----------------------------------------------------------*/
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| /* Private define ------------------------------------------------------------*/
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| /* Private macro -------------------------------------------------------------*/
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| /* Private variables ---------------------------------------------------------*/
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| /* Private function prototypes -----------------------------------------------*/
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| /* Private functions ---------------------------------------------------------*/
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| 
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| /** @defgroup PWR_Exported_Functions PWR Exported Functions
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|   * @{
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|   */
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| 
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| /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
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|   *  @brief    Initialization and de-initialization functions
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|   *
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| @verbatim
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|  ===============================================================================
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|               ##### Initialization and de-initialization functions #####
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|  ===============================================================================
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|     [..]
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|       After reset, the backup domain (RTC registers, RTC backup data
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|       registers and backup SRAM) is protected against possible unwanted
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|       write accesses.
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|       To enable access to the RTC Domain and RTC registers, proceed as follows:
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|         (+) Enable the Power Controller (PWR) APB1 interface clock using the
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|             __HAL_RCC_PWR_CLK_ENABLE() macro.
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|         (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
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| 
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| @endverbatim
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|   * @{
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|   */
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| 
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| /**
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|   * @brief Deinitializes the PWR peripheral registers to their default reset values.
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|   * @retval None
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|   */
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| void HAL_PWR_DeInit(void)
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| {
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|   __HAL_RCC_PWR_FORCE_RESET();
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|   __HAL_RCC_PWR_RELEASE_RESET();
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| }
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| 
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| /**
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|   * @brief Enables access to the backup domain (RTC registers, RTC
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|   *         backup data registers and backup SRAM).
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|   * @note  If the HSE divided by 32 is used as the RTC clock, the
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|   *         Backup Domain Access should be kept enabled.
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|   * @retval None
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|   */
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| void HAL_PWR_EnableBkUpAccess(void)
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| {
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|   SET_BIT(PWR->CR, PWR_CR_DBP);  
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| }
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| 
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| /**
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|   * @brief Disables access to the backup domain (RTC registers, RTC
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|   *         backup data registers and backup SRAM).
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|   * @note  If the HSE divided by 32 is used as the RTC clock, the
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|   *         Backup Domain Access should be kept enabled.
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|   * @retval None
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|   */
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| void HAL_PWR_DisableBkUpAccess(void)
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| {
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|   CLEAR_BIT(PWR->CR, PWR_CR_DBP);  
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| }
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| 
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| /**
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|   * @}
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|   */
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| 
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| /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
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|   *  @brief Low Power modes configuration functions
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|   *
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| @verbatim
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| 
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|  ===============================================================================
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|                  ##### Peripheral Control functions #####
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|  ===============================================================================
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|     
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|     *** WakeUp pin configuration ***
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|     ================================
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|     [..]
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|       (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
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|           forced in input pull down configuration and is active on rising edges.
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|       (+) There are up to three WakeUp pins:
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|           (++)WakeUp Pin 1 on PA.00.
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|           (++)WakeUp Pin 2 on PC.13 (STM32F303xC, STM32F303xE only).
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|           (++)WakeUp Pin 3 on PE.06.
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| 
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|     *** Main and Backup Regulators configuration ***
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|     ================================================
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|     [..]
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|       (+) When the backup domain is supplied by VDD (analog switch connected to VDD)
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|           the backup SRAM is powered from VDD which replaces the VBAT power supply to
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|           save battery life.
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| 
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|       (+) The backup SRAM is not mass erased by a tamper event. It is read
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|           protected to prevent confidential data, such as cryptographic private
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|           key, from being accessed. The backup SRAM can be erased only through
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|           the Flash interface when a protection level change from level 1 to
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|           level 0 is requested.
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|       -@- Refer to the description of Read protection (RDP) in the Flash
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|           programming manual.
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| 
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|         Refer to the datasheets for more details.
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| 
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|     *** Low Power modes configuration ***
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|     =====================================
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|     [..]
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|       The devices feature 3 low-power modes:
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|       (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
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|       (+) Stop mode: all clocks are stopped, regulator running, regulator
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|           in low power mode
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|       (+) Standby mode: 1.2V domain powered off (mode not available on STM32F3x8 devices).
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| 
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|    *** Sleep mode ***
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|    ==================
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|     [..]
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|       (+) Entry:
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|           The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
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|               functions with
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|           (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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|           (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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|      
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|       (+) Exit:
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|         (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
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|               controller (NVIC) can wake up the device from Sleep mode.
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| 
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|    *** Stop mode ***
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|    =================
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|     [..]
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|       In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI,
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|       and the HSE RC oscillators are disabled. Internal SRAM and register contents
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|       are preserved.
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|       The voltage regulator can be configured either in normal or low-power mode to minimize the consumption.
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| 
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|       (+) Entry:
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|           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI )
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|              function with:
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|           (++) Main regulator ON or
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|           (++) Low Power regulator ON.
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|           (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction or
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|           (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction
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|       (+) Exit:
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|           (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
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|           (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, 
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|                when programmed in wakeup mode (the peripheral must be 
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|                programmed in wakeup mode and the corresponding interrupt vector 
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|                must be enabled in the NVIC).
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| 
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|    *** Standby mode ***
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|    ====================
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|      [..]
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|       The Standby mode allows to achieve the lowest power consumption. It is based
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|       on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
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|       The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and
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|       the HSE oscillator are also switched off. SRAM and register contents are lost
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|       except for the RTC registers, RTC backup registers, backup SRAM and Standby
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|       circuitry.
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|       The voltage regulator is OFF.
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| 
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|       (+) Entry:
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|           (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
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|       (+) Exit:
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|           (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
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|                tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
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| 
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|    *** Auto-wakeup (AWU) from low-power mode ***
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|    =============================================
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|     [..]
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|       The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
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|       Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
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|       without depending on an external interrupt (Auto-wakeup mode).
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| 
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|     (+) RTC auto-wakeup (AWU) from the Stop and Standby modes
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| 
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|       (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
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|             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
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| 
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|       (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
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|            is necessary to configure the RTC to detect the tamper or time stamp event using the
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|            HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions.
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| 
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|       (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
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|            configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function.
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| 
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|     (+) Comparator auto-wakeup (AWU) from the Stop mode
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| 
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|       (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to:
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|            (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2U) 
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|                  to be sensitive to to the selected edges (falling, rising or falling 
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|                  and rising) (Interrupt or Event modes) using the EXTI_Init() function.
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|            (+++) Configure the comparator to generate the event.      
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| @endverbatim
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|   * @{
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|   */
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| 
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| /**
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|   * @brief Enables the WakeUp PINx functionality.
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|   * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
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|   *         This parameter can be value of :
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|   *           @ref PWR_WakeUp_Pins
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|   * @retval None
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|   */
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| void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
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| {
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|   /* Check the parameters */
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|   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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|   /* Enable the EWUPx pin */
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|   SET_BIT(PWR->CSR, WakeUpPinx);
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| }
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| 
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| /**
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|   * @brief Disables the WakeUp PINx functionality.
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|   * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
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|   *         This parameter can be values of :
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|   *           @ref PWR_WakeUp_Pins
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|   * @retval None
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|   */
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| void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
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| {
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|   /* Check the parameters */
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|   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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|   /* Disable the EWUPx pin */
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|   CLEAR_BIT(PWR->CSR, WakeUpPinx);
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| }
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| 
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| /**
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|   * @brief Enters Sleep mode.
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|   * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
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|   * @param Regulator Specifies the regulator state in SLEEP mode.
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|   *          This parameter can be one of the following values:
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|   *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
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|   *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
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|   * @note This parameter has no effect in F3 family and is just maintained to 
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|   *       offer full portability of other STM32 families softwares.
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|   * @param SLEEPEntry Specifies if SLEEP mode is entered with WFI or WFE instruction.
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|   *           When WFI entry is used, tick interrupt have to be disabled if not desired as 
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|   *           the interrupt wake up source.
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|   *           This parameter can be one of the following values:
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|   *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
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|   *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
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|   * @retval None
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|   */
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| void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
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| {
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|   /* Check the parameters */
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|   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
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| 
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|   /* Clear SLEEPDEEP bit of Cortex System Control Register */
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|   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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| 
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|   /* Select SLEEP mode entry -------------------------------------------------*/
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|   if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
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|   {
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|     /* Request Wait For Interrupt */
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|     __WFI();
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|   }
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|   else
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|   {
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|     /* Request Wait For Event */
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|     __SEV();
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|     __WFE();
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|     __WFE();
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|   }
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| }
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| 
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| /**
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|   * @brief Enters STOP mode.
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|   * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
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|   * @note  When exiting Stop mode by issuing an interrupt or a wakeup event,
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|   *         the HSI RC oscillator is selected as system clock.
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|   * @note  When the voltage regulator operates in low power mode, an additional
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|   *         startup delay is incurred when waking up from Stop mode.
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|   *         By keeping the internal regulator ON during Stop mode, the consumption
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|   *         is higher although the startup time is reduced.
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|   * @param Regulator Specifies the regulator state in STOP mode.
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|   *          This parameter can be one of the following values:
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|   *            @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON
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|   *            @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON
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|   * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
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|   *          This parameter can be one of the following values:
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|   *            @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction
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|   *            @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction
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|   * @retval None
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|   */
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| void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
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| {
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|   uint32_t tmpreg = 0U;
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| 
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|   /* Check the parameters */
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|   assert_param(IS_PWR_REGULATOR(Regulator));
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|   assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
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| 
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|   /* Select the regulator state in STOP mode ---------------------------------*/
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|   tmpreg = PWR->CR;
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|   
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|   /* Clear PDDS and LPDS bits */
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|   tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS);
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| 
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|   /* Set LPDS bit according to Regulator value */
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|   tmpreg |= Regulator;
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| 
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|   /* Store the new value */
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|   PWR->CR = tmpreg;
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| 
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|   /* Set SLEEPDEEP bit of Cortex System Control Register */
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|   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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| 
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|   /* Select STOP mode entry --------------------------------------------------*/
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|   if(STOPEntry == PWR_STOPENTRY_WFI)
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|   {
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|     /* Request Wait For Interrupt */
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|     __WFI();
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|   }
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|   else
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|   {
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|     /* Request Wait For Event */
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|     __SEV();
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|     __WFE();
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|     __WFE();
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|   }
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| 
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|   /* Reset SLEEPDEEP bit of Cortex System Control Register */
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|   SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
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| }
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| 
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| /**
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|   * @brief Enters STANDBY mode.
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|   * @note  In Standby mode, all I/O pins are high impedance except for:
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|   *          - Reset pad (still available), 
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|   *          - RTC alternate function pins if configured for tamper, time-stamp, RTC
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|   *            Alarm out, or RTC clock calibration out, 
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|   *          - WKUP pins if enabled.
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|   * @retval None
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|   */
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| void HAL_PWR_EnterSTANDBYMode(void)
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| {
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|   /* Select STANDBY mode */
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|   PWR->CR |= PWR_CR_PDDS;
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| 
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|   /* Set SLEEPDEEP bit of Cortex System Control Register */
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|   SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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| 
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|   /* This option is used to ensure that store operations are completed */
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| #if defined ( __CC_ARM)
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|   __force_stores();
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| #endif
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|   /* Request Wait For Interrupt */
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|   __WFI();
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| }
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| 
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| /**
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|   * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
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|   * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
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|   *       re-enters SLEEP mode when an interruption handling is over.
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|   *       Setting this bit is useful when the processor is expected to run only on
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|   *       interruptions handling.         
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|   * @retval None
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|   */
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| void HAL_PWR_EnableSleepOnExit(void)
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| {
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|   /* Set SLEEPONEXIT bit of Cortex System Control Register */
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|   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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| }
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| 
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| 
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| /**
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|   * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
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|   * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
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|   *       re-enters SLEEP mode when an interruption handling is over.          
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|   * @retval None
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|   */
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| void HAL_PWR_DisableSleepOnExit(void)
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| {
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|   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
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|   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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| }
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| 
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| 
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| 
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| /**
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|   * @brief Enables CORTEX M4 SEVONPEND bit. 
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|   * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
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|   *       WFE to wake up when an interrupt moves from inactive to pended.
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|   * @retval None
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|   */
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| void HAL_PWR_EnableSEVOnPend(void)
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| {
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|   /* Set SEVONPEND bit of Cortex System Control Register */
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|   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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| }
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| 
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| 
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| /**
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|   * @brief Disables CORTEX M4 SEVONPEND bit. 
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|   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
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|   *       WFE to wake up when an interrupt moves from inactive to pended.         
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|   * @retval None
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|   */
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| void HAL_PWR_DisableSEVOnPend(void)
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| {
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|   /* Clear SEVONPEND bit of Cortex System Control Register */
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|   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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| }
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| /**
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|   * @}
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|   */
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| 
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| /**
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|   * @}
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|   */
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| 
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| #endif /* HAL_PWR_MODULE_ENABLED */
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| /**
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|   * @}
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|   */
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| 
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| /**
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|   * @}
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|   */
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| 
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| /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 |