# Przegląd Konfiguracji Mesa 7i92T (firmware_versions.md) Ten plik zawiera zestawienie wszystkich dostępnych konfiguracji firmware dla karty Mesa 7i92T/7i92TF. Karta posiada dwa złącza rozszerzeń: **P2** (fizyczny, żeński port DB25 na śledziu) oraz **P1** (wewnętrzny pinheader 26-pin 2x13). ## Tabela Porównawcza Konfiguracji | Nazwa Pliku (.bin / .pin) | Port P2 (DB25 Female) | Port P1 (IDC26) | StepGen | Enkodery | PWM | | :--- | :--- | :--- | :---: | :---: | :---: | | [7i92t_5abob_encd](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_5abob_encd.pin) | **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2, Enkoder (QCount): 1) | **5-axis BOB (5ABOB)** (Enkoder (QCount): 5) | 5 | 6 | 1 | | [7i92t_5abobx2d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_5abobx2d.pin) | **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2, Enkoder (QCount): 1) | **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2, Enkoder (QCount): 1) | 10 | 2 | 2 | | [7i92t_7i76_7i74d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i76_7i74d.pin) | **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | **Mesa 7i76** (Smart Serial (SSerial): 8) | 5 | 1 | 0 | | [7i92t_7i76_7i85d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i76_7i85d.pin) | **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | **Mesa 7i76** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) | 5 | 0 | 0 | | [7i92t_7i76_7i85sd](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i76_7i85sd.pin) | **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | **Mesa 7i76** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) | 9 | 0 | 0 | | [7i92t_7i76_g540d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i76_g540d.pin) | **Gecko G540** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | **Gecko G540** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | 10 | 2 | 1 | | [7i92t_7i76x1pd](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i76x1pd.pin) | **Mesa 7i76** (StepGen: 4, PWM: 2, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | **Mesa 7i76** | 4 | 1 | 1 | | [7i92t_7i76x2d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i76x2d.pin) | **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | 10 | 2 | 0 | | [7i92t_7i77_7i74d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i77_7i74d.pin) | **Mesa 7i77 (Analog)** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) | **Mesa 7i77 (Analog)** (Smart Serial (SSerial): 8) | 0 | 0 | 0 | | [7i92t_7i77_7i761pd](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i77_7i761pd.pin) | **Mesa 7i76** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) | **Mesa 7i76** (StepGen: 4, PWM: 2, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | 4 | 0 | 1 | | [7i92t_7i77_7i76d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i77_7i76d.pin) | **Mesa 7i76** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) | **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | 5 | 0 | 0 | | [7i92t_7i77x2d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i77x2d.pin) | **Mesa 7i77 (Analog)** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) | **Mesa 7i77 (Analog)** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) | 0 | 0 | 0 | | [7i92t_7i78x2d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i78x2d.pin) | **Mesa 7i78** (StepGen: 4, PWM: 4, Enkoder (QCount): 1, Smart Serial (SSerial): 1) | **Mesa 7i78** (StepGen: 4, PWM: 4, Enkoder (QCount): 1, Smart Serial (SSerial): 1) | 8 | 2 | 2 | | [7i92t_7i85_g540d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i85_g540d.pin) | **Gecko G540** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) | **Gecko G540** (StepGen: 4, PWM: 2) | 5 | 0 | 1 | | [7i92t_7i85s_4pwm](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i85s_4pwm.pin) | **Mesa 7i85 / 7i85S** (PWM: 12, Enkoder (QCount): 2, Smart Serial (SSerial): 1) | **Mesa 7i85 / 7i85S** | 0 | 0 | 4 | | [7i92t_7i85s_5abobd](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i85s_5abobd.pin) | **5-axis BOB (5ABOB)** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) | **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2) | 9 | 0 | 1 | | [7i92t_7i85sx2d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i85sx2d.pin) | **Mesa 7i85 / 7i85S** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) | **Mesa 7i85 / 7i85S** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) | 8 | 0 | 0 | | [7i92t_7i85x2d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_7i85x2d.pin) | **Mesa 7i85 / 7i85S** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) | **Mesa 7i85 / 7i85S** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) | 0 | 0 | 0 | | [7i92t_benezan_5abobd](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_benezan_5abobd.pin) | **5-axis BOB (5ABOB)** (StepGen: 4, PWM: 2) | **5-axis BOB (5ABOB)** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | 9 | 1 | 2 | | [7i92t_benezanx2d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_benezanx2d.pin) | **Benezan BOB** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | **Benezan BOB** (StepGen: 4, PWM: 4, Enkoder (QCount): 1) | 10 | 2 | 2 | | [7i92t_g540_7i76d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_g540_7i76d.pin) | **Mesa 7i76** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) | 10 | 2 | 1 | | [7i92t_g540d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_g540d.pin) | **Gecko G540** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | **Gecko G540** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | 10 | 2 | 2 | | [7i92t_mx3660d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_mx3660d.pin) | **Leadshine MX3660** (StepGen: 3, PWM: 2, Enkoder (QCount): 1) | **Leadshine MX3660** (StepGen: 3, PWM: 2, Enkoder (QCount): 1) | 8 | 2 | 2 | | [7i92t_mx4660d](file:///home/cnc/Documents/7i92t/configs/hostmot2/7i92t_mx4660d.pin) | **Leadshine MX4660** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | **Leadshine MX4660** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) | 10 | 2 | 2 | --- ## Szczegółowy Opis Konfiguracji ### 7i92t_5abob_encd * **Port P2 (DB25):** **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2, Enkoder (QCount): 1) * **Port P1 (IDC26):** **5-axis BOB (5ABOB)** (Enkoder (QCount): 5) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 5 * Sprzętowe Enkodery (QCount): 6 * Generatory PWM: 1 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort PWM 0 PWM (Out) 14 1 IOPort None 2 2 IOPort StepGen 0 Step/Table1 (Out) 15 3 IOPort None 3 4 IOPort StepGen 0 Dir/Table2 (Out) 16 5 IOPort StepGen 4 Step/Table1 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort StepGen 4 Dir/Table2 (Out) 5 8 IOPort StepGen 1 Dir/Table2 (Out) 6 9 IOPort StepGen 2 Step/Table1 (Out) 7 10 IOPort StepGen 2 Dir/Table2 (Out) 8 11 IOPort StepGen 3 Step/Table1 (Out) 9 12 IOPort StepGen 3 Dir/Table2 (Out) 10 13 IOPort None 11 14 IOPort QCount 0 Quad-A (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text -> HDR26 1 17 IOPort QCount 1 Quad-A (In) 2 18 IOPort QCount 1 Quad-B (In) 3 19 IOPort QCount 1 Quad-IDX (In) 4 20 IOPort QCount 2 Quad-A (In) 5 21 IOPort QCount 2 Quad-B (In) 6 22 IOPort QCount 2 Quad-IDX (In) 7 23 IOPort QCount 3 Quad-A (In) 8 24 IOPort QCount 3 Quad-B (In) 9 25 IOPort QCount 3 Quad-IDX (In) 11 26 IOPort QCount 4 Quad-A (In) 13 27 IOPort QCount 4 Quad-B (In) 15 28 IOPort QCount 4 Quad-IDX (In) 17 29 IOPort QCount 5 Quad-A (In) 19 30 IOPort QCount 5 Quad-B (In) 21 31 IOPort QCount 5 Quad-IDX (In) 23 32 IOPort None 25 33 IOPort None ``` --- ### 7i92t_5abobx2d * **Port P2 (DB25):** **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2, Enkoder (QCount): 1) * **Port P1 (IDC26):** **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2, Enkoder (QCount): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 10 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 2 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort PWM 0 PWM (Out) 14 1 IOPort None 2 2 IOPort StepGen 0 Step/Table1 (Out) 15 3 IOPort None 3 4 IOPort StepGen 0 Dir/Table2 (Out) 16 5 IOPort StepGen 8 Step/Table1 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort StepGen 8 Dir/Table2 (Out) 5 8 IOPort StepGen 1 Dir/Table2 (Out) 6 9 IOPort StepGen 2 Step/Table1 (Out) 7 10 IOPort StepGen 2 Dir/Table2 (Out) 8 11 IOPort StepGen 3 Step/Table1 (Out) 9 12 IOPort StepGen 3 Dir/Table2 (Out) 10 13 IOPort None 11 14 IOPort QCount 0 Quad-A (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort PWM 1 PWM (Out) 14 18 IOPort None 2 19 IOPort StepGen 4 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 4 Dir/Table2 (Out) 16 22 IOPort StepGen 9 Step/Table1 (Out) 4 23 IOPort StepGen 5 Step/Table1 (Out) 17 24 IOPort StepGen 9 Dir/Table2 (Out) 5 25 IOPort StepGen 5 Dir/Table2 (Out) 6 26 IOPort StepGen 6 Step/Table1 (Out) 7 27 IOPort StepGen 6 Dir/Table2 (Out) 8 28 IOPort StepGen 7 Step/Table1 (Out) 9 29 IOPort StepGen 7 Dir/Table2 (Out) 10 30 IOPort None 11 31 IOPort QCount 1 Quad-A (In) 12 32 IOPort QCount 1 Quad-B (In) 13 33 IOPort QCount 1 Quad-IDX (In) ``` --- ### 7i92t_7i76_7i74d * **Port P2 (DB25):** **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Port P1 (IDC26):** **Mesa 7i76** (Smart Serial (SSerial): 8) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 5 * Sprzętowe Enkodery (QCount): 1 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort StepGen 0 Dir/Table2 (Out) 14 1 IOPort StepGen 0 Step/Table1 (Out) 2 2 IOPort StepGen 1 Dir/Table2 (Out) 15 3 IOPort StepGen 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 Dir/Table2 (Out) 16 5 IOPort StepGen 2 Step/Table1 (Out) 4 6 IOPort StepGen 3 Dir/Table2 (Out) 17 7 IOPort StepGen 3 Step/Table1 (Out) 5 8 IOPort StepGen 4 Dir/Table2 (Out) 6 9 IOPort StepGen 4 Step/Table1 (Out) 7 10 IOPort SSerial 0 TXData0 (Out) 8 11 IOPort SSerial 0 RXData0 (In) 9 12 IOPort SSerial 0 TXData1 (Out) 10 13 IOPort SSerial 0 RXData1 (In) 11 14 IOPort QCount 0 Quad-IDX (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-A (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort SSerial 1 RXData0 (In) 14 18 IOPort SSerial 1 RXData1 (In) 2 19 IOPort SSerial 1 RXData2 (In) 15 20 IOPort SSerial 1 RXData3 (In) 3 21 IOPort SSerial 1 TXData0 (Out) 16 22 IOPort SSerial 1 TXData1 (Out) 4 23 IOPort SSerial 1 TXData2 (Out) 17 24 IOPort SSerial 1 TXData3 (Out) 5 25 IOPort SSerial 1 RXData4 (In) 6 26 IOPort SSerial 1 RXData5 (In) 7 27 IOPort SSerial 1 RXData6 (In) 8 28 IOPort SSerial 1 RXData7 (In) 9 29 IOPort SSerial 1 TXData4 (Out) 10 30 IOPort SSerial 1 TXData5 (Out) 11 31 IOPort SSerial 1 TXData6 (Out) 12 32 IOPort SSerial 1 TXData7 (Out) 13 33 IOPort SSerial 1 TXEn7 (Out) ``` --- ### 7i92t_7i76_7i85d * **Port P2 (DB25):** **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Port P1 (IDC26):** **Mesa 7i76** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 5 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text -> 7I76 Pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir TB2-4,5 0 IOPort StepGen 0 Dir/Table2 (Out) TB2-2,3 1 IOPort StepGen 0 Step/Table1 (Out) TB2-10,11 2 IOPort StepGen 1 Dir/Table2 (Out) TB2-8,9 3 IOPort StepGen 1 Step/Table1 (Out) TB2-16,17 4 IOPort StepGen 2 Dir/Table2 (Out) TB2-14,15 5 IOPort StepGen 2 Step/Table1 (Out) TB2-22,23 6 IOPort StepGen 3 Dir/Table2 (Out) TB2-20,21 7 IOPort StepGen 3 Step/Table1 (Out) TB3-4,5 8 IOPort StepGen 4 Dir/Table2 (Out) TB3-2,3 9 IOPort StepGen 4 Step/Table1 (Out) Internal-Field-IO 10 IOPort SSerial 0 TXData0 (Out) Internal-Field-IO 11 IOPort SSerial 0 RXData0 (In) TB3-18,19 12 IOPort SSerial 0 TXData1 (Out) TB3-16,17 13 IOPort SSerial 0 RXData1 (In) TB3-13,14 14 IOPort MuxedQCount 2 MuxQ-IDX (In) TB3-10,11 15 IOPort MuxedQCount 2 MuxQ-B (In) TB3-7,8 16 IOPort MuxedQCount 2 MuxQ-A (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text -> 7I85 TB1-19,20 17 IOPort SSerial 0 RXData6 (In) TB1-21,22 18 IOPort SSerial 0 TXData6 (Out) TB1-11,12 19 IOPort SSerial 0 RXData5 (In) TB1-13,14 20 IOPort SSerial 0 TXData5 (Out) TB1-3,4 21 IOPort SSerial 0 RXData4 (In) TB1-5,6 22 IOPort SSerial 0 TXData4 (Out) TB2-19,20 23 IOPort SSerial 0 RXData3 (In) TB2-21,22 24 IOPort SSerial 0 TXData3 (Out) TB2-11,12 25 IOPort SSerial 0 RXData2 (In) TB2-13,14 26 IOPort SSerial 0 TXData2 (Out) Internal-EncMux 27 IOPort MuxedQCountSel 0 MuxSel0 (Out) TB3-1,2,9,10 28 IOPort MuxedQCount 0 MuxQ-A (In) TB3-4,5,12,13 29 IOPort MuxedQCount 0 MuxQ-B (In) TB3-7,8,12,13 30 IOPort MuxedQCount 0 MuxQ-IDX (In) TB3-17,18,TB2-1,2 31 IOPort MuxedQCount 1 MuxQ-A (In) TB3-20,21,TB2-4,5 32 IOPort MuxedQCount 1 MuxQ-B (In) TB3-23,24,TB2-7,8 33 IOPort MuxedQCount 1 MuxQ-IDX (In) ``` --- ### 7i92t_7i76_7i85sd * **Port P2 (DB25):** **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Port P1 (IDC26):** **Mesa 7i76** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 9 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort StepGen 0 Dir/Table2 (Out) 14 1 IOPort StepGen 0 Step/Table1 (Out) 2 2 IOPort StepGen 1 Dir/Table2 (Out) 15 3 IOPort StepGen 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 Dir/Table2 (Out) 16 5 IOPort StepGen 2 Step/Table1 (Out) 4 6 IOPort StepGen 3 Dir/Table2 (Out) 17 7 IOPort StepGen 3 Step/Table1 (Out) 5 8 IOPort StepGen 4 Dir/Table2 (Out) 6 9 IOPort StepGen 4 Step/Table1 (Out) 7 10 IOPort SSerial 0 TXData0 (Out) 8 11 IOPort SSerial 0 RXData0 (In) 9 12 IOPort SSerial 0 TXData1 (Out) 10 13 IOPort SSerial 0 RXData1 (In) 11 14 IOPort MuxedQCount 2 MuxQ-IDX (In) 12 15 IOPort MuxedQCount 2 MuxQ-B (In) 13 16 IOPort MuxedQCount 2 MuxQ-A (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort SSerial 0 RXData2 (In) 14 18 IOPort SSerial 0 TXData2 (Out) 2 19 IOPort StepGen 8 Step/Table1 (Out) 15 20 IOPort StepGen 8 Dir/Table2 (Out) 3 21 IOPort StepGen 7 Step/Table1 (Out) 16 22 IOPort StepGen 7 Dir/Table2 (Out) 4 23 IOPort StepGen 6 Step/Table1 (Out) 17 24 IOPort StepGen 6 Dir/Table2 (Out) 5 25 IOPort StepGen 5 Step/Table1 (Out) 6 26 IOPort StepGen 5 Dir/Table2 (Out) 7 27 IOPort MuxedQCountSel 0 MuxSel0 (Out) 8 28 IOPort MuxedQCount 0 MuxQ-A (In) 9 29 IOPort MuxedQCount 0 MuxQ-B (In) 10 30 IOPort MuxedQCount 0 MuxQ-IDX (In) 11 31 IOPort MuxedQCount 1 MuxQ-A (In) 12 32 IOPort MuxedQCount 1 MuxQ-B (In) 13 33 IOPort MuxedQCount 1 MuxQ-IDX (In) ``` --- ### 7i92t_7i76_g540d * **Port P2 (DB25):** **Gecko G540** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Port P1 (IDC26):** **Gecko G540** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 10 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 1 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort StepGen 0 Dir/Table2 (Out) 14 1 IOPort StepGen 0 Step/Table1 (Out) 2 2 IOPort StepGen 1 Dir/Table2 (Out) 15 3 IOPort StepGen 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 Dir/Table2 (Out) 16 5 IOPort StepGen 2 Step/Table1 (Out) 4 6 IOPort StepGen 3 Dir/Table2 (Out) 17 7 IOPort StepGen 3 Step/Table1 (Out) 5 8 IOPort StepGen 4 Dir/Table2 (Out) 6 9 IOPort StepGen 4 Step/Table1 (Out) 7 10 IOPort SSerial 0 TXData0 (Out) 8 11 IOPort SSerial 0 RXData0 (In) 9 12 IOPort SSerial 0 TXData1 (Out) 10 13 IOPort SSerial 0 RXData1 (In) 11 14 IOPort QCount 0 Quad-IDX (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-A (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort None 14 18 IOPort PWM 0 PWM (Out) 2 19 IOPort StepGen 5 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 5 Dir/Table2 (Out) 16 22 IOPort StepGen 9 Step/Table1 (Out) 4 23 IOPort StepGen 6 Step/Table1 (Out) 17 24 IOPort None 5 25 IOPort StepGen 6 Dir/Table2 (Out) 6 26 IOPort StepGen 7 Step/Table1 (Out) 7 27 IOPort StepGen 7 Dir/Table2 (Out) 8 28 IOPort StepGen 8 Step/Table1 (Out) 9 29 IOPort StepGen 8 Dir/Table2 (Out) 10 30 IOPort QCount 1 Quad-A (In) 11 31 IOPort QCount 1 Quad-B (In) 12 32 IOPort QCount 1 Quad-IDX (In) 13 33 IOPort None ``` --- ### 7i92t_7i76x1pd * **Port P2 (DB25):** **Mesa 7i76** (StepGen: 4, PWM: 2, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Port P1 (IDC26):** **Mesa 7i76** * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 4 * Sprzętowe Enkodery (QCount): 1 * Generatory PWM: 1 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort StepGen 0 Dir/Table2 (Out) 14 1 IOPort StepGen 0 Step/Table1 (Out) 2 2 IOPort StepGen 1 Dir/Table2 (Out) 15 3 IOPort StepGen 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 Dir/Table2 (Out) 16 5 IOPort StepGen 2 Step/Table1 (Out) 4 6 IOPort StepGen 3 Dir/Table2 (Out) 17 7 IOPort StepGen 3 Step/Table1 (Out) 5 8 IOPort None 6 9 IOPort PWM 0 PWM (Out) 7 10 IOPort SSerial 0 TXData0 (Out) 8 11 IOPort SSerial 0 RXData0 (In) 9 12 IOPort SSerial 0 TXData1 (Out) 10 13 IOPort SSerial 0 RXData1 (In) 11 14 IOPort QCount 0 Quad-IDX (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-A (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort None 14 18 IOPort None 2 19 IOPort None 15 20 IOPort None 3 21 IOPort None 16 22 IOPort None 4 23 IOPort None 17 24 IOPort None 5 25 IOPort None 6 26 IOPort None 7 27 IOPort None 8 28 IOPort None 9 29 IOPort None 10 30 IOPort None 11 31 IOPort None 12 32 IOPort None 13 33 IOPort None ``` --- ### 7i92t_7i76x2d * **Port P2 (DB25):** **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Port P1 (IDC26):** **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 10 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort StepGen 0 Dir/Table2 (Out) 14 1 IOPort StepGen 0 Step/Table1 (Out) 2 2 IOPort StepGen 1 Dir/Table2 (Out) 15 3 IOPort StepGen 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 Dir/Table2 (Out) 16 5 IOPort StepGen 2 Step/Table1 (Out) 4 6 IOPort StepGen 3 Dir/Table2 (Out) 17 7 IOPort StepGen 3 Step/Table1 (Out) 5 8 IOPort StepGen 4 Dir/Table2 (Out) 6 9 IOPort StepGen 4 Step/Table1 (Out) 7 10 IOPort SSerial 0 TXData0 (Out) 8 11 IOPort SSerial 0 RXData0 (In) 9 12 IOPort SSerial 0 TXData1 (Out) 10 13 IOPort SSerial 0 RXData1 (In) 11 14 IOPort QCount 0 Quad-IDX (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-A (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort StepGen 5 Dir/Table2 (Out) 14 18 IOPort StepGen 5 Step/Table1 (Out) 2 19 IOPort StepGen 6 Dir/Table2 (Out) 15 20 IOPort StepGen 6 Step/Table1 (Out) 3 21 IOPort StepGen 7 Dir/Table2 (Out) 16 22 IOPort StepGen 7 Step/Table1 (Out) 4 23 IOPort StepGen 8 Dir/Table2 (Out) 17 24 IOPort StepGen 8 Step/Table1 (Out) 5 25 IOPort StepGen 9 Dir/Table2 (Out) 6 26 IOPort StepGen 9 Step/Table1 (Out) 7 27 IOPort SSerial 0 TXData2 (Out) 8 28 IOPort SSerial 0 RXData2 (In) 9 29 IOPort SSerial 0 TXData3 (Out) 10 30 IOPort SSerial 0 RXData3 (In) 11 31 IOPort QCount 1 Quad-IDX (In) 12 32 IOPort QCount 1 Quad-B (In) 13 33 IOPort QCount 1 Quad-A (In) ``` --- ### 7i92t_7i77_7i74d * **Port P2 (DB25):** **Mesa 7i77 (Analog)** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) * **Port P1 (IDC26):** **Mesa 7i77 (Analog)** (Smart Serial (SSerial): 8) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 0 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 TXEn2 (Out) 14 1 IOPort SSerial 0 TXData2 (Out) 2 2 IOPort SSerial 0 RXData2 (In) 15 3 IOPort SSerial 0 TXData1 (Out) 3 4 IOPort SSerial 0 RXData1 (In) 16 5 IOPort SSerial 0 TXData0 (Out) 4 6 IOPort SSerial 0 RXData0 (In) 17 7 IOPort MuxedQCountSel 0 MuxSel0 (Out) 5 8 IOPort MuxedQCount 0 MuxQ-A (In) 6 9 IOPort MuxedQCount 0 MuxQ-B (In) 7 10 IOPort MuxedQCount 0 MuxQ-IDX (In) 8 11 IOPort MuxedQCount 1 MuxQ-A (In) 9 12 IOPort MuxedQCount 1 MuxQ-B (In) 10 13 IOPort MuxedQCount 1 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 2 MuxQ-A (In) 12 15 IOPort MuxedQCount 2 MuxQ-B (In) 13 16 IOPort MuxedQCount 2 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort SSerial 1 RXData0 (In) 14 18 IOPort SSerial 1 RXData1 (In) 2 19 IOPort SSerial 1 RXData2 (In) 15 20 IOPort SSerial 1 RXData3 (In) 3 21 IOPort SSerial 1 TXData0 (Out) 16 22 IOPort SSerial 1 TXData1 (Out) 4 23 IOPort SSerial 1 TXData2 (Out) 17 24 IOPort SSerial 1 TXData3 (Out) 5 25 IOPort SSerial 1 RXData4 (In) 6 26 IOPort SSerial 1 RXData5 (In) 7 27 IOPort SSerial 1 RXData6 (In) 8 28 IOPort SSerial 1 RXData7 (In) 9 29 IOPort SSerial 1 TXData4 (Out) 10 30 IOPort SSerial 1 TXData5 (Out) 11 31 IOPort SSerial 1 TXData6 (Out) 12 32 IOPort SSerial 1 TXData7 (Out) 13 33 IOPort SSerial 1 TXEn7 (Out) ``` --- ### 7i92t_7i77_7i761pd * **Port P2 (DB25):** **Mesa 7i76** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) * **Port P1 (IDC26):** **Mesa 7i76** (StepGen: 4, PWM: 2, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 4 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 1 **Rozkład pinów złącza P2 (DB25):** ```text -> 7I77 Pin# I/O Pri. func Sec. func Chan Sec. Pin func Sec. Pin Dir Internal-TXEn 0 IOPort SSerial 0 TXEn2 (Out) TB6-5,6 1 IOPort SSerial 0 TXData2 (Out) TB6-3,4 2 IOPort SSerial 0 RXData2 (In) Internal-Analog-IO 3 IOPort SSerial 0 TXData1 (Out) Internal-Analog-IO 4 IOPort SSerial 0 RXData1 (In) Internal-Field-IO 5 IOPort SSerial 0 TXData0 (Out) Internal-Field-IO 6 IOPort SSerial 0 RXData0 (In) Internal-EncMux 7 IOPort MuxedQCountSel 0 MuxSel0 (Out) TB3-1,2,9,10 8 IOPort MuxedQCount 0 MuxQ-A (In) TB3-4,5,12,13 9 IOPort MuxedQCount 0 MuxQ-B (In) TB3-7,8,15,16 10 IOPort MuxedQCount 0 MuxQ-IDX (In) TB3-17,18,TB4-1,2 11 IOPort MuxedQCount 1 MuxQ-A (In) TB3-20,21,TB4-4,5 12 IOPort MuxedQCount 1 MuxQ-B (In) TB3-23,24,TB4-7,8 13 IOPort MuxedQCount 1 MuxQ-IDX (In) TB4-9,10,17,18 14 IOPort MuxedQCount 2 MuxQ-A (In) TB4-12,13,20,21 15 IOPort MuxedQCount 2 MuxQ-B (In) TB4-15,16,23,24 16 IOPort MuxedQCount 2 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text -> 7I76 TB2-4,5 17 IOPort StepGen 0 Dir/Table2 (Out) TB2-2,3 18 IOPort StepGen 0 Step/Table1 (Out) TB2-10,11 19 IOPort StepGen 1 Dir/Table2 (Out) TB2-8,9 20 IOPort StepGen 1 Step/Table1 (Out) TB2-16,17 21 IOPort StepGen 2 Dir/Table2 (Out) TB2-14,15 22 IOPort StepGen 2 Step/Table1 (Out) TB2-22,23 23 IOPort StepGen 3 Dir/Table2 (Out) TB2-20,21 24 IOPort StepGen 3 Step/Table1 (Out) TB3-4,5 25 IOPort PWM 0 PWM (Out) TB3-2,3 26 IOPort None Internal-Field-IO 27 IOPort SSerial 0 TXData3 (Out) Internal-Field-IO 28 IOPort SSerial 0 RXData3 (In) TB3-18,19 29 IOPort SSerial 0 TXData4 (Out) TB3-16,17 30 IOPort SSerial 0 RXData4 (In) TB3-13,14 31 IOPort MuxedQCount 3 MuxQ-IDX (In) TB3-10,11 32 IOPort MuxedQCount 3 MuxQ-B (In) TB3-7,8 33 IOPort MuxedQCount 3 MuxQ-A (In) ``` --- ### 7i92t_7i77_7i76d * **Port P2 (DB25):** **Mesa 7i76** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) * **Port P1 (IDC26):** **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 5 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 TXEn2 (Out) 14 1 IOPort SSerial 0 TXData2 (Out) 2 2 IOPort SSerial 0 RXData2 (In) 15 3 IOPort SSerial 0 TXData1 (Out) 3 4 IOPort SSerial 0 RXData1 (In) 16 5 IOPort SSerial 0 TXData0 (Out) 4 6 IOPort SSerial 0 RXData0 (In) 17 7 IOPort MuxedQCountSel 0 MuxSel0 (Out) 5 8 IOPort MuxedQCount 0 MuxQ-A (In) 6 9 IOPort MuxedQCount 0 MuxQ-B (In) 7 10 IOPort MuxedQCount 0 MuxQ-IDX (In) 8 11 IOPort MuxedQCount 1 MuxQ-A (In) 9 12 IOPort MuxedQCount 1 MuxQ-B (In) 10 13 IOPort MuxedQCount 1 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 2 MuxQ-A (In) 12 15 IOPort MuxedQCount 2 MuxQ-B (In) 13 16 IOPort MuxedQCount 2 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort StepGen 0 Dir/Table2 (Out) 14 18 IOPort StepGen 0 Step/Table1 (Out) 2 19 IOPort StepGen 1 Dir/Table2 (Out) 15 20 IOPort StepGen 1 Step/Table1 (Out) 3 21 IOPort StepGen 2 Dir/Table2 (Out) 16 22 IOPort StepGen 2 Step/Table1 (Out) 4 23 IOPort StepGen 3 Dir/Table2 (Out) 17 24 IOPort StepGen 3 Step/Table1 (Out) 5 25 IOPort StepGen 4 Dir/Table2 (Out) 6 26 IOPort StepGen 4 Step/Table1 (Out) 7 27 IOPort SSerial 0 TXData3 (Out) 8 28 IOPort SSerial 0 RXData3 (In) 9 29 IOPort SSerial 0 TXData4 (Out) 10 30 IOPort SSerial 0 RXData4 (In) 11 31 IOPort MuxedQCount 3 MuxQ-IDX (In) 12 32 IOPort MuxedQCount 3 MuxQ-B (In) 13 33 IOPort MuxedQCount 3 MuxQ-A (In) ``` --- ### 7i92t_7i77x2d * **Port P2 (DB25):** **Mesa 7i77 (Analog)** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) * **Port P1 (IDC26):** **Mesa 7i77 (Analog)** (Enkoder (QCount): 3, Smart Serial (SSerial): 3) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 0 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 TXEn2 (Out) 14 1 IOPort SSerial 0 TXData2 (Out) 2 2 IOPort SSerial 0 RXData2 (In) 15 3 IOPort SSerial 0 TXData1 (Out) 3 4 IOPort SSerial 0 RXData1 (In) 16 5 IOPort SSerial 0 TXData0 (Out) 4 6 IOPort SSerial 0 RXData0 (In) 17 7 IOPort MuxedQCountSel 0 MuxSel0 (Out) 5 8 IOPort MuxedQCount 0 MuxQ-A (In) 6 9 IOPort MuxedQCount 0 MuxQ-B (In) 7 10 IOPort MuxedQCount 0 MuxQ-IDX (In) 8 11 IOPort MuxedQCount 1 MuxQ-A (In) 9 12 IOPort MuxedQCount 1 MuxQ-B (In) 10 13 IOPort MuxedQCount 1 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 2 MuxQ-A (In) 12 15 IOPort MuxedQCount 2 MuxQ-B (In) 13 16 IOPort MuxedQCount 2 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort SSerial 0 TXEn5 (Out) 14 18 IOPort SSerial 0 TXData5 (Out) 2 19 IOPort SSerial 0 RXData5 (In) 15 20 IOPort SSerial 0 TXData4 (Out) 3 21 IOPort SSerial 0 RXData4 (In) 16 22 IOPort SSerial 0 TXData3 (Out) 4 23 IOPort SSerial 0 RXData3 (In) 17 24 IOPort MuxedQCountSel 6 MuxSel0 (Out) 5 25 IOPort MuxedQCount 3 MuxQ-A (In) 6 26 IOPort MuxedQCount 3 MuxQ-B (In) 7 27 IOPort MuxedQCount 3 MuxQ-IDX (In) 8 28 IOPort MuxedQCount 4 MuxQ-A (In) 9 29 IOPort MuxedQCount 4 MuxQ-B (In) 10 30 IOPort MuxedQCount 4 MuxQ-IDX (In) 11 31 IOPort MuxedQCount 5 MuxQ-A (In) 12 32 IOPort MuxedQCount 5 MuxQ-B (In) 13 33 IOPort MuxedQCount 5 MuxQ-IDX (In) ``` --- ### 7i92t_7i78x2d * **Port P2 (DB25):** **Mesa 7i78** (StepGen: 4, PWM: 4, Enkoder (QCount): 1, Smart Serial (SSerial): 1) * **Port P1 (IDC26):** **Mesa 7i78** (StepGen: 4, PWM: 4, Enkoder (QCount): 1, Smart Serial (SSerial): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 8 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 2 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort StepGen 0 Dir/Table2 (Out) 14 1 IOPort StepGen 0 Step/Table1 (Out) 2 2 IOPort StepGen 1 Dir/Table2 (Out) 15 3 IOPort StepGen 1 Step/Table1 (Out) 3 4 IOPort StepGen 2 Dir/Table2 (Out) 16 5 IOPort StepGen 2 Step/Table1 (Out) 4 6 IOPort StepGen 3 Dir/Table2 (Out) 17 7 IOPort StepGen 3 Step/Table1 (Out) 5 8 IOPort PWM 0 PWM (Out) 6 9 IOPort PWM 0 /Enable (Out) 7 10 IOPort PWM 0 Dir (Out) 8 11 IOPort SSerial 0 TXData0 (Out) 9 12 IOPort SSerial 0 TXEn0 (Out) 10 13 IOPort SSerial 0 RXData0 (In) 11 14 IOPort QCount 0 Quad-IDX (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-A (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort StepGen 4 Dir/Table2 (Out) 14 18 IOPort StepGen 4 Step/Table1 (Out) 2 19 IOPort StepGen 5 Dir/Table2 (Out) 15 20 IOPort StepGen 5 Step/Table1 (Out) 3 21 IOPort StepGen 6 Dir/Table2 (Out) 16 22 IOPort StepGen 6 Step/Table1 (Out) 4 23 IOPort StepGen 7 Dir/Table2 (Out) 17 24 IOPort StepGen 7 Step/Table1 (Out) 5 25 IOPort PWM 1 PWM (Out) 6 26 IOPort PWM 1 /Enable (Out) 7 27 IOPort PWM 1 Dir (Out) 8 28 IOPort SSerial 0 TXData1 (Out) 9 29 IOPort SSerial 0 TXEn1 (Out) 10 30 IOPort SSerial 0 RXData1 (In) 11 31 IOPort QCount 1 Quad-IDX (In) 12 32 IOPort QCount 1 Quad-B (In) 13 33 IOPort QCount 1 Quad-A (In) ``` --- ### 7i92t_7i85_g540d * **Port P2 (DB25):** **Gecko G540** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) * **Port P1 (IDC26):** **Gecko G540** (StepGen: 4, PWM: 2) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 5 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 1 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 RXData4 (In) 14 1 IOPort SSerial 0 TXData4 (Out) 2 2 IOPort SSerial 0 RXData3 (In) 15 3 IOPort SSerial 0 TXData3 (Out) 3 4 IOPort SSerial 0 RXData2 (In) 16 5 IOPort SSerial 0 TXData2 (Out) 4 6 IOPort SSerial 0 RXData1 (In) 17 7 IOPort SSerial 0 TXData1 (Out) 5 8 IOPort SSerial 0 RXData0 (In) 6 9 IOPort SSerial 0 TXData0 (Out) 7 10 IOPort MuxedQCountSel 0 MuxSel0 (Out) 8 11 IOPort MuxedQCount 0 MuxQ-A (In) 9 12 IOPort MuxedQCount 0 MuxQ-B (In) 10 13 IOPort MuxedQCount 0 Shared-IDX (In) 11 14 IOPort MuxedQCount 1 MuxQ-A (In) 12 15 IOPort MuxedQCount 1 MuxQ-B (In) 13 16 IOPort MuxedQCount 1 Shared-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort None 14 18 IOPort PWM 0 PWM (Out) 2 19 IOPort StepGen 0 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 0 Dir/Table2 (Out) 16 22 IOPort StepGen 4 Step/Table1 (Out) 4 23 IOPort StepGen 1 Step/Table1 (Out) 17 24 IOPort None 5 25 IOPort StepGen 1 Dir/Table2 (Out) 6 26 IOPort StepGen 2 Step/Table1 (Out) 7 27 IOPort StepGen 2 Dir/Table2 (Out) 8 28 IOPort StepGen 3 Step/Table1 (Out) 9 29 IOPort StepGen 3 Dir/Table2 (Out) 10 30 IOPort None 11 31 IOPort None 12 32 IOPort None 13 33 IOPort None ``` --- ### 7i92t_7i85s_4pwm * **Port P2 (DB25):** **Mesa 7i85 / 7i85S** (PWM: 12, Enkoder (QCount): 2, Smart Serial (SSerial): 1) * **Port P1 (IDC26):** **Mesa 7i85 / 7i85S** * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 0 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 4 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 RXData0 (In) 14 1 IOPort SSerial 0 TXData0 (Out) 2 2 IOPort PWM 3 PWM (Out) 15 3 IOPort PWM 3 Dir (Out) 3 4 IOPort PWM 2 PWM (Out) 16 5 IOPort PWM 2 Dir (Out) 4 6 IOPort PWM 1 PWM (Out) 17 7 IOPort PWM 1 Dir (Out) 5 8 IOPort PWM 0 PWM (Out) 6 9 IOPort PWM 0 Dir (Out) 7 10 IOPort MuxedQCountSel 0 MuxSel0 (Out) 8 11 IOPort MuxedQCount 0 MuxQ-A (In) 9 12 IOPort MuxedQCount 0 MuxQ-B (In) 10 13 IOPort MuxedQCount 0 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 1 MuxQ-A (In) 12 15 IOPort MuxedQCount 1 MuxQ-B (In) 13 16 IOPort MuxedQCount 1 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort None 14 18 IOPort None 2 19 IOPort None 15 20 IOPort None 3 21 IOPort None 16 22 IOPort None 4 23 IOPort None 17 24 IOPort None 5 25 IOPort None 6 26 IOPort None 7 27 IOPort None 8 28 IOPort None 9 29 IOPort None 10 30 IOPort None 11 31 IOPort None 12 32 IOPort None 13 33 IOPort None ``` --- ### 7i92t_7i85s_5abobd * **Port P2 (DB25):** **5-axis BOB (5ABOB)** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) * **Port P1 (IDC26):** **5-axis BOB (5ABOB)** (StepGen: 5, PWM: 2) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 9 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 1 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 RXData0 (In) 14 1 IOPort SSerial 0 TXData0 (Out) 2 2 IOPort StepGen 3 Step/Table1 (Out) 15 3 IOPort StepGen 3 Dir/Table2 (Out) 3 4 IOPort StepGen 2 Step/Table1 (Out) 16 5 IOPort StepGen 2 Dir/Table2 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort StepGen 1 Dir/Table2 (Out) 5 8 IOPort StepGen 0 Step/Table1 (Out) 6 9 IOPort StepGen 0 Dir/Table2 (Out) 7 10 IOPort MuxedQCountSel 0 MuxSel0 (Out) 8 11 IOPort MuxedQCount 0 MuxQ-A (In) 9 12 IOPort MuxedQCount 0 MuxQ-B (In) 10 13 IOPort MuxedQCount 0 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 1 MuxQ-A (In) 12 15 IOPort MuxedQCount 1 MuxQ-B (In) 13 16 IOPort MuxedQCount 1 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort PWM 0 PWM (Out) 14 18 IOPort None 2 19 IOPort StepGen 4 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 4 Dir/Table2 (Out) 16 22 IOPort StepGen 8 Step/Table1 (Out) 4 23 IOPort StepGen 5 Step/Table1 (Out) 17 24 IOPort StepGen 8 Dir/Table2 (Out) 5 25 IOPort StepGen 5 Dir/Table2 (Out) 6 26 IOPort StepGen 6 Step/Table1 (Out) 7 27 IOPort StepGen 6 Dir/Table2 (Out) 8 28 IOPort StepGen 7 Step/Table1 (Out) 9 29 IOPort StepGen 7 Dir/Table2 (Out) 10 30 IOPort None 11 31 IOPort None 12 32 IOPort None 13 33 IOPort None ``` --- ### 7i92t_7i85sx2d * **Port P2 (DB25):** **Mesa 7i85 / 7i85S** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) * **Port P1 (IDC26):** **Mesa 7i85 / 7i85S** (StepGen: 4, Enkoder (QCount): 2, Smart Serial (SSerial): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 8 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 RXData0 (In) 14 1 IOPort SSerial 0 TXData0 (Out) 2 2 IOPort StepGen 3 Step/Table1 (Out) 15 3 IOPort StepGen 3 Dir/Table2 (Out) 3 4 IOPort StepGen 2 Step/Table1 (Out) 16 5 IOPort StepGen 2 Dir/Table2 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort StepGen 1 Dir/Table2 (Out) 5 8 IOPort StepGen 0 Step/Table1 (Out) 6 9 IOPort StepGen 0 Dir/Table2 (Out) 7 10 IOPort MuxedQCountSel 0 MuxSel0 (Out) 8 11 IOPort MuxedQCount 0 MuxQ-A (In) 9 12 IOPort MuxedQCount 0 MuxQ-B (In) 10 13 IOPort MuxedQCount 0 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 1 MuxQ-A (In) 12 15 IOPort MuxedQCount 1 MuxQ-B (In) 13 16 IOPort MuxedQCount 1 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort SSerial 0 RXData1 (In) 14 18 IOPort SSerial 0 TXData1 (Out) 2 19 IOPort StepGen 7 Step/Table1 (Out) 15 20 IOPort StepGen 7 Dir/Table2 (Out) 3 21 IOPort StepGen 6 Step/Table1 (Out) 16 22 IOPort StepGen 6 Dir/Table2 (Out) 4 23 IOPort StepGen 5 Step/Table1 (Out) 17 24 IOPort StepGen 5 Dir/Table2 (Out) 5 25 IOPort StepGen 4 Step/Table1 (Out) 6 26 IOPort StepGen 4 Dir/Table2 (Out) 7 27 IOPort MuxedQCountSel 4 MuxSel0 (Out) 8 28 IOPort MuxedQCount 2 MuxQ-A (In) 9 29 IOPort MuxedQCount 2 MuxQ-B (In) 10 30 IOPort MuxedQCount 2 MuxQ-IDX (In) 11 31 IOPort MuxedQCount 3 MuxQ-A (In) 12 32 IOPort MuxedQCount 3 MuxQ-B (In) 13 33 IOPort MuxedQCount 3 MuxQ-IDX (In) ``` --- ### 7i92t_7i85x2d * **Port P2 (DB25):** **Mesa 7i85 / 7i85S** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) * **Port P1 (IDC26):** **Mesa 7i85 / 7i85S** (Enkoder (QCount): 2, Smart Serial (SSerial): 5) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 0 * Sprzętowe Enkodery (QCount): 0 * Generatory PWM: 0 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort SSerial 0 RXData4 (In) 14 1 IOPort SSerial 0 TXData4 (Out) 2 2 IOPort SSerial 0 RXData3 (In) 15 3 IOPort SSerial 0 TXData3 (Out) 3 4 IOPort SSerial 0 RXData2 (In) 16 5 IOPort SSerial 0 TXData2 (Out) 4 6 IOPort SSerial 0 RXData1 (In) 17 7 IOPort SSerial 0 TXData1 (Out) 5 8 IOPort SSerial 0 RXData0 (In) 6 9 IOPort SSerial 0 TXData0 (Out) 7 10 IOPort MuxedQCountSel 0 MuxSel0 (Out) 8 11 IOPort MuxedQCount 0 MuxQ-A (In) 9 12 IOPort MuxedQCount 0 MuxQ-B (In) 10 13 IOPort MuxedQCount 0 MuxQ-IDX (In) 11 14 IOPort MuxedQCount 1 MuxQ-A (In) 12 15 IOPort MuxedQCount 1 MuxQ-B (In) 13 16 IOPort MuxedQCount 1 MuxQ-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort SSerial 1 RXData4 (In) 14 18 IOPort SSerial 1 TXData4 (Out) 2 19 IOPort SSerial 1 RXData3 (In) 15 20 IOPort SSerial 1 TXData3 (Out) 3 21 IOPort SSerial 1 RXData2 (In) 16 22 IOPort SSerial 1 TXData2 (Out) 4 23 IOPort SSerial 1 RXData1 (In) 17 24 IOPort SSerial 1 TXData1 (Out) 5 25 IOPort SSerial 1 RXData0 (In) 6 26 IOPort SSerial 1 TXData0 (Out) 7 27 IOPort MuxedQCountSel 4 MuxSel0 (Out) 8 28 IOPort MuxedQCount 2 MuxQ-A (In) 9 29 IOPort MuxedQCount 2 MuxQ-B (In) 10 30 IOPort MuxedQCount 2 MuxQ-IDX (In) 11 31 IOPort MuxedQCount 3 MuxQ-A (In) 12 32 IOPort MuxedQCount 3 MuxQ-B (In) 13 33 IOPort MuxedQCount 3 MuxQ-IDX (In) ``` --- ### 7i92t_benezan_5abobd * **Port P2 (DB25):** **5-axis BOB (5ABOB)** (StepGen: 4, PWM: 2) * **Port P1 (IDC26):** **5-axis BOB (5ABOB)** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 9 * Sprzętowe Enkodery (QCount): 1 * Generatory PWM: 2 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort None 14 1 IOPort None 2 2 IOPort StepGen 0 Dir/Table2 (Out) 15 3 IOPort None 3 4 IOPort StepGen 0 Step/Table1 (Out) 16 5 IOPort StepGen 4 Step/Table1 (Out) 4 6 IOPort StepGen 1 Dir/Table2 (Out) 17 7 IOPort PWM 0 PWM (Out) 5 8 IOPort StepGen 1 Step/Table1 (Out) 6 9 IOPort StepGen 2 Dir/Table2 (Out) 7 10 IOPort StepGen 2 Step/Table1 (Out) 8 11 IOPort StepGen 3 Dir/Table2 (Out) 9 12 IOPort StepGen 3 Step/Table1 (Out) 10 13 IOPort None 11 14 IOPort None 12 15 IOPort None 13 16 IOPort None ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort PWM 1 PWM (Out) 14 18 IOPort None 2 19 IOPort StepGen 5 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 5 Dir/Table2 (Out) 16 22 IOPort None 4 23 IOPort StepGen 6 Step/Table1 (Out) 17 24 IOPort None 5 25 IOPort StepGen 6 Dir/Table2 (Out) 6 26 IOPort StepGen 7 Step/Table1 (Out) 7 27 IOPort StepGen 7 Dir/Table2 (Out) 8 28 IOPort StepGen 8 Step/Table1 (Out) 9 29 IOPort StepGen 8 Dir/Table2 (Out) 10 30 IOPort None 11 31 IOPort QCount 0 Quad-A (In) 12 32 IOPort QCount 0 Quad-B (In) 13 33 IOPort QCount 0 Quad-IDX (In) ``` --- ### 7i92t_benezanx2d * **Port P2 (DB25):** **Benezan BOB** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Port P1 (IDC26):** **Benezan BOB** (StepGen: 4, PWM: 4, Enkoder (QCount): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 10 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 2 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort None 14 1 IOPort None 2 2 IOPort StepGen 0 Dir/Table2 (Out) 15 3 IOPort None 3 4 IOPort StepGen 0 Step/Table1 (Out) 16 5 IOPort StepGen 4 Step/Table1 (Out) 4 6 IOPort StepGen 1 Dir/Table2 (Out) 17 7 IOPort PWM 0 PWM (Out) 5 8 IOPort StepGen 1 Step/Table1 (Out) 6 9 IOPort StepGen 2 Dir/Table2 (Out) 7 10 IOPort StepGen 2 Step/Table1 (Out) 8 11 IOPort StepGen 3 Dir/Table2 (Out) 9 12 IOPort StepGen 3 Step/Table1 (Out) 10 13 IOPort None 11 14 IOPort QCount 0 Quad-A (In) 12 15 IOPort QCount 0 Quad-B (In) 13 16 IOPort QCount 0 Quad-IDX (In) ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort PWM 1 PWM (Out) 14 18 IOPort None 2 19 IOPort StepGen 5 Dir/Table2 (Out) 15 20 IOPort None 3 21 IOPort StepGen 5 Step/Table1 (Out) 16 22 IOPort StepGen 9 Step/Table1 (Out) 4 23 IOPort StepGen 6 Dir/Table2 (Out) 17 24 IOPort PWM 1 PWM (Out) 5 25 IOPort StepGen 6 Step/Table1 (Out) 6 26 IOPort StepGen 7 Dir/Table2 (Out) 7 27 IOPort StepGen 7 Step/Table1 (Out) 8 28 IOPort StepGen 8 Dir/Table2 (Out) 9 29 IOPort StepGen 8 Step/Table1 (Out) 10 30 IOPort None 11 31 IOPort QCount 1 Quad-A (In) 12 32 IOPort QCount 1 Quad-B (In) 13 33 IOPort QCount 1 Quad-IDX (In) ``` --- ### 7i92t_g540_7i76d * **Port P2 (DB25):** **Mesa 7i76** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Port P1 (IDC26):** **Mesa 7i76** (StepGen: 5, Enkoder (QCount): 1, Smart Serial (SSerial): 2) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 10 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 1 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort None 14 1 IOPort PWM 0 PWM (Out) 2 2 IOPort StepGen 5 Step/Table1 (Out) 15 3 IOPort None 3 4 IOPort StepGen 5 Dir/Table2 (Out) 16 5 IOPort StepGen 9 Step/Table1 (Out) 4 6 IOPort StepGen 6 Step/Table1 (Out) 17 7 IOPort None 5 8 IOPort StepGen 6 Dir/Table2 (Out) 6 9 IOPort StepGen 7 Step/Table1 (Out) 7 10 IOPort StepGen 7 Dir/Table2 (Out) 8 11 IOPort StepGen 8 Step/Table1 (Out) 9 12 IOPort StepGen 8 Dir/Table2 (Out) 10 13 IOPort QCount 1 Quad-A (In) 11 14 IOPort QCount 1 Quad-B (In) 12 15 IOPort QCount 1 Quad-IDX (In) 13 16 IOPort None ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort StepGen 0 Dir/Table2 (Out) 14 18 IOPort StepGen 0 Step/Table1 (Out) 2 19 IOPort StepGen 1 Dir/Table2 (Out) 15 20 IOPort StepGen 1 Step/Table1 (Out) 3 21 IOPort StepGen 2 Dir/Table2 (Out) 16 22 IOPort StepGen 2 Step/Table1 (Out) 4 23 IOPort StepGen 3 Dir/Table2 (Out) 17 24 IOPort StepGen 3 Step/Table1 (Out) 5 25 IOPort StepGen 4 Dir/Table2 (Out) 6 26 IOPort StepGen 4 Step/Table1 (Out) 7 27 IOPort SSerial 0 TXData0 (Out) 8 28 IOPort SSerial 0 RXData0 (In) 9 29 IOPort SSerial 0 TXData1 (Out) 10 30 IOPort SSerial 0 RXData1 (In) 11 31 IOPort QCount 0 Quad-IDX (In) 12 32 IOPort QCount 0 Quad-B (In) 13 33 IOPort QCount 0 Quad-A (In) ``` --- ### 7i92t_g540d * **Port P2 (DB25):** **Gecko G540** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Port P1 (IDC26):** **Gecko G540** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 10 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 2 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort None 14 1 IOPort PWM 0 PWM (Out) 2 2 IOPort StepGen 0 Step/Table1 (Out) 15 3 IOPort None 3 4 IOPort StepGen 0 Dir/Table2 (Out) 16 5 IOPort StepGen 4 Step/Table1 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort None 5 8 IOPort StepGen 1 Dir/Table2 (Out) 6 9 IOPort StepGen 2 Step/Table1 (Out) 7 10 IOPort StepGen 2 Dir/Table2 (Out) 8 11 IOPort StepGen 3 Step/Table1 (Out) 9 12 IOPort StepGen 3 Dir/Table2 (Out) 10 13 IOPort QCount 0 Quad-A (In) 11 14 IOPort QCount 0 Quad-B (In) 12 15 IOPort QCount 0 Quad-IDX (In) 13 16 IOPort None ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort None 14 18 IOPort PWM 1 PWM (Out) 2 19 IOPort StepGen 5 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 5 Dir/Table2 (Out) 16 22 IOPort StepGen 9 Step/Table1 (Out) 4 23 IOPort StepGen 6 Step/Table1 (Out) 17 24 IOPort None 5 25 IOPort StepGen 6 Dir/Table2 (Out) 6 26 IOPort StepGen 7 Step/Table1 (Out) 7 27 IOPort StepGen 7 Dir/Table2 (Out) 8 28 IOPort StepGen 8 Step/Table1 (Out) 9 29 IOPort StepGen 8 Dir/Table2 (Out) 10 30 IOPort QCount 1 Quad-A (In) 11 31 IOPort QCount 1 Quad-B (In) 12 32 IOPort QCount 1 Quad-IDX (In) 13 33 IOPort None ``` --- ### 7i92t_mx3660d * **Port P2 (DB25):** **Leadshine MX3660** (StepGen: 3, PWM: 2, Enkoder (QCount): 1) * **Port P1 (IDC26):** **Leadshine MX3660** (StepGen: 3, PWM: 2, Enkoder (QCount): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 8 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 2 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort None 14 1 IOPort PWM 0 PWM (Out) 2 2 IOPort StepGen 0 Step/Table1 (Out) 15 3 IOPort None 3 4 IOPort StepGen 0 Dir/Table2 (Out) 16 5 IOPort StepGen 3 Step/Table1 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort None 5 8 IOPort StepGen 1 Dir/Table2 (Out) 6 9 IOPort StepGen 2 Step/Table1 (Out) 7 10 IOPort StepGen 2 Dir/Table2 (Out) 8 11 IOPort None 9 12 IOPort None 10 13 IOPort QCount 0 Quad-A (In) 11 14 IOPort QCount 0 Quad-B (In) 12 15 IOPort QCount 0 Quad-IDX (In) 13 16 IOPort None ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort None 14 18 IOPort PWM 1 PWM (Out) 2 19 IOPort StepGen 4 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 4 Dir/Table2 (Out) 16 22 IOPort StepGen 7 Step/Table1 (Out) 4 23 IOPort StepGen 5 Step/Table1 (Out) 17 24 IOPort None 5 25 IOPort StepGen 5 Dir/Table2 (Out) 6 26 IOPort StepGen 6 Step/Table1 (Out) 7 27 IOPort StepGen 6 Dir/Table2 (Out) 8 28 IOPort None 9 29 IOPort None 10 30 IOPort QCount 1 Quad-A (In) 11 31 IOPort QCount 1 Quad-B (In) 12 32 IOPort QCount 1 Quad-IDX (In) 13 33 IOPort None ``` --- ### 7i92t_mx4660d * **Port P2 (DB25):** **Leadshine MX4660** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Port P1 (IDC26):** **Leadshine MX4660** (StepGen: 4, PWM: 2, Enkoder (QCount): 1) * **Zasoby sprzętowe FPGA:** * Sprzętowe Generatory Kroków (StepGen): 10 * Sprzętowe Enkodery (QCount): 2 * Generatory PWM: 2 **Rozkład pinów złącza P2 (DB25):** ```text 1 0 IOPort None 14 1 IOPort PWM 0 PWM (Out) 2 2 IOPort StepGen 0 Step/Table1 (Out) 15 3 IOPort None 3 4 IOPort StepGen 0 Dir/Table2 (Out) 16 5 IOPort StepGen 4 Step/Table1 (Out) 4 6 IOPort StepGen 1 Step/Table1 (Out) 17 7 IOPort None 5 8 IOPort StepGen 1 Dir/Table2 (Out) 6 9 IOPort StepGen 2 Step/Table1 (Out) 7 10 IOPort StepGen 2 Dir/Table2 (Out) 8 11 IOPort StepGen 3 Step/Table1 (Out) 9 12 IOPort StepGen 3 Dir/Table2 (Out) 10 13 IOPort QCount 0 Quad-A (In) 11 14 IOPort QCount 0 Quad-B (In) 12 15 IOPort QCount 0 Quad-IDX (In) 13 16 IOPort None ``` **Rozkład pinów złącza P1 (IDC26):** ```text 1 17 IOPort None 14 18 IOPort PWM 1 PWM (Out) 2 19 IOPort StepGen 5 Step/Table1 (Out) 15 20 IOPort None 3 21 IOPort StepGen 5 Dir/Table2 (Out) 16 22 IOPort StepGen 9 Step/Table1 (Out) 4 23 IOPort StepGen 6 Step/Table1 (Out) 17 24 IOPort None 5 25 IOPort StepGen 6 Dir/Table2 (Out) 6 26 IOPort StepGen 7 Step/Table1 (Out) 7 27 IOPort StepGen 7 Dir/Table2 (Out) 8 28 IOPort StepGen 8 Step/Table1 (Out) 9 29 IOPort StepGen 8 Dir/Table2 (Out) 10 30 IOPort QCount 1 Quad-A (In) 11 31 IOPort QCount 1 Quad-B (In) 12 32 IOPort QCount 1 Quad-IDX (In) 13 33 IOPort None ``` ---