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Drivers/STM32F3xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_can_legacy.h
* @author MCD Application Team
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CAN_LEGACY_H
#define __STM32F3xx_HAL_CAN_LEGACY_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F302x8) || \
defined(STM32F373xC) || defined(STM32F378xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CAN
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint32_t SJW; /*!< Specifies the maximum number of time quanta
the CAN hardware is allowed to lengthen or
shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE. */
uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
This parameter can be set to ENABLE or DISABLE. */
}CAN_InitTypeDef;
/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint32_t FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
uint32_t BankNumber; /*!< Select the start slave bank filter
F3 devices don't support CAN2 interface (Slave). Therefore this parameter
is meaningless but it has been kept for compatibility accross STM32 families */
}CAN_FilterConfTypeDef;
/**
* @brief CAN Tx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
uint8_t Data[8]; /*!< Contains the data to be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
}CanTxMsgTypeDef;
/**
* @brief CAN Rx message structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the received message.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
uint8_t Data[8]; /*!< Contains the data to be received.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
This parameter can be CAN_FIFO0 or CAN_FIFO1 */
}CanRxMsgTypeDef;
/**
* @brief CAN handle Structure definition
*/
typedef struct
{
CAN_TypeDef *Instance; /*!< Register base address */
CAN_InitTypeDef Init; /*!< CAN required parameters */
CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
HAL_LockTypeDef Lock; /*!< CAN locking object */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
__IO uint32_t ErrorCode; /*!< CAN Error code
This parameter can be a value of @ref CAN_Error_Code */
}CAN_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
#define HAL_CAN_ERROR_FOV0 (0x00000200U) /*!< FIFO0 overrun error */
#define HAL_CAN_ERROR_FOV1 (0x00000400U) /*!< FIFO1 overrun error */
#define HAL_CAN_ERROR_TXFAIL (0x00000800U) /*!< Transmit failure */
/**
* @}
*/
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
/**
* @}
*/
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
/**
* @}
*/
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
/**
* @}
*/
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
/** @defgroup CAN_flags CAN Flags
* @{
*/
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
and CAN_ClearFlag() functions. */
/* If the flag is 0x1XXXXXXX, it means that it can only be used with
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
/** @defgroup CAN_interrupts CAN Interrupts
* @{
*/
#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
/** @defgroup CAN_Mailboxes CAN Mailboxes
* @{
*/
/* Mailboxes definition */
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
/** @brief Reset CAN handle state
* @param __HANDLE__ CAN handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt
* @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt
* @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/**
* @brief Return the number of pending received messages.
* @param __HANDLE__ CAN handle.
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval The number of pending message.
*/
#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
/** @brief Clear the specified CAN pending flag.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_TSR_RQCP0: Request MailBox0 Flag
* @arg CAN_TSR_RQCP1: Request MailBox1 Flag
* @arg CAN_TSR_RQCP2: Request MailBox2 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
* @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
* @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
* @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
* @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
* @arg CAN_FLAG_FF0: FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
* @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
* @arg CAN_FLAG_FF1: FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the CAN Handle.
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
* @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
* @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Check the transmission status of a CAN Frame.
* @param __HANDLE__ CAN handle.
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
* @retval The new status of transmission (TRUE or FALSE).
*/
#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
/**
* @brief Release the specified receive FIFO.
* @param __HANDLE__ CAN handle.
* @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @retval None
*/
#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
/**
* @brief Cancel a transmit request.
* @param __HANDLE__ specifies the CAN Handle.
* @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
* @retval None
*/
#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
/**
* @brief Enable or disables the DBG Freeze for CAN.
* @param __HANDLE__ specifies the CAN Handle.
* @param __NEWSTATE__ new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
* during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
* @retval None
*/
#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
* @brief I/O operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
* @brief CAN Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CAN_Private_Types CAN Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CAN_Private_Variables CAN Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
/* Private Macros -----------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
#define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
#define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F302x8 || */
/* STM32F373xC || STM32F378xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CAN_LEGACY_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_ASSERT_H
#define __STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32_ASSERT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_H
#define __STM32F3xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_conf.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup HAL_Private_Macros
* @{
*/
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/**
* @}
*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup SYSCFG_BitAddress_AliasRegion SYSCFG registers bit address in the alias region
* @brief SYSCFG registers bit address in the alias region
* @{
*/
/* ------------ SYSCFG registers bit address in the alias region -------------*/
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE)
/* --- CFGR2 Register ---*/
/* Alias word address of BYP_ADDR_PAR bit */
#define CFGR2_OFFSET (SYSCFG_OFFSET + 0x18U)
#define BYPADDRPAR_BitNumber 0x04U
#define CFGR2_BYPADDRPAR_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
/**
* @}
*/
#if defined(SYSCFG_CFGR1_DMA_RMP)
/** @defgroup HAL_DMA_Remapping HAL DMA Remapping
* Elements values convention: 0xXXYYYYYY
* - YYYYYY : Position in the register
* - XX : Register index
* - 00: CFGR1 register in SYSCFG
* - 01: CFGR3 register in SYSCFG (not available on STM32F373xC/STM32F378xx devices)
* @{
*/
#define HAL_REMAPDMA_ADC24_DMA2_CH34 (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
#define HAL_REMAPDMA_TIM16_DMA1_CH6 (0x00000800U) /*!< TIM16 DMA request remap
1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
#define HAL_REMAPDMA_TIM17_DMA1_CH7 (0x00001000U) /*!< TIM17 DMA request remap
1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
#define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3 (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
#define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4 (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
#if defined(SYSCFG_CFGR3_DMA_RMP)
#if !defined(HAL_REMAP_CFGR3_MASK)
#define HAL_REMAP_CFGR3_MASK (0x01000000U)
#endif
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2 (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 2 */
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4 (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 4 */
#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6 (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 6 */
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3 (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 3 */
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5 (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 5 */
#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7 (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 7 */
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7 (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 7 */
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3 (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 3 */
#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5 (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 5 */
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6 (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
11: Map on DMA1 channel 6 */
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2 (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
01: Map on DMA1 channel 2 */
#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4 (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
10: Map on DMA1 channel 4 */
#define HAL_REMAPDMA_ADC2_DMA1_CH2 (0x01000100U) /*!< ADC2 DMA remap
x0: No remap (ADC2 on DMA2)
10: Map on DMA1 channel 2 */
#define HAL_REMAPDMA_ADC2_DMA1_CH4 (0x01000300U) /*!< ADC2 DMA remap
11: Map on DMA1 channel 4 */
#endif /* SYSCFG_CFGR3_DMA_RMP */
#if defined(SYSCFG_CFGR3_DMA_RMP)
#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH2) == HAL_REMAPDMA_SPI1_RX_DMA1_CH2) || \
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH4) == HAL_REMAPDMA_SPI1_RX_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_SPI1_RX_DMA1_CH6) == HAL_REMAPDMA_SPI1_RX_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH3) == HAL_REMAPDMA_SPI1_TX_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH5) == HAL_REMAPDMA_SPI1_TX_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_SPI1_TX_DMA1_CH7) == HAL_REMAPDMA_SPI1_TX_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH7) == HAL_REMAPDMA_I2C1_RX_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH3) == HAL_REMAPDMA_I2C1_RX_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_I2C1_RX_DMA1_CH5) == HAL_REMAPDMA_I2C1_RX_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH6) == HAL_REMAPDMA_I2C1_TX_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH2) == HAL_REMAPDMA_I2C1_TX_DMA1_CH2) || \
(((RMP) & HAL_REMAPDMA_I2C1_TX_DMA1_CH4) == HAL_REMAPDMA_I2C1_TX_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH2) == HAL_REMAPDMA_ADC2_DMA1_CH2) || \
(((RMP) & HAL_REMAPDMA_ADC2_DMA1_CH4) == HAL_REMAPDMA_ADC2_DMA1_CH4))
#else
#define IS_DMA_REMAP(RMP) ((((RMP) & HAL_REMAPDMA_ADC24_DMA2_CH34) == HAL_REMAPDMA_ADC24_DMA2_CH34) || \
(((RMP) & HAL_REMAPDMA_TIM16_DMA1_CH6) == HAL_REMAPDMA_TIM16_DMA1_CH6) || \
(((RMP) & HAL_REMAPDMA_TIM17_DMA1_CH7) == HAL_REMAPDMA_TIM17_DMA1_CH7) || \
(((RMP) & HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) == HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3) || \
(((RMP) & HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) == HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4) || \
(((RMP) & HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_DAC2_CH1_DMA1_CH5) || \
(((RMP) & HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5) == HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5))
#endif /* SYSCFG_CFGR3_DMA_RMP && SYSCFG_CFGR1_DMA_RMP*/
/**
* @}
*/
#endif /* SYSCFG_CFGR1_DMA_RMP */
/** @defgroup HAL_Trigger_Remapping HAL Trigger Remapping
* Elements values convention: 0xXXYYYYYY
* - YYYYYY : Position in the register
* - XX : Register index
* - 00: CFGR1 register in SYSCFG
* - 01: CFGR3 register in SYSCFG
* @{
*/
#define HAL_REMAPTRIGGER_DAC1_TRIG (0x00000080U) /*!< DAC trigger remap (when TSEL = 001 on STM32F303xB/C and STM32F358xx devices)
0: No remap (DAC trigger is TIM8_TRGO)
1: Remap (DAC trigger is TIM3_TRGO) */
#define HAL_REMAPTRIGGER_TIM1_ITR3 (0x00000040U) /*!< TIM1 ITR3 trigger remap
0: No remap
1: Remap (TIM1_TRG3 = TIM17_OC) */
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
#if !defined(HAL_REMAP_CFGR3_MASK)
#define HAL_REMAP_CFGR3_MASK (0x01000000U)
#endif
#define HAL_REMAPTRIGGER_DAC1_TRIG3 (0x01010000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
0: Remap (DAC trigger is TIM15_TRGO)
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG1) */
#define HAL_REMAPTRIGGER_DAC1_TRIG5 (0x01020000U) /*!< DAC1_CH1 / DAC1_CH2 Trigger remap
0: No remap
1: Remap (DAC trigger is HRTIM1_DAC1_TRIG2) */
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3) || \
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG3) == HAL_REMAPTRIGGER_DAC1_TRIG3) || \
(((RMP) & HAL_REMAPTRIGGER_DAC1_TRIG5) == HAL_REMAPTRIGGER_DAC1_TRIG5))
#else
#define IS_HAL_REMAPTRIGGER(RMP) ((((RMP) & HAL_REMAPTRIGGER_DAC1) == HAL_REMAPTRIGGER_DAC1) || \
(((RMP) & HAL_REMAPTRIGGER_TIM1_ITR3) == HAL_REMAPTRIGGER_TIM1_ITR3))
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
/**
* @}
*/
#if defined (STM32F302xE)
/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
* @{
*/
#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
0: No remap (TIM1_CC3)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
0: No remap (TIM2_CC2)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
0: No remap (TIM4_CC4)
1: Remap (TIM20_CC1) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
0: No remap (TIM6_TRGO)
1: Remap (TIM20_CC2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
0: No remap (TIM3_CC4)
1: Remap (TIM20_CC3) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
0: No remap (TIM2_CC1)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
0: No remap (EXTI line 15)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
0: No remap (TIM3_CC1)
1: Remap (TIM20_CC4) */
#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
/**
* @}
*/
#endif /* STM32F302xE */
#if defined (STM32F303xE) || defined (STM32F398xx)
/** @defgroup HAL_ADC_Trigger_Remapping HAL ADC Trigger Remapping
* @{
*/
#define HAL_REMAPADCTRIGGER_ADC12_EXT2 SYSCFG_CFGR4_ADC12_EXT2_RMP /*!< Input trigger of ADC12 regular channel EXT2
0: No remap (TIM1_CC3)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT3 SYSCFG_CFGR4_ADC12_EXT3_RMP /*!< Input trigger of ADC12 regular channel EXT3
0: No remap (TIM2_CC2)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT5 SYSCFG_CFGR4_ADC12_EXT5_RMP /*!< Input trigger of ADC12 regular channel EXT5
0: No remap (TIM4_CC4)
1: Remap (TIM20_CC1) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT13 SYSCFG_CFGR4_ADC12_EXT13_RMP /*!< Input trigger of ADC12 regular channel EXT13
0: No remap (TIM6_TRGO)
1: Remap (TIM20_CC2) */
#define HAL_REMAPADCTRIGGER_ADC12_EXT15 SYSCFG_CFGR4_ADC12_EXT15_RMP /*!< Input trigger of ADC12 regular channel EXT15
0: No remap (TIM3_CC4)
1: Remap (TIM20_CC3) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT3 SYSCFG_CFGR4_ADC12_JEXT3_RMP /*!< Input trigger of ADC12 injected channel JEXT3
0: No remap (TIM2_CC1)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT6 SYSCFG_CFGR4_ADC12_JEXT6_RMP /*!< Input trigger of ADC12 injected channel JEXT6
0: No remap (EXTI line 15)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC12_JEXT13 SYSCFG_CFGR4_ADC12_JEXT13_RMP /*!< Input trigger of ADC12 injected channel JEXT13
0: No remap (TIM3_CC1)
1: Remap (TIM20_CC4) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT5 SYSCFG_CFGR4_ADC34_EXT5_RMP /*!< Input trigger of ADC34 regular channel EXT5
0: No remap (EXTI line 2)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT6 SYSCFG_CFGR4_ADC34_EXT6_RMP /*!< Input trigger of ADC34 regular channel EXT6
0: No remap (TIM4_CC1)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC34_EXT15 SYSCFG_CFGR4_ADC34_EXT15_RMP /*!< Input trigger of ADC34 regular channel EXT15
0: No remap (TIM2_CC1)
1: Remap (TIM20_CC1) */
#define HAL_REMAPADCTRIGGER_ADC34_JEXT5 SYSCFG_CFGR4_ADC34_JEXT5_RMP /*!< Input trigger of ADC34 injected channel JEXT5
0: No remap (TIM4_CC3)
1: Remap (TIM20_TRGO) */
#define HAL_REMAPADCTRIGGER_ADC34_JEXT11 SYSCFG_CFGR4_ADC34_JEXT11_RMP /*!< Input trigger of ADC34 injected channel JEXT11
0: No remap (TIM1_CC3)
1: Remap (TIM20_TRGO2) */
#define HAL_REMAPADCTRIGGER_ADC34_JEXT14 SYSCFG_CFGR4_ADC34_JEXT14_RMP /*!< Input trigger of ADC34 injected channel JEXT14
0: No remap (TIM7_TRGO)
1: Remap (TIM20_CC2) */
#define IS_HAL_REMAPADCTRIGGER(RMP) ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2) == HAL_REMAPADCTRIGGER_ADC12_EXT2) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3) == HAL_REMAPADCTRIGGER_ADC12_EXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5) == HAL_REMAPADCTRIGGER_ADC12_EXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13) == HAL_REMAPADCTRIGGER_ADC12_EXT13) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15) == HAL_REMAPADCTRIGGER_ADC12_EXT15) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3) == HAL_REMAPADCTRIGGER_ADC12_JEXT3) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6) == HAL_REMAPADCTRIGGER_ADC12_JEXT6) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5) == HAL_REMAPADCTRIGGER_ADC34_EXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6) == HAL_REMAPADCTRIGGER_ADC34_EXT6) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15) == HAL_REMAPADCTRIGGER_ADC34_EXT15) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5) == HAL_REMAPADCTRIGGER_ADC34_JEXT5) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
(((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
/**
* @}
*/
#endif /* STM32F303xE || STM32F398xx */
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#if defined(SYSCFG_CFGR1_I2C_PB6_FMP)
#define SYSCFG_FASTMODEPLUS_PB6 ((uint32_t)SYSCFG_CFGR1_I2C_PB6_FMP) /*!< Enable Fast-mode Plus on PB6 */
#endif /* SYSCFG_CFGR1_I2C_PB6_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB7_FMP)
#define SYSCFG_FASTMODEPLUS_PB7 ((uint32_t)SYSCFG_CFGR1_I2C_PB7_FMP) /*!< Enable Fast-mode Plus on PB7 */
#endif /* SYSCFG_CFGR1_I2C_PB7_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define SYSCFG_FASTMODEPLUS_PB8 ((uint32_t)SYSCFG_CFGR1_I2C_PB8_FMP) /*!< Enable Fast-mode Plus on PB8 */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
#define SYSCFG_FASTMODEPLUS_PB9 ((uint32_t)SYSCFG_CFGR1_I2C_PB9_FMP) /*!< Enable Fast-mode Plus on PB9 */
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
/**
* @}
*/
#if defined(SYSCFG_RCR_PAGE0)
/* CCM-SRAM defined */
/** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
* @{
*/
#define HAL_SYSCFG_WP_PAGE0 (SYSCFG_RCR_PAGE0) /*!< ICODE SRAM Write protection page 0 */
#define HAL_SYSCFG_WP_PAGE1 (SYSCFG_RCR_PAGE1) /*!< ICODE SRAM Write protection page 1 */
#define HAL_SYSCFG_WP_PAGE2 (SYSCFG_RCR_PAGE2) /*!< ICODE SRAM Write protection page 2 */
#define HAL_SYSCFG_WP_PAGE3 (SYSCFG_RCR_PAGE3) /*!< ICODE SRAM Write protection page 3 */
#if defined(SYSCFG_RCR_PAGE4)
/* More than 4KB CCM-SRAM defined */
#define HAL_SYSCFG_WP_PAGE4 (SYSCFG_RCR_PAGE4) /*!< ICODE SRAM Write protection page 4 */
#define HAL_SYSCFG_WP_PAGE5 (SYSCFG_RCR_PAGE5) /*!< ICODE SRAM Write protection page 5 */
#define HAL_SYSCFG_WP_PAGE6 (SYSCFG_RCR_PAGE6) /*!< ICODE SRAM Write protection page 6 */
#define HAL_SYSCFG_WP_PAGE7 (SYSCFG_RCR_PAGE7) /*!< ICODE SRAM Write protection page 7 */
#endif /* SYSCFG_RCR_PAGE4 */
#if defined(SYSCFG_RCR_PAGE8)
#define HAL_SYSCFG_WP_PAGE8 (SYSCFG_RCR_PAGE8) /*!< ICODE SRAM Write protection page 8 */
#define HAL_SYSCFG_WP_PAGE9 (SYSCFG_RCR_PAGE9) /*!< ICODE SRAM Write protection page 9 */
#define HAL_SYSCFG_WP_PAGE10 (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
#define HAL_SYSCFG_WP_PAGE11 (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
#define HAL_SYSCFG_WP_PAGE12 (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
#define HAL_SYSCFG_WP_PAGE13 (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
#define HAL_SYSCFG_WP_PAGE14 (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
#define HAL_SYSCFG_WP_PAGE15 (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
#endif /* SYSCFG_RCR_PAGE8 */
#if defined(SYSCFG_RCR_PAGE8)
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFU))
#elif defined(SYSCFG_RCR_PAGE4)
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x00FFU))
#else
#define IS_HAL_SYSCFG_WP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000FU))
#endif /* SYSCFG_RCR_PAGE8 */
/**
* @}
*/
#endif /* SYSCFG_RCR_PAGE0 */
/** @defgroup HAL_SYSCFG_Interrupts HAL SYSCFG Interrupts
* @{
*/
#define HAL_SYSCFG_IT_FPU_IOC (SYSCFG_CFGR1_FPU_IE_0) /*!< Floating Point Unit Invalid operation Interrupt */
#define HAL_SYSCFG_IT_FPU_DZC (SYSCFG_CFGR1_FPU_IE_1) /*!< Floating Point Unit Divide-by-zero Interrupt */
#define HAL_SYSCFG_IT_FPU_UFC (SYSCFG_CFGR1_FPU_IE_2) /*!< Floating Point Unit Underflow Interrupt */
#define HAL_SYSCFG_IT_FPU_OFC (SYSCFG_CFGR1_FPU_IE_3) /*!< Floating Point Unit Overflow Interrupt */
#define HAL_SYSCFG_IT_FPU_IDC (SYSCFG_CFGR1_FPU_IE_4) /*!< Floating Point Unit Input denormal Interrupt */
#define HAL_SYSCFG_IT_FPU_IXC (SYSCFG_CFGR1_FPU_IE_5) /*!< Floating Point Unit Inexact Interrupt */
#define IS_HAL_SYSCFG_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_0) == SYSCFG_CFGR1_FPU_IE_0) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_1) == SYSCFG_CFGR1_FPU_IE_1) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_2) == SYSCFG_CFGR1_FPU_IE_2) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_3) == SYSCFG_CFGR1_FPU_IE_3) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_4) == SYSCFG_CFGR1_FPU_IE_4) || \
(((__INTERRUPT__) & SYSCFG_CFGR1_FPU_IE_5) == SYSCFG_CFGR1_FPU_IE_5))
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
*/
/** @defgroup Debug_MCU_APB1_Freeze Freeze/Unfreeze APB1 Peripherals in Debug mode
* @{
*/
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM5_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_TIM18_STOP)
#define __HAL_FREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#define __HAL_UNFREEZE_TIM18_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM18_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
#if defined(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT */
#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
#if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
#define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
#define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
#endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
/**
* @}
*/
/** @defgroup Debug_MCU_APB2_Freeze Freeze/Unfreeze APB2 Peripherals in Debug mode
* @{
*/
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM15() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM16() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#define __HAL_DBGMCU_UNFREEZE_TIM17() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM19_STOP)
#define __HAL_FREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM19_STOP))
#define __HAL_UNFREEZE_TIM19_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM19_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM19_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_TIM20_STOP)
#define __HAL_FREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM20_STOP))
#define __HAL_UNFREEZE_TIM20_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM20_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_TIM20_STOP */
#if defined(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP)
#define __HAL_FREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
#define __HAL_UNFREEZE_HRTIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_HRTIM1_STOP))
#endif /* DBGMCU_APB2_FZ_DBG_HRTIM1_STOP */
/**
* @}
*/
/** @defgroup Memory_Mapping_Selection Memory Mapping Selection
* @{
*/
#if defined(SYSCFG_CFGR1_MEM_MODE)
/** @brief Main Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
#endif /* SYSCFG_CFGR1_MEM_MODE */
#if defined(SYSCFG_CFGR1_MEM_MODE_0)
/** @brief System Flash memory mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
}while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 */
#if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
/** @brief Embedded SRAM mapped at 0x00000000
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
}while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
#if defined(SYSCFG_CFGR1_MEM_MODE_2)
#define __HAL_SYSCFG_FMC_BANK() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_2); \
}while(0U)
#endif /* SYSCFG_CFGR1_MEM_MODE_2 */
/**
* @}
*/
/** @defgroup Encoder_Mode Encoder Mode
* @{
*/
#if defined(SYSCFG_CFGR1_ENCODER_MODE)
/** @brief No Encoder mode
*/
#define __HAL_REMAPENCODER_NONE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE))
#endif /* SYSCFG_CFGR1_ENCODER_MODE */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0)
/** @brief Encoder mode : TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
*/
#define __HAL_REMAPENCODER_TIM2() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_0; \
}while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_1)
/** @brief Encoder mode : TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively
*/
#define __HAL_REMAPENCODER_TIM3() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= SYSCFG_CFGR1_ENCODER_MODE_1; \
}while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_1 */
#if defined(SYSCFG_CFGR1_ENCODER_MODE_0) && defined(SYSCFG_CFGR1_ENCODER_MODE_1)
/** @brief Encoder mode : TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 (STM32F303xB/C and STM32F358xx devices)
*/
#define __HAL_REMAPENCODER_TIM4() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_ENCODER_MODE); \
SYSCFG->CFGR1 |= (SYSCFG_CFGR1_ENCODER_MODE_0 | SYSCFG_CFGR1_ENCODER_MODE_1); \
}while(0U)
#endif /* SYSCFG_CFGR1_ENCODER_MODE_0 && SYSCFG_CFGR1_ENCODER_MODE_1 */
/**
* @}
*/
/** @defgroup DMA_Remap_Enable DMA Remap Enable
* @{
*/
#if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
*/
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 |= ((__DMA_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 |= (__DMA_REMAP__))); \
}while(0U)
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
(((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 &= (~(__DMA_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 &= ~(__DMA_REMAP__))); \
}while(0U)
#elif defined(SYSCFG_CFGR1_DMA_RMP)
/** @brief DMA remapping enable/disable macros
* @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
*/
#define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
SYSCFG->CFGR1 |= (__DMA_REMAP__); \
}while(0U)
#define __HAL_DMA_REMAP_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_DMA_REMAP((__DMA_REMAP__))); \
SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
}while(0U)
#endif /* SYSCFG_CFGR3_DMA_RMP || SYSCFG_CFGR1_DMA_RMP */
/**
* @}
*/
/** @defgroup FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
* That you can find above these macros.
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0U)
/**
* @}
*/
/** @defgroup Floating_Point_Unit_Interrupts_Enable Floating Point Unit Interrupts Enable
* @{
*/
/** @brief SYSCFG interrupt enable/disable macros
* @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts
*/
#define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
SYSCFG->CFGR1 |= (__INTERRUPT__); \
}while(0U)
#define __HAL_SYSCFG_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
SYSCFG->CFGR1 &= ~(__INTERRUPT__); \
}while(0U)
/**
* @}
*/
#if defined(SYSCFG_CFGR1_USB_IT_RMP)
/** @defgroup USB_Interrupt_Remap USB Interrupt Remap
* @{
*/
/** @brief USB interrupt remapping enable/disable macros
*/
#define __HAL_REMAPINTERRUPT_USB_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_USB_IT_RMP))
#define __HAL_REMAPINTERRUPT_USB_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_USB_IT_RMP))
/**
* @}
*/
#endif /* SYSCFG_CFGR1_USB_IT_RMP */
#if defined(SYSCFG_CFGR1_VBAT)
/** @defgroup VBAT_Monitoring_Enable VBAT Monitoring Enable
* @{
*/
/** @brief SYSCFG interrupt enable/disable macros
*/
#define __HAL_SYSCFG_VBAT_MONITORING_ENABLE() (SYSCFG->CFGR1 |= (SYSCFG_CFGR1_VBAT))
#define __HAL_SYSCFG_VBAT_MONITORING_DISABLE() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_VBAT))
/**
* @}
*/
#endif /* SYSCFG_CFGR1_VBAT */
#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
* @{
*/
/** @brief SYSCFG Break Lockup lock
* Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
#if defined(SYSCFG_CFGR2_PVD_LOCK)
/** @defgroup PVD_Lock_Enable PVD Lock
* @{
*/
/** @brief SYSCFG Break PVD lock
* Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_PVD_LOCK */
#if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
/** @defgroup SRAM_Parity_Lock SRAM Parity Lock
* @{
*/
/** @brief SYSCFG Break SRAM PARITY lock
* Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
* @note The selected configuration is locked and can be unlocked by system reset
*/
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
/** @defgroup Trigger_Remapping_Enable Trigger Remapping Enable
* @{
*/
#if defined(SYSCFG_CFGR3_TRIGGER_RMP)
/** @brief Trigger remapping enable/disable macros
* @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
*/
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 |= ((__TRIGGER_REMAP__) & ~HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__))); \
}while(0U)
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ? \
(SYSCFG->CFGR3 &= (~(__TRIGGER_REMAP__) | HAL_REMAP_CFGR3_MASK)) : \
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__))); \
}while(0U)
#else
/** @brief Trigger remapping enable/disable macros
* @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
*/
#define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(SYSCFG->CFGR1 |= (__TRIGGER_REMAP__)); \
}while(0U)
#define __HAL_REMAPTRIGGER_DISABLE(__TRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__))); \
(SYSCFG->CFGR1 &= ~(__TRIGGER_REMAP__)); \
}while(0U)
#endif /* SYSCFG_CFGR3_TRIGGER_RMP */
/**
* @}
*/
#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
/** @defgroup ADC_Trigger_Remapping_Enable ADC Trigger Remapping Enable
* @{
*/
/** @brief ADC trigger remapping enable/disable macros
* @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
*/
#define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
(SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__)); \
}while(0U)
#define __HAL_REMAPADCTRIGGER_DISABLE(__ADCTRIGGER_REMAP__) do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__))); \
(SYSCFG->CFGR4 &= ~(__ADCTRIGGER_REMAP__)); \
}while(0U)
/**
* @}
*/
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(SYSCFG_CFGR2_BYP_ADDR_PAR)
/** @defgroup RAM_Parity_Check_Disable RAM Parity Check Disable
* @{
*/
/**
* @brief Parity check on RAM disable macro
* @note Disabling the parity check on RAM locks the configuration bit.
* To re-enable the parity check on RAM perform a system reset.
*/
#define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (*(__IO uint32_t *) CFGR2_BYPADDRPAR_BB = 0x00000001U)
/**
* @}
*/
#endif /* SYSCFG_CFGR2_BYP_ADDR_PAR */
#if defined(SYSCFG_RCR_PAGE0)
/** @defgroup CCM_RAM_Page_Write_Protection_Enable CCM RAM page write protection enable
* @{
*/
/** @brief CCM RAM page write protection enable macro
* @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection
* @note write protection can only be disabled by a system reset
*/
#define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__) do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
SYSCFG->RCR |= (__PAGE_WP__); \
}while(0U)
/**
* @}
*/
#endif /* SYSCFG_RCR_PAGE0 */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/**
* @}
*/
/* Exported variables ---------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_adc.h Normal file
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@@ -0,0 +1,273 @@
/**
******************************************************************************
* @file stm32f3xx_hal_adc.h
* @author MCD Application Team
* @brief Header file containing functions prototypes of ADC HAL library.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_ADC_H
#define __STM32F3xx_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/* Include ADC HAL Extended module */
/* (include on top of file since ADC structures are defined in extended file) */
#include "stm32f3xx_hal_adc_ex.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on, multimode ADC master control) */
#define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master ( */
/**
* @brief ADC handle Structure definition
*/
typedef struct __ADC_HandleTypeDef
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC required parameters */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ /*!< ADC end of sampling callback */
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}ADC_HandleTypeDef;
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL ADC Callback ID enumeration definition
*/
typedef enum
{
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
} HAL_ADC_CallbackIDTypeDef;
/**
* @brief HAL ADC Callback pointer definition
*/
typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup ADC_Exported_Macro ADC Exported Macros
* @{
*/
/** @brief Reset ADC handle state
* @param __HANDLE__ ADC handle
* @retval None
*/
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
#endif
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions ADC Exported Functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
/* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
* @}
*/
/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
* @brief ADC Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32F3xx_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_can.h
* @author MCD Application Team
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_CAN_H
#define STM32F3xx_HAL_CAN_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
#if defined (CAN)
/** @addtogroup CAN
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
} HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the length of a time quantum.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
uint32_t Mode; /*!< Specifies the CAN operating mode.
This parameter can be a value of @ref CAN_operating_mode */
uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
is allowed to lengthen or shorten a bit to perform resynchronization.
This parameter can be a value of @ref CAN_synchronisation_jump_width */
uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
This parameter can be set to ENABLE or DISABLE. */
} CAN_InitTypeDef;
/**
* @brief CAN filter configuration structure definition
*/
typedef struct
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
This parameter mus be a number between Min_Data = 0 and Max_Data = 13. */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
uint32_t FilterScale; /*!< Specifies the filter scale.
This parameter can be a value of @ref CAN_filter_scale */
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be a value of @ref CAN_filter_activation */
uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
STM32F3xx devices don't support slave CAN instance (dual CAN). Therefore
this parameter is meaningless but it has been kept for compatibility accross
STM32 families. */
} CAN_FilterTypeDef;
/**
* @brief CAN Tx message header structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
@note: Time Triggered Communication Mode must be enabled.
@note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
This parameter can be set to ENABLE or DISABLE. */
} CAN_TxHeaderTypeDef;
/**
* @brief CAN Rx message header structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
@note: Time Triggered Communication Mode must be enabled.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
} CAN_RxHeaderTypeDef;
/**
* @brief CAN handle Structure definition
*/
typedef struct __CAN_HandleTypeDef
{
CAN_TypeDef *Instance; /*!< Register base address */
CAN_InitTypeDef Init; /*!< CAN required parameters */
__IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
__IO uint32_t ErrorCode; /*!< CAN Error code.
This parameter can be a value of @ref CAN_Error_Code */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */
void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */
void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */
void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */
void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */
void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */
void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */
void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */
void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */
void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */
void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */
void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */
void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */
void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */
void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
} CAN_HandleTypeDef;
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/**
* @brief HAL CAN common Callback ID enumeration definition
*/
typedef enum
{
HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */
HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */
HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */
HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */
HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */
HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */
HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */
HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */
HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */
HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */
HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */
HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */
HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */
HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */
HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */
} HAL_CAN_CallbackIDTypeDef;
/**
* @brief HAL CAN Callback pointer definition
*/
typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */
#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */
#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */
/**
* @}
*/
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
/**
* @}
*/
/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
/**
* @}
*/
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
/**
* @}
*/
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
/**
* @}
*/
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
/**
* @}
*/
/** @defgroup CAN_filter_activation CAN Filter Activation
* @{
*/
#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */
#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */
/**
* @}
*/
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
* @{
*/
#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
/**
* @}
*/
/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
* @{
*/
#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
/**
* @}
*/
/** @defgroup CAN_flags CAN Flags
* @{
*/
/* Transmit Flags */
#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
/* Receive Flags */
#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
/* Error Flags */
#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
/** @defgroup CAN_Interrupts CAN Interrupts
* @{
*/
/* Transmit Interrupt */
#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
/** @brief Reset CAN handle state
* @param __HANDLE__ CAN handle.
* @retval None
*/
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_CAN_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
/**
* @brief Enable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt sources to enable.
* This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupts.
* @param __HANDLE__ CAN handle.
* @param __INTERRUPT__ CAN Interrupt sources to disable.
* This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** @brief Check if the specified CAN interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the CAN Handle.
* @param __INTERRUPT__ specifies the CAN interrupt source to check.
* This parameter can be a value of @arg CAN_Interrupts
* @retval The state of __IT__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
/** @brief Check whether the specified CAN flag is set or not.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of @arg CAN_flags
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Clear the specified CAN pending flag.
* @param __HANDLE__ specifies the CAN Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
* @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
* @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
* @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
* @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
* @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
* @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
* @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
* @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
* @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
* @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
* @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
* @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
* @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
* @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
* @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
* @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
* @retval None
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
(((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group3 Control functions
* @brief Control functions
* @{
*/
/* Control functions **********************************************************/
HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
* @brief Interrupts management
* @{
*/
/* Interrupts management ******************************************************/
HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
* @brief Callback functions
* @{
*/
/* Callbacks functions ********************************************************/
void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
* @brief CAN Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CAN_Private_Types CAN Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CAN_Private_Variables CAN Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
/* Private Macros -----------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
((ACTIVATION) == CAN_FILTER_ENABLE))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
#endif /* CAN */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_CAN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_cec.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_cec.h
* @author MCD Application Team
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_CEC_H
#define STM32F3xx_HAL_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
#if defined (CEC)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CEC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
*/
/**
* @brief CEC Init Structure definition
*/
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
It can be one of @ref CEC_Signal_Free_Time
and belongs to the set {0,...,7} where
0x0 is the default configuration
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
or CEC_EXTENDED_TOLERANCE */
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
CEC_RX_STOP_ON_BRE: reception is stopped. */
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.
a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
there is no error-bit generation in case of Short Bit Period Error detection in
a broadcast message while LSTN bit is set. */
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
own address (OAR). Messages addressed to different destination are ignored.
Broadcast messages are always received.
CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
} CEC_InitTypeDef;
/**
* @brief HAL CEC State definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 CEC peripheral initialization status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 CEC peripheral initialization status
* 0 : Reset (peripheral not initialized)
* 1 : Init done (peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef uint32_t HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
typedef struct __CEC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __CEC_HandleTypeDef
*hcec); /*!< CEC Tx Transfer completed callback */
void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */
void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */
void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */
void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */
#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */
} CEC_HandleTypeDef;
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL CEC Callback ID enumeration definition
*/
typedef enum
{
HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */
HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */
HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */
HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */
HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */
} HAL_CEC_CallbackIDTypeDef;
/**
* @brief HAL CEC Callback pointer definition
*/
typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */
typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,
uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
/** @defgroup CEC_State_Definition CEC State Code Definition
* @{
*/
#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */
/**
* @}
*/
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
/**
* @}
*/
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
*/
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
*/
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
*/
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
*/
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
*/
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
*/
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
*/
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
/**
* @}
*/
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
/**
* @}
*/
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
/**
* @}
*/
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
* @{
*/
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
#define CEC_IT_TXERR CEC_IER_TXERRIE
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
#define CEC_IT_TXEND CEC_IER_TXENDIE
#define CEC_IT_TXBR CEC_IER_TXBRIE
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
#define CEC_IT_LBPE CEC_IER_LBPEIE
#define CEC_IT_SBPE CEC_IER_SBPEIE
#define CEC_IT_BRE CEC_IER_BREIE
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
#define CEC_IT_RXEND CEC_IER_RXENDIE
#define CEC_IT_RXBR CEC_IER_RXBRIE
/**
* @}
*/
/** @defgroup CEC_Flags_Definitions CEC Flags definition
* @{
*/
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define CEC_FLAG_TXERR CEC_ISR_TXERR
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define CEC_FLAG_TXEND CEC_ISR_TXEND
#define CEC_FLAG_TXBR CEC_ISR_TXBR
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define CEC_FLAG_LBPE CEC_ISR_LBPE
#define CEC_FLAG_SBPE CEC_ISR_SBPE
#define CEC_FLAG_BRE CEC_ISR_BRE
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define CEC_FLAG_RXEND CEC_ISR_RXEND
#define CEC_FLAG_RXBR CEC_ISR_RXBR
/**
* @}
*/
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CEC_Exported_Macros CEC Exported Macros
* @{
*/
/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__ CEC handle.
* @retval None
*/
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
} while(0)
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval ITStatus
*/
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1)
* @param __HANDLE__ specifies the CEC Handle.
* @param __FLAG__ specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval none
*/
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__ specifies the CEC Handle.
* @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag
* @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register
* @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
* @param __HANDLE__ specifies the CEC Handle.
* @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CEC_Exported_Functions
* @{
*/
/** @addtogroup CEC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,
pCEC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);
#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,
uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CEC_Private_Types CEC Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CEC_Private_Variables CEC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CEC_Private_Macros CEC Private Macros
* @{
*/
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
((__MODE__) == CEC_FULL_LISTENING_MODE))
/** @brief Check CEC message size.
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header).
* @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* CEC */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xxHAL_CEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_comp.h
* @author MCD Application Team
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_COMP_H
#define STM32F3xx_HAL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t InvertingInput; /*!< Selects the inverting input of the comparator.
This parameter can be a value of @ref COMPEx_InvertingInput */
uint32_t NonInvertingInput; /*!< Selects the non inverting input of the comparator.
This parameter can be a value of @ref COMPEx_NonInvertingInput
Note: Only available on STM32F302xB/xC, STM32F303xB/xC and STM32F358xx devices */
uint32_t Output; /*!< Selects the output redirection of the comparator.
This parameter can be a value of @ref COMPEx_Output */
uint32_t OutputPol; /*!< Selects the output polarity of the comparator.
This parameter can be a value of @ref COMP_OutputPolarity */
uint32_t Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
This parameter can be a value of @ref COMPEx_Hysteresis
Note: Only available on STM32F302xB/xC, STM32F303xB/xC, STM32F373xB/xC, STM32F358xx and STM32F378xx devices */
uint32_t BlankingSrce; /*!< Selects the output blanking source of the comparator.
This parameter can be a value of @ref COMPEx_BlankingSrce
Note: Not available on STM32F373xB/C and STM32F378xx devices */
uint32_t Mode; /*!< Selects the operating consumption mode of the comparator
to adjust the speed/consumption.
This parameter can be a value of @ref COMPEx_Mode
Note: Not available on STM32F301x6/x8, STM32F302x6/x8, STM32F334x6/x8, STM32F318xx and STM32F328xx devices */
uint32_t WindowMode; /*!< Selects the window mode of the comparator X (X=2U, 4 or 6 if available).
This parameter can be a value of @ref COMPEx_WindowMode */
uint32_t TriggerMode; /*!< Selects the trigger mode of the comparator (interrupt mode).
This parameter can be a value of @ref COMP_TriggerMode */
} COMP_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized or disabled */
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
HAL_COMP_STATE_READY_LOCKED = 0x11U, /*!< COMP initialized but the configuration is locked */
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */
} HAL_COMP_StateTypeDef;
/**
* @brief COMP Handle Structure definition
*/
typedef struct __COMP_HandleTypeDef
{
COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
__IO uint32_t ErrorCode; /*!< COMP Error code */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
} COMP_HandleTypeDef;
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL COMP Callback ID enumeration definition
*/
typedef enum
{
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
} HAL_COMP_CallbackIDTypeDef;
/**
* @brief HAL COMP Callback pointer definition
*/
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_Error_Code COMP Error Code
* @{
*/
#define HAL_COMP_ERROR_NONE (0x00U) /*!< No error */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U) /*!< Invalid Callback error */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup COMP_OutputPolarity COMP Output Polarity
* @{
*/
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000U) /*!< COMP output on GPIO isn't inverted */
#define COMP_OUTPUTPOL_INVERTED COMP_CSR_COMPxPOL /*!< COMP output on GPIO is inverted */
/**
* @}
*/
/** @defgroup COMP_OutputLevel COMP Output Level
* @{
*/
/* When output polarity is not inverted, comparator output is low when
the non-inverting input is at a lower voltage than the inverting input*/
#define COMP_OUTPUTLEVEL_LOW (0x00000000U)
/* When output polarity is not inverted, comparator output is high when
the non-inverting input is at a higher voltage than the inverting input */
#define COMP_OUTPUTLEVEL_HIGH COMP_CSR_COMPxOUT
/**
* @}
*/
/** @defgroup COMP_TriggerMode COMP Trigger Mode
* @{
*/
#define COMP_TRIGGERMODE_NONE (0x00000000U) /*!< No External Interrupt trigger detection */
#define COMP_TRIGGERMODE_IT_RISING (0x00000001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_IT_FALLING (0x00000002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_IT_RISING_FALLING (0x00000003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define COMP_TRIGGERMODE_EVENT_RISING (0x00000010U) /*!< Event Mode with Rising edge trigger detection */
#define COMP_TRIGGERMODE_EVENT_FALLING (0x00000020U) /*!< Event Mode with Falling edge trigger detection */
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (0x00000030U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup COMP_State_Lock COMP State Lock
* @{
*/
#define COMP_STATE_BIT_LOCK (0x00000010U) /* Lock bit in COMP handle state */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup COMP_Exported_Macros COMP Exported Macros
* @{
*/
/** @brief Reset COMP handle state.
* @param __HANDLE__ COMP handle.
* @retval None
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
#endif
/**
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
* @param __HANDLE__ COMP handle
* @retval None
*/
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/**
* @}
*/
/* Include COMP HAL Extended module */
#include "stm32f3xx_hal_comp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup COMP_Exported_Functions
* @{
*/
/** @addtogroup COMP_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup COMP_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
/* Callback in Interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup COMP_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral State functions **************************************************/
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_Private_Macros COMP Private Macros
* @{
*/
/** @defgroup COMP_IS_COMP_Definitions COMP Private macros to check input parameters
* @{
*/
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
((__POL__) == COMP_OUTPUTPOL_INVERTED))
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_COMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
#define __STM32F3xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CAN_MODULE_ENABLED
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
#define HAL_CEC_MODULE_ENABLED
#define HAL_COMP_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_PCCARD_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_HRTIM_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_OPAMP_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SDADC_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SMBUS_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_TSC_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
* Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
* Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE (40000U)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
*/
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
* - External clock not generated on EVAL 373
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE (8000000U) /*!< Value of the External oscillator in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 1U
#define INSTRUCTION_CACHE_ENABLE 0U
#define DATA_CACHE_ENABLE 0U
#define USE_SPI_CRC 1U
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */
#define USE_HAL_SDADC_REGISTER_CALLBACKS 0U /* SDADC register callback disabled */
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U /* HRTIM register callback disabled */
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */
#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1U*/
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f3xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f3xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f3xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f3xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f3xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f3xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f3xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
#include "stm32f3xx_hal_can_legacy.h"
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f3xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32f3xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f3xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f3xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f3xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32f3xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32f3xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32f3xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h"
#endif /* HAL_PCCARD_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f3xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f3xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f3xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f3xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32f3xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f3xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f3xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f3xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SDADC_MODULE_ENABLED
#include "stm32f3xx_hal_sdadc.h"
#endif /* HAL_SDADC_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f3xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f3xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f3xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f3xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32f3xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f3xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f3xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f3xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CORTEX_H
#define __STM32F3xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK (0x00000004U)
/**
* @}
*/
#if (__MPU_PRESENT == 1U)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U)
#define MPU_HARDFAULT_NMI (0x00000002U)
#define MPU_PRIVILEGED_DEFAULT (0x00000004U)
#define MPU_HFNMI_PRIVDEF (0x00000006U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported Macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1U)
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
* @{
*/
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
/**
* @}
*/
#if (__MPU_PRESENT == 1U)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @brief CORTEX private functions
* @{
*/
#if (__MPU_PRESENT == 1U)
void HAL_MPU_Disable(void);
void HAL_MPU_Enable(uint32_t MPU_Control);
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_CRC_H
#define STM32F3xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef;
/**
* @brief CRC Init Structure definition
*/
typedef struct
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal,
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
is set to DEFAULT_INIT_VALUE_ENABLE. */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
becomes 0x58D43CB2
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
0x1A2B3C4D becomes 0xD458B23C
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
into 0x22CC4488 */
} CRC_InitTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
(8-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
half-words (16-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
(32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
error must occur if InputBufferFormat is not one of the three values listed
above */
} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
* @{
*/
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
/**
* @}
*/
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ CRC handle
* @param __INIT__ 32-bit initial value
* @retval None
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
* @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
((LENGTH) == CRC_POLYLENGTH_16B) || \
((LENGTH) == CRC_POLYLENGTH_8B) || \
((LENGTH) == CRC_POLYLENGTH_7B))
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
/* Include CRC HAL Extended module */
#include "stm32f3xx_hal_crc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_crc_ex.h
* @author MCD Application Team
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_CRC_EX_H
#define STM32F3xx_HAL_CRC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{
*/
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/**
* @}
*/
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
/**
* @brief Set CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
* @{
*/
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions
* @{
*/
/** @addtogroup CRCEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_CRC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_dac.h
* @author MCD Application Team
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_DAC_H
#define STM32F3xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
}HAL_DAC_StateTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DACEx_trigger_selection */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer
For a given DAC channel, is this paramater applies then DAC_OutputSwitch
does not apply */
uint32_t DAC_OutputSwitch; /*!< Specifies whether the DAC channel output switch is enabled or disabled.
This parameter can be a value of @ref DAC_OutputSwitch
For a given DAC channel, is this paramater applies then DAC_OutputBuffer
does not apply */
}DAC_ChannelConfTypeDef;
/**
* @brief DAC handle Structure definition
*/
typedef struct __DAC_HandleTypeDef
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1U */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2U */
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef* hdac);
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback ) (struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}DAC_HandleTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DAC Callback ID enumeration definition
*/
typedef enum
{
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSP_INIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSP_DEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
}HAL_DAC_CallbackIDTypeDef;
/**
* @brief HAL DAC Callback pointer definition
*/
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup DAC_lfsrunmask_triangleamplitude DAC lfsrunmask triangleamplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 (0x00000000U) /*!< Select max triangle amplitude of 1U */
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3U */
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7U */
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15U */
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31U */
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63U */
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127U */
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255U */
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511U */
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023U */
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047U */
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095U */
/**
* @}
*/
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE (0x00000000U)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
/**
* @}
*/
#if defined(DAC_CR_OUTEN1)
/** @defgroup DAC_output_switch DAC output switch
* @{
*/
#define DAC_OUTPUTSWITCH_DISABLE (0x00000000U)
#define DAC_OUTPUTSWITCH_ENABLE ((uint32_t)DAC_CR_OUTEN1)
/**
* @}
*/
#endif /* DAC_CR_OUTEN1 */
/** @defgroup DAC_data_alignement DAC data alignement
* @{
*/
#define DAC_ALIGN_12B_R (0x00000000U)
#define DAC_ALIGN_12B_L (0x00000004U)
#define DAC_ALIGN_8B_R (0x00000008U)
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_interrupts_definition DAC interrupts definition
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1)
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_CR_DMAUDRIE2)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
/** @brief Reset DAC handle state
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel
* @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Disable the DAC channel
* @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Set DHR12R1 alignment
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @addtogroup DAC_Private_Macros
* @{
*/
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#if defined(DAC_CR_OUTEN1)
#define IS_DAC_OUTPUT_SWITCH_STATE(STATE) (((STATE) == DAC_OUTPUTSWITCH_DISABLE) || \
((STATE) == DAC_OUTPUTSWITCH_ENABLE))
#endif /* DAC_CR_OUTEN1 */
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
/**
* @}
*/
/* Include DAC HAL Extended module */
#include "stm32f3xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId, pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_dac_ex.h
* @author MCD Application Team
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_DAC_EX_H
#define STM32F3xx_HAL_DAC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
/** @defgroup DACEx_trigger_selection DACEx trigger selection
* @{
*/
#if defined(STM32F301x8) || defined(STM32F318xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F301x8 || STM32F318xx */
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F302x8)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F302xE || */
/* STM32F302xC || */
/* STM32F302x8 */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 selection */
#define DAC_TRIGGER_T8_TRGO DAC_TRIGGER_T3_TRGO /*!< TIM8 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM8 selection */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F328xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F303x8 || STM32F328xx */
#if defined(STM32F373xC) || defined(STM32F378xx)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel (DAC1) */
#define DAC_TRIGGER_T18_TRGO DAC_TRIGGER_T5_TRGO /*!< TIM18 TRGO selected as external conversion trigger for DAC channel (DAC2) */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32F334x8)
#define DAC_TRIGGER_NONE (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG) for TIM3 remap */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel
Use __HAL_REMAPTRIGGER_DISABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for TIM15 selection */
#define DAC_TRIGGER_HRTIM1_DACTRG1 DAC_TRIGGER_T15_TRGO /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG3) for HRTIM1 DACTRG1 selection */
#define DAC_TRIGGER_HRTIM1_DACTRG2 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC channel (DAC1)
Use __HAL_REMAPTRIGGER_ENABLE(HAL_REMAPTRIGGER_DAC1_TRIG5) for HRTIM1 DACTRG2 remap */
#define DAC_TRIGGER_HRTIM1_DACTRG3 DAC_TRIGGER_HRTIM1_DACTRG2 /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC channel (DAC2)*/
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM1_DACTRG2) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#endif /* STM32F334x8 */
/**
* @}
*/
/** @defgroup DACEx_Channel_selection DACEx Channel selection
* @{
*/
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
#endif /* STM32F302xE || */
/* STM32F302xC || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
#define DAC_CHANNEL_1 (0x00000000U) /*!< DAC Channel 1U */
#define DAC_CHANNEL_2 (0x00000010U) /*!< DAC Channel 2U */
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F373xC || STM32F378xx */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
#if defined(STM32F302xE) || \
defined(STM32F302xC) || \
defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
#endif /* STM32F302xE || */
/* STM32F302xC || */
/* STM32F301x8 || STM32F302x8 || STM32F318xx */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
#if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#endif /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F373xC || STM32F378xx */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DACEx_Exported_Functions
* @{
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx || */
/* STM32F373xC || STM32F378xx */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_HAL_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DEF
#define __STM32F3xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
#include "Legacy/stm32_hal_legacy.h"
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == BIT)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
(__DMA_HANDLE_).Parent = (__HANDLE__); \
} while(0U)
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1U)
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifdef __cplusplus
}
#endif
#endif /* ___STM32F3xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DMA_H
#define __STM32F3xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03 /*!< DMA timeout state */
}HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01 /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04 /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_DMA_ERROR_TE (0x00000001U) /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER (0x00000004U) /*!< no ongoin transfer */
#define HAL_DMA_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U) /*!< Not supported mode */
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY (0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE (0x00000000U) /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE (0x00000000U) /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE (0x00000000U) /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE (0x00000000U) /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL (0x00000000U) /*!< Normal Mode */
#define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW (0x00000000U) /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
#define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
/**
* @}
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 (0x00000001U)
#define DMA_FLAG_TC1 (0x00000002U)
#define DMA_FLAG_HT1 (0x00000004U)
#define DMA_FLAG_TE1 (0x00000008U)
#define DMA_FLAG_GL2 (0x00000010U)
#define DMA_FLAG_TC2 (0x00000020U)
#define DMA_FLAG_HT2 (0x00000040U)
#define DMA_FLAG_TE2 (0x00000080U)
#define DMA_FLAG_GL3 (0x00000100U)
#define DMA_FLAG_TC3 (0x00000200U)
#define DMA_FLAG_HT3 (0x00000400U)
#define DMA_FLAG_TE3 (0x00000800U)
#define DMA_FLAG_GL4 (0x00001000U)
#define DMA_FLAG_TC4 (0x00002000U)
#define DMA_FLAG_HT4 (0x00004000U)
#define DMA_FLAG_TE4 (0x00008000U)
#define DMA_FLAG_GL5 (0x00010000U)
#define DMA_FLAG_TC5 (0x00020000U)
#define DMA_FLAG_HT5 (0x00040000U)
#define DMA_FLAG_TE5 (0x00080000U)
#define DMA_FLAG_GL6 (0x00100000U)
#define DMA_FLAG_TC6 (0x00200000U)
#define DMA_FLAG_HT6 (0x00400000U)
#define DMA_FLAG_TE6 (0x00800000U)
#define DMA_FLAG_GL7 (0x01000000U)
#define DMA_FLAG_TC7 (0x02000000U)
#define DMA_FLAG_HT7 (0x04000000U)
#define DMA_FLAG_TE7 (0x08000000U)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state
* @param __HANDLE__ DMA handle.
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
/**
* @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disables the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA Channel interrupt is enabled or disabled.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask
* @arg DMA_IT_HT: Half transfer complete interrupt mask
* @arg DMA_IT_TE: Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Returns the number of remaining data units in the current DMAy Channelx transfer.
* @param __HANDLE__ DMA handle
*
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
/* Include DMA HAL Extended module */
#include "stm32f3xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Input and Output operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3 Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @brief DMA private macros
* @{
*/
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U))
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_DMA_EX_H
#define __STM32F3xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Macros DMA Extended Exported Macros
* @{
*/
/* Interrupt & Flag management */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
defined(STM32F373xC) || defined(STM32F378xx)
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
DMA_FLAG_TC5)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
DMA_FLAG_HT5)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
DMA_FLAG_TE5)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_GL7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GL4 :\
DMA_FLAG_GL5)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
(DMA1->ISR & (__FLAG__)))
/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 or 1_5 (depending on DMA1 or DMA2) to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
(DMA1->IFCR = (__FLAG__)))
/**
* @}
*/
#else /* STM32F301x8_STM32F302x8_STM32F318xx_STM32F303x8_STM32F334x8_STM32F328xx Product devices */
/** @defgroup DMA_Low_density_Medium_density_Product_devices DMA Low density and Medium density product devices
* @{
*/
/**
* @brief Returns the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
/**
* @brief Returns the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
/**
* @brief Returns the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GL1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GL2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GL3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GL4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GL5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GL6 :\
DMA_FLAG_GL7)
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
/**
* @brief Clears the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx: Transfer complete flag
* @arg DMA_FLAG_HTx: Half transfer complete flag
* @arg DMA_FLAG_TEx: Transfer error flag
* Where x can be 1_7 to select the DMA Channel flag.
* @retval None
*/
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#endif /* __STM32F3xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_exti.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_EXTI_H
#define STM32F3xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
/**
* @brief HAL EXTI common Callback ID enumeration definition
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u) /*!< External interrupt line 0 */
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u) /*!< External interrupt line 1 */
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u) /*!< External interrupt line 2 */
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u) /*!< External interrupt line 3 */
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u) /*!< External interrupt line 4 */
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u) /*!< External interrupt line 5 */
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u) /*!< External interrupt line 6 */
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u) /*!< External interrupt line 7 */
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u) /*!< External interrupt line 8 */
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u) /*!< External interrupt line 9 */
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au) /*!< External interrupt line 10 */
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu) /*!< External interrupt line 11 */
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu) /*!< External interrupt line 12 */
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du) /*!< External interrupt line 13 */
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu) /*!< External interrupt line 14 */
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu) /*!< External interrupt line 15 */
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#if defined(EXTI_IMR_MR18)
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
#else
#define EXTI_LINE_18 (EXTI_RESERVED | EXTI_REG1 | 0x12u)
#endif /* EXTI_IMR_MR18 */
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u) /*!< External interrupt line 19 Connected to the RTC tamper and Timestamps */
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u) /*!< External interrupt line 20 Connected to the RTC wakeup timer */
#if defined(EXTI_IMR_MR21)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */
#else
#define EXTI_LINE_21 (EXTI_RESERVED | EXTI_REG1 | 0x15u)
#endif /* EXTI_IMR_MR21 */
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) /*!< External interrupt line 23 Connected to the internal I2C1 wakeup event */
#if defined(EXTI_IMR_MR24)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) /*!< External interrupt line 24 Connected to the internal I2C2 wakeup event */
#else
#define EXTI_LINE_24 (EXTI_RESERVED | EXTI_REG1 | 0x18u)
#endif /* EXTI_IMR_MR24 */
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) /*!< External interrupt line 25 Connected to the internal USART1 wakeup event */
#if defined(EXTI_IMR_MR26)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) /*!< External interrupt line 26 Connected to the internal USART2 wakeup event */
#else
#define EXTI_LINE_26 (EXTI_RESERVED | EXTI_REG1 | 0x1Au)
#endif /* EXTI_IMR_MR26 */
#if defined(EXTI_IMR_MR27)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) /*!< External interrupt line 27 Connected to the internal I2C3 wakeup event */
#else
#define EXTI_LINE_27 (EXTI_RESERVED | EXTI_REG1 | 0x1Bu)
#endif /* EXTI_IMR_MR27 */
#if defined(EXTI_IMR_MR28)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) /*!< External interrupt line 28 Connected to the internal USART3 wakeup event */
#else
#define EXTI_LINE_28 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
#endif /* EXTI_IMR_MR28 */
#if defined(EXTI_32_63_SUPPORT)
#if defined(EXTI_IMR_MR29)
#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du) /*!< External interrupt line 29 Connected to the Comparator 3 output */
#else
#define EXTI_LINE_29 (EXTI_RESERVED | EXTI_REG1 | 0x1Cu)
#endif /* EXTI_IMR_MR29 */
#if defined(EXTI_IMR_MR30)
#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu) /*!< External interrupt line 30 Connected to the Comparator 4 output */
#else
#define EXTI_LINE_30 (EXTI_RESERVED | EXTI_REG1 | 0x1Eu)
#endif /* EXTI_IMR_MR30 */
#if defined(EXTI_IMR_MR31)
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu) /*!< External interrupt line 31 Connected to the Comparator 5 output */
#else
#define EXTI_LINE_31 (EXTI_RESERVED | EXTI_REG1 | 0x1Fu)
#endif /* EXTI_IMR_MR31 */
#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u) /*!< External interrupt line 32 Connected to the Comparator 6 output */
#if defined(EXTI_IMR2_MR33)
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u) /*!< External interrupt line 33 Connected to the Comparator 7 output */
#else
#define EXTI_LINE_33 (EXTI_RESERVED | EXTI_REG2 | 0x01u)
#endif /* EXTI_IMR2_MR33 */
#if defined(EXTI_IMR2_MR34)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u) /*!< External interrupt line 34 Connected to the USART4 output */
#else
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u)
#endif /* EXTI_IMR2_MR34 */
#if defined(EXTI_IMR2_MR35)
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u) /*!< External interrupt line 35 Connected to the USART5 output */
#else
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u)
#endif /* EXTI_IMR2_MR35 */
#endif /* EXTI_32_63_SUPPORT */
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000u
#define EXTI_MODE_INTERRUPT 0x00000001u
#define EXTI_MODE_EVENT 0x00000002u
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#if defined(GPIOE)
#define EXTI_GPIOE 0x00000004u
#endif /* GPIOE */
#define EXTI_GPIOF 0x00000005u
#if defined(GPIOG)
#define EXTI_GPIOG 0x00000006u
#endif /* GPIOG */
#if defined(GPIOH)
#define EXTI_GPIOH 0x00000007u
#endif /* GPIOH */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16u
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#if defined(EXTI_32_63_SUPPORT)
#define EXTI_LINE_NB 36uL
#else
#define EXTI_LINE_NB 29uL
#endif /* EXTI_32_63_SUPPORT */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
#if defined(GPIOH)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#elif defined(GPIOE)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOF))
#endif /* GPIOE */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

381
Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_flash.h
* @author MCD Application Team
* @brief Header file of Flash HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_FLASH_H
#define __STM32F3xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */
/**
* @}
*/
/** @addtogroup FLASH_Private_Macros
* @{
*/
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))
#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
((__LATENCY__) == FLASH_LATENCY_1) || \
((__LATENCY__) == FLASH_LATENCY_2))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Procedure structure definition
*/
typedef enum
{
FLASH_PROC_NONE = 0U,
FLASH_PROC_PAGEERASE = 1U,
FLASH_PROC_MASSERASE = 2U,
FLASH_PROC_PROGRAMHALFWORD = 3U,
FLASH_PROC_PROGRAMWORD = 4U,
FLASH_PROC_PROGRAMDOUBLEWORD = 5U
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */
__IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */
__IO uint64_t Data; /*!< Internal variable to save data to be programmed */
HAL_LockTypeDef Lock; /*!< FLASH locking object */
__IO uint32_t ErrorCode; /*!< FLASH error code
This parameter can be a value of @ref FLASH_Error_Codes */
} FLASH_ProcessTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_Error_Codes FLASH Error Codes
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */
#define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */
#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!<Program a half-word (16-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!<Program a word (32-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_DOUBLEWORD (0x03U) /*!<Program a double word (64-bit) at a specified address*/
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 (0x00000000U) /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
/**
* @}
*/
/** @defgroup FLASH_Flag_definition FLASH Flag definition
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */
/**
* @}
*/
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error Interrupt source */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @brief macros to control FLASH features
* @{
*/
/** @defgroup FLASH_Half_Cycle FLASH Half Cycle
* @brief macros to handle FLASH half cycle
* @{
*/
/**
* @brief Enable the FLASH half cycle access.
* @retval None
*/
#define __HAL_FLASH_HALF_CYCLE_ACCESS_ENABLE() (FLASH->ACR |= FLASH_ACR_HLFCYA)
/**
* @brief Disable the FLASH half cycle access.
* @retval None
*/
#define __HAL_FLASH_HALF_CYCLE_ACCESS_DISABLE() (FLASH->ACR &= (~FLASH_ACR_HLFCYA))
/**
* @}
*/
/** @defgroup FLASH_EM_Latency FLASH Latency
* @brief macros to handle FLASH Latency
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__ FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
* @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
* @retval None
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (FLASH->ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* This parameter can be one of the following values:
* @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle
* @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle
* @arg @ref FLASH_LATENCY_2 FLASH Two Latency cycles
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @}
*/
/** @defgroup FLASH_Prefetch FLASH Prefetch
* @brief macros to handle FLASH Prefetch buffer
* @{
*/
/**
* @brief Enable the FLASH prefetch buffer.
* @retval None
*/
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE)
/**
* @brief Disable the FLASH prefetch buffer.
* @retval None
*/
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE))
/**
* @}
*/
/** @defgroup FLASH_Interrupt FLASH Interrupts
* @brief macros to handle FLASH interrupts
* @{
*/
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__))
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
* @arg @ref FLASH_IT_ERR Error Interrupt
* @retval none
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__))
/**
* @brief Get the specified FLASH flag status.
* @param __FLAG__ specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg @ref FLASH_FLAG_BSY FLASH Busy flag
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
* @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag
* @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__))
/**
* @}
*/
/**
* @}
*/
/* Include FLASH HAL Extended module */
#include "stm32f3xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler function */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
uint32_t HAL_FLASH_GetError(void);
/**
* @}
*/
/**
* @}
*/
/* Private function -------------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_flash_ex.h Normal file
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@@ -0,0 +1,475 @@
/**
******************************************************************************
* @file stm32f3xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of Flash HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_FLASH_EX_H
#define __STM32F3xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/** @addtogroup FLASHEx_Private_Constants
* @{
*/
#define FLASH_SIZE_DATA_REGISTER (0x1FFFF7CCU)
/**
* @}
*/
/** @addtogroup FLASHEx_Private_Macros
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA))
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1))/*||\
((LEVEL) == OB_RDP_LEVEL_2))*/
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
#define IS_OB_SDACD_VDD_MONITOR(VDD_MONITOR) (((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_SET) || \
((VDD_MONITOR) == OB_SDACD_VDD_MONITOR_RESET))
#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
((ADDRESS) <= 0x0803FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= 0x0807FFFFU))
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
((ADDRESS) <= 0x0800FFFFU) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
((ADDRESS) <= 0x08007FFFU) : ((ADDRESS) <= 0x08003FFFU))))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0803FFFFU) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0801FFFFU) : \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU)))
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0807FFFFU)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x0800FFFFU) : \
(((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08007FFFU) : \
((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1U <= 0x08003FFFU)))
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< TypeErase: Mass erase or page erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t PageAddress; /*!< PageAdress: Initial FLASH page address to erase when mass erase is disabled
This parameter must be a number between Min_Data = FLASH_BASE and Max_Data = FLASH_BANK1_END */
uint32_t NbPages; /*!< NbPages: Number of pagess to be erased.
This parameter must be a value between Min_Data = 1 and Max_Data = (max number of pages - value of initial page)*/
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH Options bytes program structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< OptionType: Option byte to be configured.
This parameter can be a value of @ref FLASHEx_OB_Type */
uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_OB_WRP_State */
uint32_t WRPPage; /*!< WRPPage: specifies the page(s) to be write protected
This parameter can be a value of @ref FLASHEx_OB_Write_Protection */
uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level..
This parameter can be a value of @ref FLASHEx_OB_Read_Protection */
uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte:
IWDG / STOP / STDBY / BOOT1 / VDDA_ANALOG / SRAM_PARITY / SDADC12_VDD_MONITOR
This parameter can be a combination of @ref FLASHEx_OB_IWatchdog, @ref FLASHEx_OB_nRST_STOP,
@ref FLASHEx_OB_nRST_STDBY, @ref FLASHEx_OB_BOOT1, @ref FLASHEx_OB_VDDA_Analog_Monitoring,
@ref FLASHEx_OB_RAM_Parity_Check_Enable.
@if STM32F373xC
And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
@endif
@if STM32F378xx
And @ref FLASHEx_OB_SDADC12_VDD_MONITOR (only for STM32F373xC & STM32F378xx devices)
@endif
*/
uint32_t DATAAddress; /*!< DATAAddress: Address of the option byte DATA to be programmed
This parameter can be a value of @ref FLASHEx_OB_Data_Address */
uint8_t DATAData; /*!< DATAData: Data to be stored in the option byte DATA
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
} FLASH_OBProgramInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
* @{
*/
/** @defgroup FLASHEx_Page_Size FLASHEx Page Size
* @{
*/
#define FLASH_PAGE_SIZE 0x800
/**
* @}
*/
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_PAGES (0x00U) /*!<Pages erase only*/
#define FLASH_TYPEERASE_MASSERASE (0x01U) /*!<Flash mass erase activation*/
/**
* @}
*/
/** @defgroup FLASHEx_OptionByte_Constants Option Byte Constants
* @{
*/
/** @defgroup FLASHEx_OB_Type Option Bytes Type
* @{
*/
#define OPTIONBYTE_WRP (0x01U) /*!<WRP option byte configuration*/
#define OPTIONBYTE_RDP (0x02U) /*!<RDP option byte configuration*/
#define OPTIONBYTE_USER (0x04U) /*!<USER option byte configuration*/
#define OPTIONBYTE_DATA (0x08U) /*!<DATA option byte configuration*/
/**
* @}
*/
/** @defgroup FLASHEx_OB_WRP_State Option Byte WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE (0x00U) /*!<Disable the write protection of the desired pages*/
#define OB_WRPSTATE_ENABLE (0x01U) /*!<Enable the write protection of the desired pagess*/
/**
* @}
*/
/** @defgroup FLASHEx_OB_Write_Protection FLASHEx OB Write Protection
* @{
*/
#define OB_WRP_PAGES0TO1 (0x00000001U) /* Write protection of page 0 to 1 */
#define OB_WRP_PAGES2TO3 (0x00000002U) /* Write protection of page 2 to 3 */
#define OB_WRP_PAGES4TO5 (0x00000004U) /* Write protection of page 4 to 5 */
#define OB_WRP_PAGES6TO7 (0x00000008U) /* Write protection of page 6 to 7 */
#define OB_WRP_PAGES8TO9 (0x00000010U) /* Write protection of page 8 to 9 */
#define OB_WRP_PAGES10TO11 (0x00000020U) /* Write protection of page 10 to 11 */
#define OB_WRP_PAGES12TO13 (0x00000040U) /* Write protection of page 12 to 13 */
#define OB_WRP_PAGES14TO15 (0x00000080U) /* Write protection of page 14 to 15 */
#define OB_WRP_PAGES16TO17 (0x00000100U) /* Write protection of page 16 to 17 */
#define OB_WRP_PAGES18TO19 (0x00000200U) /* Write protection of page 18 to 19 */
#define OB_WRP_PAGES20TO21 (0x00000400U) /* Write protection of page 20 to 21 */
#define OB_WRP_PAGES22TO23 (0x00000800U) /* Write protection of page 22 to 23 */
#define OB_WRP_PAGES24TO25 (0x00001000U) /* Write protection of page 24 to 25 */
#define OB_WRP_PAGES26TO27 (0x00002000U) /* Write protection of page 26 to 27 */
#define OB_WRP_PAGES28TO29 (0x00004000U) /* Write protection of page 28 to 29 */
#define OB_WRP_PAGES30TO31 (0x00008000U) /* Write protection of page 30 to 31 */
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
#define OB_WRP_PAGES62TO127 (0x80000000U) /* Write protection of page 62 to 127 */
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
#define OB_WRP_PAGES32TO33 (0x00010000U) /* Write protection of page 32 to 33 */
#define OB_WRP_PAGES34TO35 (0x00020000U) /* Write protection of page 34 to 35 */
#define OB_WRP_PAGES36TO37 (0x00040000U) /* Write protection of page 36 to 37 */
#define OB_WRP_PAGES38TO39 (0x00080000U) /* Write protection of page 38 to 39 */
#define OB_WRP_PAGES40TO41 (0x00100000U) /* Write protection of page 40 to 41 */
#define OB_WRP_PAGES42TO43 (0x00200000U) /* Write protection of page 42 to 43 */
#define OB_WRP_PAGES44TO45 (0x00400000U) /* Write protection of page 44 to 45 */
#define OB_WRP_PAGES46TO47 (0x00800000U) /* Write protection of page 46 to 47 */
#define OB_WRP_PAGES48TO49 (0x01000000U) /* Write protection of page 48 to 49 */
#define OB_WRP_PAGES50TO51 (0x02000000U) /* Write protection of page 50 to 51 */
#define OB_WRP_PAGES52TO53 (0x04000000U) /* Write protection of page 52 to 53 */
#define OB_WRP_PAGES54TO55 (0x08000000U) /* Write protection of page 54 to 55 */
#define OB_WRP_PAGES56TO57 (0x10000000U) /* Write protection of page 56 to 57 */
#define OB_WRP_PAGES58TO59 (0x20000000U) /* Write protection of page 58 to 59 */
#define OB_WRP_PAGES60TO61 (0x40000000U) /* Write protection of page 60 to 61 */
#define OB_WRP_PAGES62TO255 (0x80000000U) /* Write protection of page 62 to 255 */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
#define OB_WRP_PAGES0TO15MASK (0x000000FFU)
#define OB_WRP_PAGES16TO31MASK (0x0000FF00U)
#if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define OB_WRP_PAGES48TO127MASK (0xFF000000U)
#endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE)
#define OB_WRP_PAGES32TO47MASK (0x00FF0000U)
#define OB_WRP_PAGES48TO255MASK (0xFF000000U)
#endif /* STM32F302xE || STM32F303xE */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) \
|| defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) \
|| defined(STM32F373xC) || defined(STM32F378xx)
#define OB_WRP_ALLPAGES (0xFFFFFFFFU) /*!< Write protection of all pages */
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
/* STM32F302xC || STM32F303xC || STM32F358xx || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) \
|| defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define OB_WRP_ALLPAGES (0x0000FFFFU) /*!< Write protection of all pages */
#endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
/* STM32F303x8 || STM32F334x8 || STM32F328xx */
/**
* @}
*/
/** @defgroup FLASHEx_OB_Read_Protection Option Byte Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0U */
/**
* @}
*/
/** @defgroup FLASHEx_OB_IWatchdog Option Byte IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint8_t)0x01U) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware IWDG selected */
/**
* @}
*/
/** @defgroup FLASHEx_OB_nRST_STOP Option Byte nRST STOP
* @{
*/
#define OB_STOP_NO_RST ((uint8_t)0x02U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
/** @defgroup FLASHEx_OB_nRST_STDBY Option Byte nRST STDBY
* @{
*/
#define OB_STDBY_NO_RST ((uint8_t)0x04U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
/** @defgroup FLASHEx_OB_BOOT1 Option Byte BOOT1
* @{
*/
#define OB_BOOT1_RESET ((uint8_t)0x00U) /*!< BOOT1 Reset */
#define OB_BOOT1_SET ((uint8_t)0x10U) /*!< BOOT1 Set */
/**
* @}
*/
/** @defgroup FLASHEx_OB_VDDA_Analog_Monitoring Option Byte VDDA Analog Monitoring
* @{
*/
#define OB_VDDA_ANALOG_ON ((uint8_t)0x20U) /*!< Analog monitoring on VDDA Power source ON */
#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00U) /*!< Analog monitoring on VDDA Power source OFF */
/**
* @}
*/
/** @defgroup FLASHEx_OB_RAM_Parity_Check_Enable Option Byte SRAM Parity Check Enable
* @{
*/
#define OB_SRAM_PARITY_SET ((uint8_t)0x00U) /*!< SRAM parity check enable set */
#define OB_SRAM_PARITY_RESET ((uint8_t)0x40U) /*!< SRAM parity check enable reset */
/**
* @}
*/
#if defined(FLASH_OBR_SDADC12_VDD_MONITOR)
/** @defgroup FLASHEx_OB_SDADC12_VDD_MONITOR OB SDADC12 VDD MONITOR
* @{
*/
#define OB_SDACD_VDD_MONITOR_RESET ((uint8_t)0x00U) /*!< SDADC VDD Monitor reset */
#define OB_SDACD_VDD_MONITOR_SET ((uint8_t)0x80U) /*!< SDADC VDD Monitor set */
/**
* @}
*/
#endif /* FLASH_OBR_SDADC12_VDD_MONITOR */
/** @defgroup FLASHEx_OB_Data_Address Option Byte Data Address
* @{
*/
#define OB_DATA_ADDRESS_DATA0 (0x1FFFF804U)
#define OB_DATA_ADDRESS_DATA1 (0x1FFFF806U)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
/**
* @}
*/
/** @addtogroup FLASHEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_FLASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_GPIO_H
#define __STM32F3xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
}GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
}GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0x00WX00YZ
* - W : EXTI trigger detection on 3 bits
* - X : EXTI mode (IT or Event) on 2 bits
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 2 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 4 MHz to 10 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH (0x00000003U) /*!< range 10 MHz to 50 MHz, please refer to the product datasheet */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0u
#define GPIO_MODE (0x3uL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0uL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1uL << GPIO_MODE_Pos)
#define MODE_AF (0x2uL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3uL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4u
#define OUTPUT_TYPE (0x1uL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0uL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1uL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16u
#define EXTI_MODE (0x3uL << EXTI_MODE_Pos)
#define EXTI_IT (0x1uL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2uL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20u
#define TRIGGER_MODE (0x7uL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1uL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2uL << TRIGGER_MODE_Pos)
#define TRIGGER_LEVEL (0x4uL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @addtogroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32f3xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_I2C_H
#define STM32F3xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32f3xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
(~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32f3xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_i2c_ex.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_I2C_EX_H
#define STM32F3xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C2_FMP)
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#else
#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */
#endif /* SYSCFG_CFGR1_I2C2_FMP */
#if defined(SYSCFG_CFGR1_I2C3_FMP)
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#else
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
#endif /* SYSCFG_CFGR1_I2C3_FMP */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32f3xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_i2s.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_I2S_H
#define STM32F3xx_HAL_I2S_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
#if defined(SPI_I2S_SUPPORT)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup I2S
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t ClockSource; /*!< Specifies the I2S Clock Source.
This parameter can be a value of @ref I2S_Clock_Source */
uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode.
This parameter can be a value of @ref I2S_FullDuplex_Mode */
} I2S_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
} HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
typedef struct __I2S_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
void (*IrqHandlerISR)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
} I2S_HandleTypeDef;
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL I2S Callback ID enumeration definition
*/
typedef enum
{
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
} HAL_I2S_CallbackIDTypeDef;
/**
* @brief HAL I2S Callback pointer definition
*/
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
/**
* @}
*/
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
/**
* @}
*/
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
/**
* @}
*/
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K (192000U)
#define I2S_AUDIOFREQ_96K (96000U)
#define I2S_AUDIOFREQ_48K (48000U)
#define I2S_AUDIOFREQ_44K (44100U)
#define I2S_AUDIOFREQ_32K (32000U)
#define I2S_AUDIOFREQ_22K (22050U)
#define I2S_AUDIOFREQ_16K (16000U)
#define I2S_AUDIOFREQ_11K (11025U)
#define I2S_AUDIOFREQ_8K (8000U)
#define I2S_AUDIOFREQ_DEFAULT (2U)
/**
* @}
*/
/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode
* @{
*/
#define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U)
#define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U)
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW (0x00000000U)
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_IT_TXE SPI_CR2_TXEIE
#define I2S_IT_RXNE SPI_CR2_RXNEIE
#define I2S_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXE
#define I2S_FLAG_RXNE SPI_SR_RXNE
#define I2S_FLAG_UDR SPI_SR_UDR
#define I2S_FLAG_OVR SPI_SR_OVR
#define I2S_FLAG_FRE SPI_SR_FRE
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
#define I2S_FLAG_MASK (SPI_SR_RXNE\
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
/** @defgroup I2S_Clock_Source I2S Clock Source Definition
* @{
*/
#define I2S_CLOCK_EXTERNAL (0x00000001U)
#define I2S_CLOCK_SYSCLK (0x00000002U)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
/** @brief Disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
__IO uint32_t tmpreg_udr = 0x00U;\
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg_udr); \
}while(0U)
/** @brief Flush the I2S DR Register.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
__IO uint32_t tmpreg_dr = 0x00U;\
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
*/
/* Include I2S Extension module */
#include "stm32f3xx_hal_i2s_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
*/
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun error flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_CHSIDE: Channel side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
* This parameter can be a value of @ref I2S_Mode
* @retval None
*/
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
((__STANDARD__) == I2S_STANDARD_LSB) || \
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
((__FORMAT__) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \
((MODE) == I2S_FULLDUPLEXMODE_ENABLE))
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the I2S serial clock steady state.
* This parameter can be a value of @ref I2S_Clock_Polarity
* @retval None
*/
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
((__CPOL__) == I2S_CPOL_HIGH))
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
((CLOCK) == I2S_CLOCK_SYSCLK))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SPI_I2S_SUPPORT */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_i2s_ex.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_I2S_EX_H
#define STM32F3xx_HAL_I2S_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
/** @addtogroup I2SEx I2SEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
* @{
*/
#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
/** @brief Enable or disable the specified I2SExt peripheral.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
/** @brief Enable or disable the specified I2SExt interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2SExt flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2SExt OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg_udr = 0x00U; \
tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
UNUSED(tmpreg_udr); \
}while(0U)
/** @brief Flush the I2S and I2SExt DR Registers.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_FLUSH_RX_DR(__HANDLE__) do{ \
__IO uint32_t tmpreg_dr = 0x00U; \
tmpreg_dr = I2SxEXT((__HANDLE__)->Instance)->DR; \
tmpreg_dr = ((__HANDLE__)->Instance->DR); \
UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
* @{
*/
/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
* @{
*/
/* Extended features functions *************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
uint16_t Size);
/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_I2S_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_irda.h
* @author MCD Application Team
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_IRDA_H
#define STM32F3xx_HAL_IRDA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup IRDA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
*/
/**
* @brief IRDA Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
The baud rate register is computed using the following formula:
Baud Rate Register = ((usart_ker_clk) / ((hirda->Init.BaudRate)))
where usart_ker_clk is the IRDA input clock */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDAEx_Word_Length */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref IRDA_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
to achieve low-power frequency.
@note Prescaler value 0 is forbidden */
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
This parameter can be a value of @ref IRDA_Low_Power */
} IRDA_InitTypeDef;
/**
* @brief HAL IRDA State definition
* @note HAL IRDA State value is a combination of 2 different substates:
* gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef uint32_t HAL_IRDA_StateTypeDef;
/**
* @brief IRDA clock sources definition
*/
typedef enum
{
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
} IRDA_ClockSourceTypeDef;
/**
* @brief IRDA handle Structure definition
*/
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
typedef struct __IRDA_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
{
USART_TypeDef *Instance; /*!< USART registers base address */
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
uint16_t Mask; /*!< USART RX RDR register mask */
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO uint32_t ErrorCode; /*!< IRDA Error code */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
} IRDA_HandleTypeDef;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief HAL IRDA Callback ID enumeration definition
*/
typedef enum
{
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
} HAL_IRDA_CallbackIDTypeDef;
/**
* @brief HAL IRDA Callback pointer definition
*/
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
* @{
*/
/** @defgroup IRDA_State_Definition IRDA State Code Definition
* @{
*/
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
Value is allowed for gState only */
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between
gState and RxState values */
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
Value is allowed for gState only */
/**
* @}
*/
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
* @{
*/
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
* @{
*/
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
/**
* @}
*/
/** @defgroup IRDA_State IRDA State
* @{
*/
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
/**
* @}
*/
/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
/**
* @}
*/
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
* @{
*/
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
/**
* @}
*/
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
/**
* @}
*/
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
/**
* @}
*/
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
* @{
*/
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
/** @defgroup IRDA_Flags IRDA Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
#define IRDA_FLAG_TXE USART_ISR_TXE /*!< IRDA transmit data register empty */
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
#define IRDA_FLAG_RXNE USART_ISR_RXNE /*!< IRDA read data register not empty */
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
/**
* @}
*/
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
/* Elements values convention: 000000000XXYYYYYb
- YYYYY : Interrupt source position in the XX register (5bits)
- XX : Interrupt source register (2bits)
- 01: CR1 register
- 10: CR2 register
- 11: CR3 register */
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
/* Elements values convention: 0000ZZZZ00000000b
- ZZZZ : Flag position in the ISR register(4bits) */
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
/**
* @}
*/
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
* @{
*/
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
/**
* @}
*/
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
* @{
*/
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
#define IRDA_CR_POS 5U /*!< IRDA control register position */
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
* @{
*/
/** @brief Reset IRDA handle state.
* @param __HANDLE__ IRDA handle.
* @retval None
*/
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
/** @brief Flush the IRDA DR register.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref IRDA_CLEAR_PEF
* @arg @ref IRDA_CLEAR_FEF
* @arg @ref IRDA_CLEAR_NEF
* @arg @ref IRDA_CLEAR_OREF
* @arg @ref IRDA_CLEAR_TCF
* @arg @ref IRDA_CLEAR_IDLEF
* @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the IRDA PE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
/** @brief Clear the IRDA FE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
/** @brief Clear the IRDA NE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
/** @brief Clear the IRDA ORE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
/** @brief Clear the IRDA IDLE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref IRDA_FLAG_BUSY Busy flag
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
* @arg @ref IRDA_FLAG_NE Noise Error flag
* @arg @ref IRDA_FLAG_FE Framing Error flag
* @arg @ref IRDA_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
((__HANDLE__)->Instance->CR1 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
((__HANDLE__)->Instance->CR2 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
((__HANDLE__)->Instance->CR3 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
* @arg @ref IRDA_IT_NE Noise Error interrupt
* @arg @ref IRDA_IT_FE Framing Error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific IRDA request flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the IRDA one bit sample method.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the IRDA one bit sample method.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup IRDA_Private_Macros
* @{
*/
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
* @retval True or False
*/
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
* @retval True or False
*/
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
/** @brief Ensure that IRDA frame parity is valid.
* @param __PARITY__ IRDA frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
((__PARITY__) == IRDA_PARITY_EVEN) || \
((__PARITY__) == IRDA_PARITY_ODD))
/** @brief Ensure that IRDA communication mode is valid.
* @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that IRDA power mode is valid.
* @param __MODE__ IRDA power mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
((__MODE__) == IRDA_POWERMODE_NORMAL))
/** @brief Ensure that IRDA state is valid.
* @param __STATE__ IRDA state mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
((__STATE__) == IRDA_STATE_ENABLE))
/** @brief Ensure that IRDA associated UART/USART mode is valid.
* @param __MODE__ IRDA associated UART/USART mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
((__MODE__) == IRDA_MODE_ENABLE))
/** @brief Ensure that IRDA sampling rate is valid.
* @param __ONEBIT__ IRDA sampling rate.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
*/
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
/** @brief Ensure that IRDA DMA TX mode is valid.
* @param __DMATX__ IRDA DMA TX mode.
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
*/
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
((__DMATX__) == IRDA_DMA_TX_ENABLE))
/** @brief Ensure that IRDA DMA RX mode is valid.
* @param __DMARX__ IRDA DMA RX mode.
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
*/
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
((__DMARX__) == IRDA_DMA_RX_ENABLE))
/** @brief Ensure that IRDA request is valid.
* @param __PARAM__ IRDA request.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
/* Include IRDA HAL Extended module */
#include "stm32f3xx_hal_irda_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
* @{
*/
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_IRDA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_irda_ex.h
* @author MCD Application Team
* @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_IRDA_EX_H
#define STM32F3xx_HAL_IRDA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @defgroup IRDAEx IRDAEx
* @brief IRDA Extended HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
* @{
*/
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
* @{
*/
#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
#elif defined(USART_CR1_M)
#define IRDA_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long frame */
#endif
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
* @{
*/
/** @brief Report the IRDA clock source.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || STM32F302xC || STM32F303xC || STM32F358xx */
/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
#elif defined(USART_CR1_M)
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
} while(0U)
#endif
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#if defined(USART_CR1_M1)&&defined(USART_CR1_M0)
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
#elif defined(USART_CR1_M)
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
#endif
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_IRDA_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_iwdg.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_IWDG_H
#define STM32F3xx_HAL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @defgroup IWDG IWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{
*/
/**
* @brief IWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
} IWDG_InitTypeDef;
/**
* @brief IWDG Handle Structure definition
*/
typedef struct
{
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
} IWDG_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
/** @defgroup IWDG_Window_option IWDG Window option
* @{
*/
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{
*/
/**
* @brief Enable the IWDG peripheral.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{
*/
/* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{
*/
/**
* @brief IWDG Key Register BitMask
*/
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Check IWDG prescaler value.
* @param __PRESCALER__ IWDG prescaler value
* @retval None
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/**
* @brief Check IWDG reload value.
* @param __RELOAD__ IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @brief Check IWDG window value.
* @param __WINDOW__ IWDG window value
* @retval None
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nand.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_nand.h
* @author MCD Application Team
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_NAND_H
#define STM32F3xx_HAL_NAND_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FMC_BANK3)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup NAND
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Types NAND Exported Types
* @{
*/
/**
* @brief HAL NAND State structures definition
*/
typedef enum
{
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
} HAL_NAND_StateTypeDef;
/**
* @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
/*<! NAND memory electronic signature maker and device IDs */
uint8_t Maker_Id;
uint8_t Device_Id;
uint8_t Third_Id;
uint8_t Fourth_Id;
} NAND_IDTypeDef;
/**
* @brief NAND Memory address Structure definition
*/
typedef struct
{
uint16_t Page; /*!< NAND memory Page address */
uint16_t Plane; /*!< NAND memory Zone address */
uint16_t Block; /*!< NAND memory Block address */
} NAND_AddressTypeDef;
/**
* @brief NAND Memory info Structure definition
*/
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
for 8 bits addressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
for 8 bits addressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
uint32_t PlaneNbr; /*!< NAND memory number of planes */
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
* @brief NAND handle Structure definition
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
typedef struct __NAND_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
{
FMC_NAND_TypeDef *Instance; /*!< Register base address */
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NAND locking object */
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief HAL NAND Callback ID enumeration definition
*/
typedef enum
{
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
* @retval None
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_NAND_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* NAND Control functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE1 0x70000000UL
#define NAND_DEVICE2 0x80000000UL
#define NAND_WRITE_TIMEOUT 0x01000000UL
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS 0x00000100UL
#define NAND_INVALID_ADDRESS 0x00000200UL
#define NAND_TIMEOUT_ERROR 0x00000400UL
#define NAND_BUSY 0x00000000UL
#define NAND_ERROR 0x00000001UL
#define NAND_READY 0x00000040UL
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NAND_Private_Macros NAND Private Macros
* @{
*/
/**
* @brief NAND memory address computation.
* @param __ADDRESS__ NAND memory address.
* @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + \
(((__ADDRESS__)->Plane) * \
((__HANDLE__)->Config.PlaneSize))) * \
((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
* @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
* @brief NAND memory address cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND address cycling value.
*/
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
/**
* @brief NAND memory Columns cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND Column address cycling value.
*/
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK3 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_NAND_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_nor.h
* @author MCD Application Team
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_NOR_H
#define STM32F3xx_HAL_NOR_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup NOR
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup NOR_Exported_Types NOR Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
} HAL_NOR_StateTypeDef;
/**
* @brief FMC NOR Status typedef
*/
typedef enum
{
HAL_NOR_STATUS_SUCCESS = 0U,
HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT
} HAL_NOR_StatusTypeDef;
/**
* @brief FMC NOR ID typedef
*/
typedef struct
{
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
uint16_t Device_Code1;
uint16_t Device_Code2;
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
These codes can be accessed by performing read operations with specific
control signals and addresses set.They can also be accessed by issuing
an Auto Select command */
} NOR_IDTypeDef;
/**
* @brief FMC NOR CFI typedef
*/
typedef struct
{
/*!< Defines the information stored in the memory's Common flash interface
which contains a description of various electrical and timing parameters,
density information and functions supported by the memory */
uint16_t CFI_1;
uint16_t CFI_2;
uint16_t CFI_3;
uint16_t CFI_4;
} NOR_CFITypeDef;
/**
* @brief NOR handle Structure definition
*/
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
typedef struct __NOR_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NOR locking object */
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
uint32_t CommandSet; /*!< NOR algorithm command set and control */
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */
void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
} NOR_HandleTypeDef;
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/**
* @brief HAL NOR Callback ID enumeration definition
*/
typedef enum
{
HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */
HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */
} HAL_NOR_CallbackIDTypeDef;
/**
* @brief HAL NOR Callback pointer definition
*/
typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NOR_Exported_Macros NOR Exported Macros
* @{
*/
/** @brief Reset NOR handle state
* @param __HANDLE__ specifies the NOR handle.
* @retval None
*/
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_NOR_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
* @{
*/
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
/* NOR callback registering/unregistering */
HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
pNOR_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
* @{
*/
/* NOR Control functions *****************************************************/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
* @{
*/
/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NOR_Private_Constants NOR Private Constants
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x0061)
#define CFI2_ADDRESS ((uint16_t)0x0062)
#define CFI3_ADDRESS ((uint16_t)0x0063)
#define CFI4_ADDRESS ((uint16_t)0x0064)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFF)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x00)
#define NOR_MEMORY_16B ((uint8_t)0x01)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 (0x60000000U)
#define NOR_MEMORY_ADRESS2 (0x64000000U)
#define NOR_MEMORY_ADRESS3 (0x68000000U)
#define NOR_MEMORY_ADRESS4 (0x6C000000U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NOR_Private_Macros NOR Private Macros
* @{
*/
/**
* @brief NOR memory address shifting.
* @param __NOR_ADDRESS NOR base address
* @param __NOR_MEMORY_WIDTH_ NOR memory width
* @param __ADDRESS__ NOR memory address
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
/**
* @brief NOR memory write data to specified address.
* @param __ADDRESS__ NOR memory address
* @param __DATA__ Data to write
* @retval None
*/
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
__DSB(); \
} while(0)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_NOR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_opamp.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_hal_opamp.h
* @author MCD Application Team
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_OPAMP_H
#define STM32F3xx_HAL_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup OPAMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
* @{
*/
/**
* @brief OPAMP Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the OPAMP mode
This parameter must be a value of @ref OPAMP_Mode
mode is either Standalone, - Follower or PGA */
uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & Pga modes
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
This parameter must be a value of @ref OPAMP_InvertingInput
InvertingInput is either VM0 or VM1
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
This parameter is Not Applicable */
uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
This parameter must be a value of @ref OPAMP_NonInvertingInput
NonInvertingInput is either VP0, VP1, VP2 or VP3 */
uint32_t TimerControlledMuxmode; /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
This parameter must be a value of @ref OPAMP_TimerControlledMuxmode */
uint32_t InvertingInputSecondary; /*!< Specifies the inverting input (secondary) of the opamp when
TimerControlledMuxmode is enabled
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
This parameter must be a value of @ref OPAMP_InvertingInputSecondary
InvertingInputSecondary is either VM0 or VM1
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
This parameter is Not Applicable */
uint32_t NonInvertingInputSecondary; /*!< Specifies the non inverting input (secondary) of the opamp when
TimerControlledMuxmode is enabled
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
NonInvertingInput is either VP0, VP1, VP2 or VP3 */
uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
i.e. when mode is OPAMP_PGA_MODE
This parameter must be a value of @ref OPAMP_PgaConnect
Either: not connected, connected to VM0, connected to VM1
(VM0 or VM1 are typically used for external filtering) */
uint32_t PgaGain; /*!< Specifies the gain in PGA mode
i.e. when mode is OPAMP_PGA_MODE.
This parameter must be a value of @ref OPAMP_PgaGain (2U, 4U, 8 or 16U ) */
uint32_t UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref OPAMP_UserTrimming
UserTrimming is either factory or user trimming */
uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31U */
} OPAMP_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_OPAMP_STATE_RESET = 0x00000000U, /*!< OPMAP is not yet Initialized */
HAL_OPAMP_STATE_READY = 0x00000001U, /*!< OPAMP is initialized and ready for use */
HAL_OPAMP_STATE_CALIBBUSY = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */
HAL_OPAMP_STATE_BUSY = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005U, /*!< OPAMP is locked
only system reset allows reconfiguring the opamp. */
}HAL_OPAMP_StateTypeDef;
/**
* @brief OPAMP Handle Structure definition to @brief OPAMP Handle Structure definition
*/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
typedef struct __OPAMP_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
{
OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
void (* MspInitCallback) (struct __OPAMP_HandleTypeDef *hopamp);
void (* MspDeInitCallback) (struct __OPAMP_HandleTypeDef *hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
} OPAMP_HandleTypeDef;
/**
* @brief OPAMP_TrimmingValueTypeDef @brief definition
*/
typedef uint32_t OPAMP_TrimmingValueTypeDef;
/**
* @}
*/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL OPAMP Callback ID enumeration definition
*/
typedef enum
{
HAL_OPAMP_MSP_INIT_CB_ID = 0x01U, /*!< OPAMP MspInit Callback ID */
HAL_OPAMP_MSP_DEINIT_CB_ID = 0x02U, /*!< OPAMP MspDeInit Callback ID */
HAL_OPAMP_ALL_CB_ID = 0x03U /*!< OPAMP All ID */
} HAL_OPAMP_CallbackIDTypeDef;
/**
* @brief HAL OPAMP Callback pointer definition
*/
typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
* @{
*/
/** @defgroup OPAMP_CSR_INIT OPAMP CSR init register Mask
* @{
*/
/* Used for Init phase */
#define OPAMP_CSR_UPDATE_PARAMETERS_INIT_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP \
| OPAMP_CSR_USERTRIM | OPAMP_CSR_PGGAIN | OPAMP_CSR_VPSSEL \
| OPAMP_CSR_VMSSEL | OPAMP_CSR_TCMEN | OPAMP_CSR_VPSEL \
| OPAMP_CSR_VMSEL | OPAMP_CSR_FORCEVP)
/**
* @}
*/
/** @defgroup OPAMP_Mode OPAMP Mode
* @{
*/
#define OPAMP_STANDALONE_MODE (0x00000000U) /*!< standalone mode */
#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
((INPUT) == OPAMP_PGA_MODE) || \
((INPUT) == OPAMP_FOLLOWER_MODE))
/**
* @}
*/
/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
* @{
*/
#define OPAMP_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSEL /*!< VP0 (PA1 for OPAMP1, VP0 PA7 for OPAMP2, VP0 PB0 for OPAMP3, VP0 PB13 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, VP3 PD14 for OPAMP2, VP1 PB13 for OPAMP3, VP1 PD11 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< VP2 (PA3 for OPAMP1, VP2 PB0 for OPAMP2, VP2 PA1 for OPAMP3, VP3 PA4 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL_0 /*!< VP3 (PA5 for OPAMP1, VP1 PB14 for OPAMP2, VP3 PA5 for OPAMP3, VP2 PB11 for OPAMP4)
connected to OPAMPx non inverting input */
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_IO3))
/**
* @}
*/
/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
* @{
*/
#define OPAMP_INVERTINGINPUT_IO0 (0x00000000U) /*!< inverting input connected to VM0 */
#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< inverting input connected to VM1 */
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_INVERTINGINPUT_IO1))
/**
* @}
*/
/** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
* @{
*/
#define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000U) /*!< Timer controlled Mux mode disabled */
#define OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE OPAMP_CSR_TCMEN /*!< Timer controlled Mux mode enabled */
#define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) (((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE) || \
((MUXMODE) == OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE))
/**
* @}
*/
/** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
* @{
*/
#define OPAMP_SEC_NONINVERTINGINPUT_IO0 OPAMP_CSR_VPSSEL /*!< VP0 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_SEC_NONINVERTINGINPUT_IO1 (0x00000000U) /*!< VP1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSSEL_1 /*!< VP2 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
connected to OPAMPx non inverting input */
#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSSEL_0 /*!< VP3 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
connected to OPAMPx non inverting input */
#define IS_OPAMP_SEC_NONINVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3))
/**
* @}
*/
/** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
* @{
*/
#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000U) /*!< VM0 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
connected to OPAMPx inverting input */
#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_CSR_VMSSEL /*!< VM1 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
connected to OPAMPx inverting input */
#define IS_OPAMP_SEC_INVERTINGINPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1))
/**
* @}
*/
/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
* @{
*/
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000U) /*!< In PGA mode, the non inverting input is not connected */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the non inverting input is connected to VM0 */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the non inverting input is connected to VM1 */
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1))
/**
* @}
*/
/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
* @{
*/
#define OPAMP_PGA_GAIN_2 (0x00000000U) /*!< PGA gain = 2 */
#define OPAMP_PGA_GAIN_4 OPAMP_CSR_PGGAIN_0 /*!< PGA gain = 4 */
#define OPAMP_PGA_GAIN_8 OPAMP_CSR_PGGAIN_1 /*!< PGA gain = 8 */
#define OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain = 16 */
#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
((GAIN) == OPAMP_PGA_GAIN_4) || \
((GAIN) == OPAMP_PGA_GAIN_8) || \
((GAIN) == OPAMP_PGA_GAIN_16))
/**
* @}
*/
/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
* @{
*/
#define OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< Factory trimming */
#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
((TRIMMING) == OPAMP_TRIMMING_USER))
/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
* @{
*/
#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFU) /*!< Dummy trimming value */
#define OPAMP_FACTORYTRIMMING_N (0x00000000U) /*!< Offset trimming N */
#define OPAMP_FACTORYTRIMMING_P (0x00000001U) /*!< Offset trimming P */
#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
/**
* @}
*/
/** @defgroup OPAMP_TrimmingValue OPAMP Trimming Value
* @{
*/
#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
/**
* @}
*/
/** @defgroup OPAMP_Input OPAMP Input
* @{
*/
#define OPAMP_INPUT_INVERTING (24U) /*!< Inverting input */
#define OPAMP_INPUT_NONINVERTING (19U) /*!< Non inverting input */
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
((INPUT) == OPAMP_INPUT_NONINVERTING))
/**
* @}
*/
/** @defgroup OPAMP_VREF OPAMP VREF
* @{
*/
#define OPAMP_VREF_3VDDA (0x00000000U) /*!< OPMAP Vref = 3.3U% VDDA */
#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10U% VDDA */
#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50U% VDDA */
#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90U% VDDA */
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
((VREF) == OPAMP_VREF_10VDDA) || \
((VREF) == OPAMP_VREF_50VDDA) || \
((VREF) == OPAMP_VREF_90VDDA))
/**
* @}
*/
/** @defgroup OPAMP_Vref2ADCforCalib OPAMP Vref2ADCforCalib
* @{
*/
#define OPAMP_VREF_NOTCONNECTEDTO_ADC (0x00000000U) /*!< VREF not connected to ADC */
#define OPAMP_VREF_CONNECTEDTO_ADC (0x00000001U) /*!< VREF not connected to ADC */
#define IS_OPAMP_ALLOPAMPVREF_CONNECT(CONNECT) (((CONNECT) == OPAMP_VREF_NOTCONNECTEDTO_ADC) || \
((CONNECT) == OPAMP_VREF_CONNECTEDTO_ADC))
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
* @{
*/
/** @brief Reset OPAMP handle state
* @param __HANDLE__ OPAMP handle.
* @retval None
*/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_OPAMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/**
* @}
*/
/* Include OPAMP HAL Extended module */
#include "stm32f3xx_hal_opamp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
* @{
*/
/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp);
void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/* OPAMP callback registering/unregistering */
HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* Peripheral State functions **************************************************/
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_OPAMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_opamp_ex.h
* @author MCD Application Team
* @brief Header file of OPAMP HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_OPAMP_EX_H
#define STM32F3xx_HAL_OPAMP_EX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup OPAMPEx OPAMPEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
* @{
*/
/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
* @{
*/
/* I/O operation functions *****************************************************/
#if defined(STM32F302xE) || \
defined(STM32F302xC)
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
#endif /* STM32F302xE || */
/* STM32F302xC */
#if defined(STM32F303xE) || defined(STM32F398xx) || \
defined(STM32F303xC) || defined(STM32F358xx)
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4);
#endif /* STM32F303xE || STM32F398xx || */
/* STM32F303xC || STM32F358xx */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_OPAMP_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_pccard.h
* @author MCD Application Team
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_PCCARD_H
#define STM32F3xx_HAL_PCCARD_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FMC_BANK4)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup PCCARD
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Types PCCARD Exported Types
* @{
*/
/**
* @brief HAL PCCARD State structures definition
*/
typedef enum
{
HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */
HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */
HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */
HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */
} HAL_PCCARD_StateTypeDef;
typedef enum
{
HAL_PCCARD_STATUS_SUCCESS = 0U,
HAL_PCCARD_STATUS_ONGOING,
HAL_PCCARD_STATUS_ERROR,
HAL_PCCARD_STATUS_TIMEOUT
} HAL_PCCARD_StatusTypeDef;
/**
* @brief FMC_PCCARD handle Structure definition
*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
typedef struct __PCCARD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */
{
FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */
FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */
__IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */
HAL_LockTypeDef Lock; /*!< PCCARD Lock */
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */
void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */
void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */
#endif
} PCCARD_HandleTypeDef;
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/**
* @brief HAL PCCARD Callback ID enumeration definition
*/
typedef enum
{
HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */
HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */
HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */
} HAL_PCCARD_CallbackIDTypeDef;
/**
* @brief HAL PCCARD Callback pointer definition
*/
typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard);
#endif
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PCCARD_Exported_Macros PCCARD Exported Macros
* @{
*/
/** @brief Reset PCCARD handle state
* @param __HANDLE__ specifies the PCCARD handle.
* @retval None
*/
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_PCCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
#endif
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCCARD_Exported_Functions
* @{
*/
/** @addtogroup PCCARD_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming,
FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming);
HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard);
/**
* @}
*/
/** @addtogroup PCCARD_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress,
uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus);
HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard);
void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard);
#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1)
/* PCCARD callback registering/unregistering */
HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId,
pPCCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard,
HAL_PCCARD_CallbackIDTypeDef CallbackId);
#endif
/**
* @}
*/
/** @addtogroup PCCARD_Exported_Functions_Group3
* @{
*/
/* PCCARD State functions *******************************************************/
HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard);
HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard);
HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PCCARD_Private_Constants PCCARD Private Constants
* @{
*/
#define PCCARD_DEVICE_ADDRESS 0x90000000U
#define PCCARD_ATTRIBUTE_SPACE_ADDRESS 0x98000000U /* Attribute space size to @0x9BFF FFFF */
#define PCCARD_COMMON_SPACE_ADDRESS PCCARD_DEVICE_ADDRESS /* Common space size to @0x93FF FFFF */
#define PCCARD_IO_SPACE_ADDRESS 0x9C000000U /* IO space size to @0x9FFF FFFF */
#define PCCARD_IO_SPACE_PRIMARY_ADDR 0x9C0001F0U /* IO space size to @0x9FFF FFFF */
/* Flash-ATA registers description */
#define ATA_DATA ((uint8_t)0x00) /* Data register */
#define ATA_SECTOR_COUNT ((uint8_t)0x02) /* Sector Count register */
#define ATA_SECTOR_NUMBER ((uint8_t)0x03) /* Sector Number register */
#define ATA_CYLINDER_LOW ((uint8_t)0x04) /* Cylinder low register */
#define ATA_CYLINDER_HIGH ((uint8_t)0x05) /* Cylinder high register */
#define ATA_CARD_HEAD ((uint8_t)0x06) /* Card/Head register */
#define ATA_STATUS_CMD ((uint8_t)0x07) /* Status(read)/Command(write) register */
#define ATA_STATUS_CMD_ALTERNATE ((uint8_t)0x0E) /* Alternate Status(read)/Command(write) register */
#define ATA_COMMON_DATA_AREA ((uint16_t)0x0400) /* Start of data area (for Common access only!) */
#define ATA_CARD_CONFIGURATION ((uint16_t)0x0202) /* Card Configuration and Status Register */
/* Flash-ATA commands */
#define ATA_READ_SECTOR_CMD ((uint8_t)0x20)
#define ATA_WRITE_SECTOR_CMD ((uint8_t)0x30)
#define ATA_ERASE_SECTOR_CMD ((uint8_t)0xC0)
#define ATA_IDENTIFY_CMD ((uint8_t)0xEC)
/* PC Card/Compact Flash status */
#define PCCARD_TIMEOUT_ERROR ((uint8_t)0x60)
#define PCCARD_BUSY ((uint8_t)0x80)
#define PCCARD_PROGR ((uint8_t)0x01)
#define PCCARD_READY ((uint8_t)0x40)
#define PCCARD_SECTOR_SIZE 255U /* In half words */
/**
* @}
*/
/* Compact Flash redefinition */
#define HAL_CF_Init HAL_PCCARD_Init
#define HAL_CF_DeInit HAL_PCCARD_DeInit
#define HAL_CF_MspInit HAL_PCCARD_MspInit
#define HAL_CF_MspDeInit HAL_PCCARD_MspDeInit
#define HAL_CF_Read_ID HAL_PCCARD_Read_ID
#define HAL_CF_Write_Sector HAL_PCCARD_Write_Sector
#define HAL_CF_Read_Sector HAL_PCCARD_Read_Sector
#define HAL_CF_Erase_Sector HAL_PCCARD_Erase_Sector
#define HAL_CF_Reset HAL_PCCARD_Reset
#define HAL_CF_IRQHandler HAL_PCCARD_IRQHandler
#define HAL_CF_ITCallback HAL_PCCARD_ITCallback
#define HAL_CF_GetState HAL_PCCARD_GetState
#define HAL_CF_GetStatus HAL_PCCARD_GetStatus
#define HAL_CF_ReadStatus HAL_PCCARD_ReadStatus
#define HAL_CF_STATUS_SUCCESS HAL_PCCARD_STATUS_SUCCESS
#define HAL_CF_STATUS_ONGOING HAL_PCCARD_STATUS_ONGOING
#define HAL_CF_STATUS_ERROR HAL_PCCARD_STATUS_ERROR
#define HAL_CF_STATUS_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
#define HAL_CF_StatusTypeDef HAL_PCCARD_StatusTypeDef
#define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS
#define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS
#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS
#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS
#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR
#define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR
#define CF_BUSY PCCARD_BUSY
#define CF_PROGR PCCARD_PROGR
#define CF_READY PCCARD_READY
#define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE
/* Private macros ------------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK4 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_PCCARD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

995
Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd.h Normal file
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@@ -0,0 +1,995 @@
/**
******************************************************************************
* @file stm32f3xx_hal_pcd.h
* @author MCD Application Team
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_PCD_H
#define STM32F3xx_HAL_PCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_usb.h"
#if defined (USB)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup PCD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PCD_Exported_Types PCD Exported Types
* @{
*/
/**
* @brief PCD State structure definition
*/
typedef enum
{
HAL_PCD_STATE_RESET = 0x00,
HAL_PCD_STATE_READY = 0x01,
HAL_PCD_STATE_ERROR = 0x02,
HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
/* Device LPM suspend state */
typedef enum
{
LPM_L0 = 0x00, /* on */
LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03, /* off */
} PCD_LPM_StateTypeDef;
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
} PCD_LPM_MsgTypeDef;
typedef enum
{
PCD_BCD_ERROR = 0xFF,
PCD_BCD_CONTACT_DETECTION = 0xFE,
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
} PCD_BCD_MsgTypeDef;
typedef USB_TypeDef PCD_TypeDef;
typedef USB_CfgTypeDef PCD_InitTypeDef;
typedef USB_EPTypeDef PCD_EPTypeDef;
/**
* @brief PCD Handle Structure definition
*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
typedef struct __PCD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
void *pData; /*!< Pointer to upper stack Handler */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
} PCD_HandleTypeDef;
/**
* @}
*/
/* Include PCD HAL Extended module */
#include "stm32f3xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1U
#define PCD_PHY_EMBEDDED 2U
#define PCD_PHY_UTMI 3U
/**
* @}
*/
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
* @brief PCD Error Code definition
* @{
*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
& (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
&= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_WAKEUP_EXTI_LINE)
#define __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE() \
do { \
EXTI->FTSR &= ~(USB_WAKEUP_EXTI_LINE); \
EXTI->RTSR |= USB_WAKEUP_EXTI_LINE; \
} while(0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
* @brief HAL USB OTG PCD Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
} HAL_PCD_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
* @brief HAL USB OTG PCD Callback pointer definition
* @{
*/
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
/**
* @}
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PCD_Private_Constants PCD Private Constants
* @{
*/
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
* @{
*/
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
/**
* @}
*/
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
#define PCD_EP0MPS_64 EP_MPS_64
#define PCD_EP0MPS_32 EP_MPS_32
#define PCD_EP0MPS_16 EP_MPS_16
#define PCD_EP0MPS_08 EP_MPS_8
/**
* @}
*/
/** @defgroup PCD_ENDP PCD ENDP
* @{
*/
#define PCD_ENDP0 0U
#define PCD_ENDP1 1U
#define PCD_ENDP2 2U
#define PCD_ENDP3 3U
#define PCD_ENDP4 4U
#define PCD_ENDP5 5U
#define PCD_ENDP6 6U
#define PCD_ENDP7 7U
/**
* @}
*/
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
* @{
*/
#define PCD_SNG_BUF 0U
#define PCD_DBL_BUF 1U
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
/******************** Bit definition for USB_COUNTn_RX register *************/
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\
(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
/* ENDPOINT transfer */
#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wType Endpoint Type.
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
& USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Endpoint Type
*/
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
/**
* @brief free buffer used from the application realizing it to the line
* toggles bit SW_BUF in the double buffered endpoint register
* @param USBx USB device.
* @param bEpNum, bDir
* @retval None
*/
#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
else if ((bDir) == 1U) \
{ \
/* IN double buffered endpoint */ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
/**
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wStaterx new state.
* @param wStatetx new state.
* @retval None
*/
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TXRX_STATUS */
/**
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
* /STAT_RX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval status
*/
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
/**
* @brief sets directly the VALID tx/rx-status into the endpoint register
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
/**
* @brief checks stall condition in an endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
/**
* @brief set & clear EP_KIND bit.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_EP_KIND */
/**
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
} while(0) /* PCD_CLEAR_TX_EP_CTR */
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
#define PCD_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
} while(0) /* PCD_TX_DTOG */
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
{ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
{ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
} while(0) /* PCD_CLEAR_TX_DTOG */
/**
* @brief Sets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_ADDRESS */
/**
* @brief Gets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/**
* @brief sets address of the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval address of the buffer.
*/
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
/**
* @brief Sets counter of rx buffer with no. of blocks.
* @param pdwReg Register pointer
* @param wCount Counter.
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
(wNBlocks)--; \
} \
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
(wNBlocks)++; \
} \
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
if ((wCount) == 0U) \
{ \
*(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else if((wCount) <= 62U) \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
} while(0)
/**
* @brief sets counter for the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wCount Counter value.
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
} while(0)
/**
* @brief gets counter of the tx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Counter value
*/
#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
/**
* @brief Sets addresses in a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wBuf0Addr: buffer 0 address.
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param bDir endpoint dir EP_DBUF_OUT = OUT
* EP_DBUF_IN = IN
* @param wCount: Counter value
* @retval None
*/
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
} \
else \
{ \
if ((bDir) == 1U) \
{ \
/* IN endpoint */ \
PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
} \
} \
} while(0) /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
if ((bDir) == 0U) \
{ \
/* OUT endpoint */ \
PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
} \
else \
{ \
if ((bDir) == 1U) \
{ \
/* IN endpoint */ \
_wBase += (uint32_t)(USBx)->BTABLE; \
_wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
*_wEPRegVal = (uint16_t)(wCount); \
} \
} \
} while(0) /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

84
Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pcd_ex.h Normal file
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@@ -0,0 +1,84 @@
/**
******************************************************************************
* @file stm32f3xx_hal_pcd_ex.h
* @author MCD Application Team
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_PCD_EX_H
#define STM32F3xx_HAL_PCD_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
#if defined (USB)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup PCDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

219
Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_pwr.h Normal file
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@@ -0,0 +1,219 @@
/**
******************************************************************************
* @file stm32f3xx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_PWR_H
#define __STM32F3xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup PWR PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
* @{
*/
#define PWR_WAKEUP_PIN1 ((uint32_t)PWR_CSR_EWUP1) /*!< Wakeup pin 1U */
#define PWR_WAKEUP_PIN2 ((uint32_t)PWR_CSR_EWUP2) /*!< Wakeup pin 2U */
#define PWR_WAKEUP_PIN3 ((uint32_t)PWR_CSR_EWUP3) /*!< Wakeup pin 3U */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON (0x00000000U) /*!< Voltage regulator on during STOP mode */
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS /*!< Voltage regulator in low-power mode during STOP mode */
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter SLEEP mode */
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter SLEEP mode */
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) /*!< Wait For Interruption instruction to enter STOP mode */
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) /*!< Wait For Event instruction to enter STOP mode */
/**
* @}
*/
/** @defgroup PWR_Flag PWR Flag
* @{
*/
#define PWR_FLAG_WU PWR_CSR_WUF /*!< Wakeup event from wakeup pin or RTC alarm */
#define PWR_FLAG_SB PWR_CSR_SBF /*!< Standby flag */
#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Power Voltage Detector output flag */
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF /*!< VREFINT reference voltage ready */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macro PWR Exported Macro
* @{
*/
/** @brief Check PWR flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
* was received from the WKUP pin or from the RTC alarm (Alarm A
* or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
* An additional wakeup event is detected if the WKUP pin is enabled
* (by setting the EWUP bit) when the WKUP pin level is already high.
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
* resumed from StandBy mode.
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference
* voltage VREFINT is ready.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the PWR's pending flags.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_WU: Wake Up flag
* @arg PWR_FLAG_SB: StandBy flag
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
/**
* @}
*/
/* Include PWR HAL Extended module */
#include "stm32f3xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_PWR_DeInit(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions **********************************************/
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_PWR_EX_H
#define __STM32F3xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
* @{
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F303x8) || defined(STM32F334x8) || \
defined(STM32F301x8) || defined(STM32F302x8) || \
defined(STM32F373xC)
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level
This parameter can be a value of @ref PWREx_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWREx_PVD_Mode */
}PWR_PVDTypeDef;
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || STM32F302x8 || */
/* STM32F373xC */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
* @{
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F303x8) || defined(STM32F334x8) || \
defined(STM32F301x8) || defined(STM32F302x8) || \
defined(STM32F373xC)
/** @defgroup PWREx_PVD_detection_level PWR Extended PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 /*!< PVD threshold around 2.2 V */
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 /*!< PVD threshold around 2.3 V */
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 /*!< PVD threshold around 2.4 V */
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 /*!< PVD threshold around 2.5 V */
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 /*!< PVD threshold around 2.6 V */
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 /*!< PVD threshold around 2.7 V */
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 /*!< PVD threshold around 2.8 V */
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /*!< PVD threshold around 2.9 V */
/**
* @}
*/
/** @defgroup PWREx_PVD_Mode PWR Extended PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
#define PWR_EXTI_LINE_PVD EXTI_IMR_MR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || STM32F302x8 || */
/* STM32F373xC */
#if defined(STM32F373xC) || defined(STM32F378xx)
/** @defgroup PWREx_SDADC_ANALOGx PWR Extended SDADC ANALOGx
* @{
*/
#define PWR_SDADC_ANALOG1 ((uint32_t)PWR_CR_ENSD1) /*!< Enable SDADC1 */
#define PWR_SDADC_ANALOG2 ((uint32_t)PWR_CR_ENSD2) /*!< Enable SDADC2 */
#define PWR_SDADC_ANALOG3 ((uint32_t)PWR_CR_ENSD3) /*!< Enable SDADC3 */
/**
* @}
*/
#endif /* STM32F373xC || STM32F378xx */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
* @{
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F303x8) || defined(STM32F334x8) || \
defined(STM32F301x8) || defined(STM32F302x8) || \
defined(STM32F373xC)
/**
* @brief Enable interrupt on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
/**
* @brief Disable interrupt on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
/**
* @brief Enable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
/**
* @brief Disable event on PVD Exti Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/**
* @brief PVD EXTI line configuration: set falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set rising edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
/**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
/**
* @brief Clear the PVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || STM32F302x8 || */
/* STM32F373xC */
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
* @{
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F303x8) || defined(STM32F334x8) || \
defined(STM32F301x8) || defined(STM32F302x8) || \
defined(STM32F373xC)
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || STM32F302x8 || */
/* STM32F373xC */
#if defined(STM32F373xC) || defined(STM32F378xx)
#define IS_PWR_SDADC_ANALOG(SDADC) (((SDADC) == PWR_SDADC_ANALOG1) || \
((SDADC) == PWR_SDADC_ANALOG2) || \
((SDADC) == PWR_SDADC_ANALOG3))
#endif /* STM32F373xC || STM32F378xx */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions
* @{
*/
/* Peripheral Extended control functions **************************************/
#if defined(STM32F302xE) || defined(STM32F303xE) || \
defined(STM32F302xC) || defined(STM32F303xC) || \
defined(STM32F303x8) || defined(STM32F334x8) || \
defined(STM32F301x8) || defined(STM32F302x8) || \
defined(STM32F373xC)
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || STM32F302x8 || */
/* STM32F373xC */
#if defined(STM32F373xC) || defined(STM32F378xx)
void HAL_PWREx_EnableSDADC(uint32_t Analogx);
void HAL_PWREx_DisableSDADC(uint32_t Analogx);
#endif /* STM32F373xC || STM32F378xx */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_PWR_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_rtc.h
* @author MCD Application Team
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_RTC_H
#define __STM32F3xx_HAL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @defgroup RTC RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
} HAL_RTCStateTypeDef;
/**
* @brief RTC Configuration Structure definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
} RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight
Saving Time, please use HAL_RTC_DST_xxx functions */
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight
Saving Time, please use HAL_RTC_DST_xxx functions */
} RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
} RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
uint32_t Alarm; /*!< Specifies the alarm .
This parameter can be a value of @ref RTC_Alarms_Definitions */
} RTC_AlarmTypeDef;
/**
* @brief RTC Handle Structure definition
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
typedef struct __RTC_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
{
RTC_TypeDef *Instance; /*!< Register base address */
RTC_InitTypeDef Init; /*!< RTC required parameters */
HAL_LockTypeDef Lock; /*!< RTC locking object */
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */
void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */
void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */
void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */
void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */
void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */
#if defined(RTC_TAMPER3_SUPPORT)
void (* Tamper3EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 3 Event callback */
#endif /* RTC_TAMPER3_SUPPORT */
void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */
void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
} RTC_HandleTypeDef;
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL RTC Callback ID enumeration definition
*/
typedef enum
{
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */
#if defined(RTC_TAMPER3_SUPPORT)
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06u, /*!< RTC Tamper 3 Callback ID */
#endif /* RTC_TAMPER3_SUPPORT */
HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */
HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */
}HAL_RTC_CallbackIDTypeDef;
/**
* @brief HAL RTC Callback pointer definition
*/
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 0x00000000U
#define RTC_HOURFORMAT_12 RTC_CR_FMT
/**
* @}
*/
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
/**
* @}
*/
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U
#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
/**
* @}
*/
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET 0x00000000U
#define RTC_STOREOPERATION_SET RTC_CR_BCK
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions
* @{
*/
#define RTC_FORMAT_BIN 0x000000000U
#define RTC_FORMAT_BCD 0x000000001U
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
/**
* @}
*/
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
/**
* @}
*/
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
/**
* @}
*/
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE 0x00000000U
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_NONE | \
RTC_ALARMMASK_DATEWEEKDAY | \
RTC_ALARMMASK_HOURS | \
RTC_ALARMMASK_MINUTES | \
RTC_ALARMMASK_SECONDS)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
/**
* @}
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are ignored in Alarm
comparison. Only SS[0] is compared. */
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are ignored in Alarm
comparison. Only SS[1:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] are ignored in Alarm
comparison. Only SS[2:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are ignored in Alarm
comparison. Only SS[3:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] are ignored in Alarm
comparison. Only SS[4:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] are ignored in Alarm
comparison. Only SS[5:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] are ignored in Alarm
comparison. Only SS[6:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are ignored in Alarm
comparison. Only SS[7:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] are ignored in Alarm
comparison. Only SS[8:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] are ignored in Alarm
comparison. Only SS[9:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] are ignored in Alarm
comparison. Only SS[10:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] are ignored in Alarm
comparison.Only SS[11:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] are ignored in Alarm
comparison. Only SS[12:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
to activate alarm. */
/**
* @}
*/
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS RTC_CR_TSIE
#define RTC_IT_WUT RTC_CR_WUTIE
#define RTC_IT_ALRB RTC_CR_ALRBIE
#define RTC_IT_ALRA RTC_CR_ALRAIE
#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /* Used only to Enable the Tamper Interrupt */
#define RTC_IT_TAMP1 0x00020000U /*only for RTC_ISR flag check*/
#define RTC_IT_TAMP2 0x00040000U /*only for RTC_ISR flag check*/
#if defined(RTC_TAMPER3_SUPPORT)
#define RTC_IT_TAMP3 0x00080000U /*only for RTC_ISR flag check*/
#endif /* RTC_TAMPER3_SUPPORT */
/**
* @}
*/
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
#if defined(RTC_TAMPER3_SUPPORT)
#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F
#endif /* RTC_TAMPER3_SUPPORT */
#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
#define RTC_FLAG_TSF RTC_ISR_TSF
#define RTC_FLAG_WUTF RTC_ISR_WUTF
#define RTC_FLAG_ALRBF RTC_ISR_ALRBF
#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
#define RTC_FLAG_INITF RTC_ISR_INITF
#define RTC_FLAG_RSF RTC_ISR_RSF
#define RTC_FLAG_INITS RTC_ISR_INITS
#define RTC_FLAG_SHPF RTC_ISR_SHPF
#define RTC_FLAG_WUTWF RTC_ISR_WUTWF
#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF
#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
/** @brief Reset RTC handle state
* @param __HANDLE__ RTC handle.
* @retval None
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL;\
(__HANDLE__)->MspDeInitCallback = NULL;\
}while(0u)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Disable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xCAU; \
(__HANDLE__)->Instance->WPR = 0x53U; \
} while(0U)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0U)
/**
* @brief Enable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
/**
* @brief Disable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
/**
* @brief Enable the RTC ALARMB peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
/**
* @brief Disable the RTC ALARMB peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
/**
* @brief Enable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET)
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag sources to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
* @arg RTC_FLAG_ALRAWF
* @arg RTC_FLAG_ALRBWF
* @retval None
*/
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
/**
* @brief Clear the RTC Alarm's pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
* @retval None
*/
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Enable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();
/**
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Clear the RTC Alarm associated Exti line flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @}
*/
/* Include RTC HAL Extended module */
#include "stm32f3xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @{
*/
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
/* RTC Daylight Saving Time functions *****************************************/
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @{
*/
/* RTC Alarm functions ********************************************************/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK 0x007F7F7FU
#define RTC_DR_RESERVED_MASK 0x00FFFF3FU
#define RTC_INIT_MASK 0xFFFFFFFFU
#define RTC_RSF_MASK 0xFFFFFF5FU
#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
RTC_FLAG_INITF | RTC_FLAG_RSF | \
RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
#define RTC_TIMEOUT_VALUE 1000
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR19 /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
/**
* @}
*/
/* Private macros -----------------------------------------------------------*/
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
* @{
*/
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U)
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U)
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
((PM) == RTC_HOURFORMAT12_PM))
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U))
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET)
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU)
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
/**
* @}
*/
/**
* @}
*/
/* Private functions -------------------------------------------------------------*/
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_RTC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_sdadc.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the SDADC
* firmware library.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_SDADC_H
#define __STM32F3xx_SDADC_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(SDADC1) || defined(SDAD2) || defined(SDADC3)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup SDADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDADC_Exported_Types SDADC Exported Types
* @{
*/
/**
* @brief HAL SDADC States definition
*/
typedef enum
{
HAL_SDADC_STATE_RESET = 0x00U, /*!< SDADC not initialized */
HAL_SDADC_STATE_READY = 0x01U, /*!< SDADC initialized and ready for use */
HAL_SDADC_STATE_CALIB = 0x02U, /*!< SDADC calibration in progress */
HAL_SDADC_STATE_REG = 0x03U, /*!< SDADC regular conversion in progress */
HAL_SDADC_STATE_INJ = 0x04U, /*!< SDADC injected conversion in progress */
HAL_SDADC_STATE_REG_INJ = 0x05U, /*!< SDADC regular and injected conversions in progress */
HAL_SDADC_STATE_ERROR = 0xFFU, /*!< SDADC state error */
}HAL_SDADC_StateTypeDef;
/**
* @brief SDADC Init Structure definition
*/
typedef struct
{
uint32_t IdleLowPowerMode; /*!< Specifies if SDADC can enter in power down or standby when idle.
This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
uint32_t FastConversionMode; /*!< Specifies if Fast conversion mode is enabled or not.
This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
uint32_t SlowClockMode; /*!< Specifies if slow clock mode is enabled or not.
This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
uint32_t ReferenceVoltage; /*!< Specifies the reference voltage.
Note: This parameter is common to all SDADC instances.
This parameter can be a value of @ref SDADC_Reference_Voltage */
}SDADC_InitTypeDef;
/**
* @brief SDADC handle Structure definition
*/
typedef struct __SDADC_HandleTypeDef
{
SDADC_TypeDef *Instance; /*!< SDADC registers base address */
SDADC_InitTypeDef Init; /*!< SDADC init parameters */
DMA_HandleTypeDef *hdma; /*!< SDADC DMA Handle parameters */
uint32_t RegularContMode; /*!< Regular conversion continuous mode */
uint32_t InjectedContMode; /*!< Injected conversion continuous mode */
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
uint32_t InjConvRemaining; /*!< Injected conversion remaining */
uint32_t RegularTrigger; /*!< Current trigger used for regular conversion */
uint32_t InjectedTrigger; /*!< Current trigger used for injected conversion */
uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
uint32_t RegularMultimode; /*!< current type of regular multimode */
uint32_t InjectedMultimode; /*!< Current type of injected multimode */
HAL_SDADC_StateTypeDef State; /*!< SDADC state */
uint32_t ErrorCode; /*!< SDADC Error code */
#if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
void (* ConvHalfCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC half regular conversion complete callback */
void (* ConvCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC regular conversion complete callback */
void (* InjectedConvHalfCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC half injected conversion complete callback */
void (* InjectedConvCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC injected conversion complete callback */
void (* CalibrationCpltCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC calibration callback */
void (* ErrorCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC error callback */
void (* MspInitCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC Msp Init callback */
void (* MspDeInitCallback)(struct __SDADC_HandleTypeDef *hadc); /*!< SDADC Msp DeInit callback */
#endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
}SDADC_HandleTypeDef;
/**
* @brief SDADC Configuration Register Parameter Structure
*/
typedef struct
{
uint32_t InputMode; /*!< Specifies the input mode (single ended, differential...)
This parameter can be any value of @ref SDADC_InputMode */
uint32_t Gain; /*!< Specifies the gain setting.
This parameter can be any value of @ref SDADC_Gain */
uint32_t CommonMode; /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U).
This parameter can be any value of @ref SDADC_CommonMode */
uint32_t Offset; /*!< Specifies the 12-bit offset value.
This parameter can be any value lower or equal to 0x00000FFFU */
}SDADC_ConfParamTypeDef;
#if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SDADC Callback ID enumeration definition
*/
typedef enum
{
HAL_SDADC_CONVERSION_HALF_CB_ID = 0x00U, /*!< SDADC half regular conversion complete callback ID */
HAL_SDADC_CONVERSION_COMPLETE_CB_ID = 0x01U, /*!< SDADC regular conversion complete callback ID */
HAL_SDADC_INJ_CONVERSION_HALF_CB_ID = 0x02U, /*!< SDADC half injected conversion complete callback ID */
HAL_SDADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x03U, /*!< SDADC injected conversion complete callback ID */
HAL_SDADC_CALIBRATION_COMPLETE_CB_ID = 0x04U, /*!< SDADC calibration callback ID */
HAL_SDADC_ERROR_CB_ID = 0x05U, /*!< SDADC error callback ID */
HAL_SDADC_MSPINIT_CB_ID = 0x06U, /*!< SDADC Msp Init callback ID */
HAL_SDADC_MSPDEINIT_CB_ID = 0x07U /*!< SDADC Msp DeInit callback ID */
} HAL_SDADC_CallbackIDTypeDef;
/**
* @brief HAL SDADC Callback pointer definition
*/
typedef void (*pSDADC_CallbackTypeDef)(SDADC_HandleTypeDef *hsdadc); /*!< pointer to a SDADC callback function */
#endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SDADC_Exported_Constants SDADC Exported Constants
* @{
*/
/** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
* @{
*/
#define SDADC_LOWPOWER_NONE (0x00000000UL)
#define SDADC_LOWPOWER_POWERDOWN SDADC_CR1_PDI
#define SDADC_LOWPOWER_STANDBY SDADC_CR1_SBI
/**
* @}
*/
/** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
* @{
*/
#define SDADC_FAST_CONV_DISABLE (0x00000000UL)
#define SDADC_FAST_CONV_ENABLE SDADC_CR2_FAST
/**
* @}
*/
/** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
* @{
*/
#define SDADC_SLOW_CLOCK_DISABLE (0x00000000UL)
#define SDADC_SLOW_CLOCK_ENABLE SDADC_CR1_SLOWCK
/**
* @}
*/
/** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
* @{
*/
#define SDADC_VREF_EXT (0x00000000UL) /*!< The reference voltage is forced externally using VREF pin */
#define SDADC_VREF_VREFINT1 SDADC_CR1_REFV_0 /*!< The reference voltage is forced internally to 1.22V VREFINT */
#define SDADC_VREF_VREFINT2 SDADC_CR1_REFV_1 /*!< The reference voltage is forced internally to 1.8V VREFINT */
#define SDADC_VREF_VDDA SDADC_CR1_REFV /*!< The reference voltage is forced internally to VDDA */
/**
* @}
*/
/** @defgroup SDADC_ConfIndex SDADC Configuration Index
* @{
*/
#define SDADC_CONF_INDEX_0 (0x00000000UL) /*!< Configuration 0 Register selected */
#define SDADC_CONF_INDEX_1 (0x00000001U) /*!< Configuration 1 Register selected */
#define SDADC_CONF_INDEX_2 (0x00000002U) /*!< Configuration 2 Register selected */
/**
* @}
*/
/** @defgroup SDADC_InputMode SDADC Input Mode
* @{
*/
#define SDADC_INPUT_MODE_DIFF (0x00000000UL) /*!< Conversions are executed in differential mode */
#define SDADC_INPUT_MODE_SE_OFFSET SDADC_CONF0R_SE0_0 /*!< Conversions are executed in single ended offset mode */
#define SDADC_INPUT_MODE_SE_ZERO_REFERENCE SDADC_CONF0R_SE0 /*!< Conversions are executed in single ended zero-volt reference mode */
/**
* @}
*/
/** @defgroup SDADC_Gain SDADC Gain
* @{
*/
#define SDADC_GAIN_1 (0x00000000UL) /*!< Gain equal to 1U */
#define SDADC_GAIN_2 SDADC_CONF0R_GAIN0_0 /*!< Gain equal to 2U */
#define SDADC_GAIN_4 SDADC_CONF0R_GAIN0_1 /*!< Gain equal to 4U */
#define SDADC_GAIN_8 (0x00300000U) /*!< Gain equal to 8U */
#define SDADC_GAIN_16 SDADC_CONF0R_GAIN0_2 /*!< Gain equal to 16U */
#define SDADC_GAIN_32 (0x00500000U) /*!< Gain equal to 32U */
#define SDADC_GAIN_1_2 SDADC_CONF0R_GAIN0 /*!< Gain equal to 1U/2U */
/**
* @}
*/
/** @defgroup SDADC_CommonMode SDADC Common Mode
* @{
*/
#define SDADC_COMMON_MODE_VSSA (0x00000000UL) /*!< Select SDADC VSSA as common mode */
#define SDADC_COMMON_MODE_VDDA_2 SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
#define SDADC_COMMON_MODE_VDDA SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
/**
* @}
*/
/** @defgroup SDADC_Channel_Selection SDADC Channel Selection
* @{
*/
/* SDADC Channels ------------------------------------------------------------*/
/* The SDADC channels are defined as follows:
- in 16-bit LSB the channel mask is set
- in 16-bit MSB the channel number is set
e.g. for channel 5 definition:
- the channel mask is 0x00000020 (bit 5 is set)
- the channel number 5 is 0x00050000
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
#define SDADC_CHANNEL_0 (0x00000001UL)
#define SDADC_CHANNEL_1 (0x00010002UL)
#define SDADC_CHANNEL_2 (0x00020004UL)
#define SDADC_CHANNEL_3 (0x00030008UL)
#define SDADC_CHANNEL_4 (0x00040010UL)
#define SDADC_CHANNEL_5 (0x00050020UL)
#define SDADC_CHANNEL_6 (0x00060040UL)
#define SDADC_CHANNEL_7 (0x00070080UL)
#define SDADC_CHANNEL_8 (0x00080100UL)
/**
* @}
*/
/** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
* @{
*/
#define SDADC_CALIBRATION_SEQ_1 (0x00000000UL) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
#define SDADC_CALIBRATION_SEQ_2 SDADC_CR2_CALIBCNT_0 /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
#define SDADC_CALIBRATION_SEQ_3 SDADC_CR2_CALIBCNT_1 /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
/**
* @}
*/
/** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
* @{
*/
#define SDADC_CONTINUOUS_CONV_OFF (0x00000000UL) /*!< Conversion are not continuous */
#define SDADC_CONTINUOUS_CONV_ON (0x00000001UL) /*!< Conversion are continuous */
/**
* @}
*/
/** @defgroup SDADC_Trigger SDADC Trigger
* @{
*/
#define SDADC_SOFTWARE_TRIGGER (0x00000000UL) /*!< Software trigger */
#define SDADC_SYNCHRONOUS_TRIGGER (0x00000001UL) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
#define SDADC_EXTERNAL_TRIGGER (0x00000002UL) /*!< External trigger */
/**
* @}
*/
/** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
* @{
*/
#define SDADC_EXT_TRIG_TIM13_CC1 (0x00000000UL) /*!< Trigger source for SDADC1 */
#define SDADC_EXT_TRIG_TIM14_CC1 (0x00000100UL) /*!< Trigger source for SDADC1 */
#define SDADC_EXT_TRIG_TIM16_CC1 (0x00000000UL) /*!< Trigger source for SDADC3 */
#define SDADC_EXT_TRIG_TIM17_CC1 (0x00000000UL) /*!< Trigger source for SDADC2 */
#define SDADC_EXT_TRIG_TIM12_CC1 (0x00000100UL) /*!< Trigger source for SDADC2 */
#define SDADC_EXT_TRIG_TIM12_CC2 (0x00000100UL) /*!< Trigger source for SDADC3 */
#define SDADC_EXT_TRIG_TIM15_CC2 (0x00000200UL) /*!< Trigger source for SDADC1 */
#define SDADC_EXT_TRIG_TIM2_CC3 (0x00000200UL) /*!< Trigger source for SDADC2 */
#define SDADC_EXT_TRIG_TIM2_CC4 (0x00000200UL) /*!< Trigger source for SDADC3 */
#define SDADC_EXT_TRIG_TIM3_CC1 (0x00000300UL) /*!< Trigger source for SDADC1 */
#define SDADC_EXT_TRIG_TIM3_CC2 (0x00000300UL) /*!< Trigger source for SDADC2 */
#define SDADC_EXT_TRIG_TIM3_CC3 (0x00000300UL) /*!< Trigger source for SDADC3 */
#define SDADC_EXT_TRIG_TIM4_CC1 (0x00000400UL) /*!< Trigger source for SDADC1 */
#define SDADC_EXT_TRIG_TIM4_CC2 (0x00000400UL) /*!< Trigger source for SDADC2 */
#define SDADC_EXT_TRIG_TIM4_CC3 (0x00000400UL) /*!< Trigger source for SDADC3 */
#define SDADC_EXT_TRIG_TIM19_CC2 (0x00000500UL) /*!< Trigger source for SDADC1 */
#define SDADC_EXT_TRIG_TIM19_CC3 (0x00000500UL) /*!< Trigger source for SDADC2 */
#define SDADC_EXT_TRIG_TIM19_CC4 (0x00000500UL) /*!< Trigger source for SDADC3 */
#define SDADC_EXT_TRIG_EXTI11 (0x00000700UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
#define SDADC_EXT_TRIG_EXTI15 (0x00000600UL) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
/**
* @}
*/
/** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
* @{
*/
#define SDADC_EXT_TRIG_RISING_EDGE SDADC_CR2_JEXTEN_0 /*!< External rising edge */
#define SDADC_EXT_TRIG_FALLING_EDGE SDADC_CR2_JEXTEN_1 /*!< External falling edge */
#define SDADC_EXT_TRIG_BOTH_EDGES SDADC_CR2_JEXTEN /*!< External rising and falling edges */
/**
* @}
*/
/** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
* @{
*/
#define SDADC_INJECTED_DELAY_NONE (0x00000000UL) /*!< No delay on injected conversion */
#define SDADC_INJECTED_DELAY SDADC_CR2_JDS /*!< Delay on injected conversion */
/**
* @}
*/
/** @defgroup SDADC_MultimodeType SDADC Multimode Type
* @{
*/
#define SDADC_MULTIMODE_SDADC1_SDADC2 (0x00000000UL) /*!< Get conversion values for SDADC1 and SDADC2 */
#define SDADC_MULTIMODE_SDADC1_SDADC3 (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */
/**
* @}
*/
/** @defgroup SDADC_ErrorCode SDADC Error Code
* @{
*/
#define SDADC_ERROR_NONE (0x00000000UL) /*!< No error */
#define SDADC_ERROR_REGULAR_OVERRUN (0x00000001UL) /*!< Overrun occurs during regular conversion */
#define SDADC_ERROR_INJECTED_OVERRUN (0x00000002UL) /*!< Overrun occurs during injected conversion */
#define SDADC_ERROR_DMA (0x00000003UL) /*!< DMA error occurs */
#if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
#define SDADC_ERROR_INVALID_CALLBACK (0x00000004UL) /*!< Invalid Callback error */
#endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SDADC_interrupts_definition SDADC interrupts definition
* @{
*/
#define SDADC_IT_EOCAL SDADC_CR1_EOCALIE /*!< End of calibration interrupt enable */
#define SDADC_IT_JEOC SDADC_CR1_JEOCIE /*!< Injected end of conversion interrupt enable */
#define SDADC_IT_JOVR SDADC_CR1_JOVRIE /*!< Injected data overrun interrupt enable */
#define SDADC_IT_REOC SDADC_CR1_REOCIE /*!< Regular end of conversion interrupt enable */
#define SDADC_IT_ROVR SDADC_CR1_ROVRIE /*!< Regular data overrun interrupt enable */
/**
* @}
*/
/** @defgroup SDADC_flags_definition SDADC flags definition
* @{
*/
#define SDADC_FLAG_EOCAL SDADC_ISR_EOCALF /*!< End of calibration flag */
#define SDADC_FLAG_JEOC SDADC_ISR_JEOCF /*!< End of injected conversion flag */
#define SDADC_FLAG_JOVR SDADC_ISR_JOVRF /*!< Injected conversion overrun flag */
#define SDADC_FLAG_REOC SDADC_ISR_REOCF /*!< End of regular conversion flag */
#define SDADC_FLAG_ROVR SDADC_ISR_ROVRF /*!< Regular conversion overrun flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SDADC_Exported_Macros SDADC Exported Macros
* @{
*/
/* Macro for internal HAL driver usage, and possibly can be used into code of */
/* final user. */
/** @brief Enable the ADC end of conversion interrupt.
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC Interrupt
* This parameter can be any combination of the following values:
* @arg SDADC_IT_EOCAL: End of calibration interrupt enable
* @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
* @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
* @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
* @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
* @retval None
*/
#define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
/** @brief Disable the ADC end of conversion interrupt.
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC Interrupt
* This parameter can be any combination of the following values:
* @arg SDADC_IT_EOCAL: End of calibration interrupt enable
* @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
* @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
* @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
* @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
* @retval None
*/
#define __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC interrupt source to check
* This parameter can be any combination of the following values:
* @arg SDADC_IT_EOCAL: End of calibration interrupt enable
* @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
* @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
* @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
* @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
* @retval State of interruption (SET or RESET)
*/
#define __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected ADC's flag status.
* @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag
* This parameter can be any combination of the following values:
* @arg SDADC_FLAG_EOCAL: End of calibration flag
* @arg SDADC_FLAG_JEOC: End of injected conversion flag
* @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
* @arg SDADC_FLAG_REOC: End of regular conversion flag
* @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
* @retval None
*/
#define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the ADC's pending flags
* @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag
* This parameter can be any combination of the following values:
* @arg SDADC_FLAG_EOCAL: End of calibration flag
* @arg SDADC_FLAG_JEOC: End of injected conversion flag
* @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
* @arg SDADC_FLAG_REOC: End of regular conversion flag
* @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
* @retval None
*/
#define __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
/** @brief Reset SDADC handle state
* @param __HANDLE__ SDADC handle.
* @retval None
*/
#if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
#define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
(__HANDLE__)->State = HAL_SDADC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
#endif
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SDADC_Private_Macros SDADC Private Macros
* @{
*/
#define IS_SDADC_LOWPOWER_MODE(LOWPOWER) (((LOWPOWER) == SDADC_LOWPOWER_NONE) || \
((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
#define IS_SDADC_FAST_CONV_MODE(FAST) (((FAST) == SDADC_FAST_CONV_DISABLE) || \
((FAST) == SDADC_FAST_CONV_ENABLE))
#define IS_SDADC_SLOW_CLOCK_MODE(MODE) (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
((MODE) == SDADC_SLOW_CLOCK_ENABLE))
#define IS_SDADC_VREF(VREF) (((VREF) == SDADC_VREF_EXT) || \
((VREF) == SDADC_VREF_VREFINT1) || \
((VREF) == SDADC_VREF_VREFINT2) || \
((VREF) == SDADC_VREF_VDDA))
#define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0) || \
((CONF) == SDADC_CONF_INDEX_1) || \
((CONF) == SDADC_CONF_INDEX_2))
#define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF) || \
((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
#define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1) || \
((GAIN) == SDADC_GAIN_2) || \
((GAIN) == SDADC_GAIN_4) || \
((GAIN) == SDADC_GAIN_8) || \
((GAIN) == SDADC_GAIN_16) || \
((GAIN) == SDADC_GAIN_32) || \
((GAIN) == SDADC_GAIN_1_2))
#define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA) || \
((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
((MODE) == SDADC_COMMON_MODE_VDDA))
#define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
/* Just one channel of the 9 channels can be selected for regular conversion */
#define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0) || \
((CHANNEL) == SDADC_CHANNEL_1) || \
((CHANNEL) == SDADC_CHANNEL_2) || \
((CHANNEL) == SDADC_CHANNEL_3) || \
((CHANNEL) == SDADC_CHANNEL_4) || \
((CHANNEL) == SDADC_CHANNEL_5) || \
((CHANNEL) == SDADC_CHANNEL_6) || \
((CHANNEL) == SDADC_CHANNEL_7) || \
((CHANNEL) == SDADC_CHANNEL_8))
/* Any or all of the 9 channels can be selected for injected conversion */
#define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
#define IS_SDADC_CALIB_SEQUENCE(SEQUENCE) (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1) || \
((SEQUENCE) == SDADC_CALIBRATION_SEQ_2) || \
((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
#define IS_SDADC_CONTINUOUS_MODE(MODE) (((MODE) == SDADC_CONTINUOUS_CONV_OFF) || \
((MODE) == SDADC_CONTINUOUS_CONV_ON))
#define IS_SDADC_REGULAR_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
#define IS_SDADC_INJECTED_TRIGGER(TRIGGER) (((TRIGGER) == SDADC_SOFTWARE_TRIGGER) || \
((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER) || \
((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
#define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
#define IS_SDADC_EXT_TRIG_EDGE(TRIGGER) (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE) || \
((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE) || \
((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
#define IS_SDADC_INJECTED_DELAY(DELAY) (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
((DELAY) == SDADC_INJECTED_DELAY))
#define IS_SDADC_MULTIMODE_TYPE(TYPE) (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
* @{
*/
/** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
#if (USE_HAL_SDADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SDADC_RegisterCallback(SDADC_HandleTypeDef *sdhadc, HAL_SDADC_CallbackIDTypeDef CallbackID, pSDADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SDADC_UnRegisterCallback(SDADC_HandleTypeDef *sdhadc, HAL_SDADC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SDADC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
uint32_t ConfIndex,
SDADC_ConfParamTypeDef* ConfParamStruct);
HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
uint32_t Channel,
uint32_t ConfIndex);
HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
uint32_t Channel,
uint32_t ContinuousMode);
HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
uint32_t Channel,
uint32_t ContinuousMode);
HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
uint32_t InjectedExtTrigger,
uint32_t ExtTriggerEdge);
HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
uint32_t InjectedDelay);
HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
/**
* @}
*/
/** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
/**
* @}
*/
/** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
uint32_t HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SDADC1 || SDAD2 || SDADC3 */
#ifdef __cplusplus
}
#endif
#endif /*__STM32F3xx_SDADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@@ -0,0 +1,414 @@
/**
******************************************************************************
* @file stm32f3xx_hal_smartcard_ex.h
* @author MCD Application Team
* @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_SMARTCARD_EX_H
#define STM32F3xx_HAL_SMARTCARD_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup SMARTCARDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
* @{
*/
/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
* @{
*/
#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
* @{
*/
#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 000ZZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5 bits)
* - XX : Interrupt source register (2 bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZZ : Flag position in the ISR register(5 bits)
* @{
*/
#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
/**
* @}
*/
/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
* @{
*/
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise error detected clear flag */
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
* @{
*/
/** @brief Report the SMARTCARD clock source.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F302xE)|| defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif
/** @brief Set the Transmission Completion flag
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
* AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
* to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
* @retval None
*/
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
do { \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} while(0U)
/** @brief Return the transmission completion flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
* When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
* reported.
* @retval Transmission completion flag
*/
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC)
/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
* @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
*/
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/* IO operation methods *******************************************************/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ***********************************************/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_SMARTCARD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_smbus.h
* @author MCD Application Team
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_SMBUS_H
#define STM32F3xx_HAL_SMBUS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup SMBUS
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
* @{
*/
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
* @brief SMBUS Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
This parameter calculated by referring to SMBUS initialization section
in Reference manual */
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
This parameter can be a value of @ref SMBUS_Analog_Filter */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
This parameter can be a value of @ref SMBUS_addressing_mode */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref SMBUS_nostretch_mode */
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
(Enable bits and different timeout values)
This parameter calculated by referring to SMBUS initialization section
in Reference manual */
} SMBUS_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_definition HAL state definition
* @brief HAL State definition
* @{
*/
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
*/
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
* @brief SMBUS Error Code definition
* @{
*/
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
* @brief SMBUS handle Structure definition
* @{
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
typedef struct __SMBUS_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
uint16_t XferSize; /*!< SMBUS transfer size */
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
__IO uint32_t State; /*!< SMBUS communication state */
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Listen Complete callback */
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Error callback */
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< SMBUS Slave Address Match callback */
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Msp Init callback */
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Msp DeInit callback */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef;
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SMBUS Callback ID enumeration definition
*/
typedef enum
{
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
} HAL_SMBUS_CallbackIDTypeDef;
/**
* @brief HAL SMBUS Callback pointer definition
*/
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
/*!< pointer to an SMBUS callback function */
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an SMBUS Address Match callback function */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
* @{
*/
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
* @{
*/
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
* @{
*/
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
* @{
*/
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
* @{
*/
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
* @{
*/
#define SMBUS_PEC_DISABLE (0x00000000U)
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
/**
* @}
*/
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
* @{
*/
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
/**
* @}
*/
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
* @{
*/
#define SMBUS_SOFTEND_MODE (0x00000000U)
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
/**
* @}
*/
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
* @{
*/
#define SMBUS_NO_STARTSTOP (0x00000000U)
#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
* @{
*/
/* List of XferOptions in usage of :
* 1- Restart condition when direction change
* 2- No Restart condition in other use cases
*/
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
/**
* @}
*/
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
* @brief SMBUS Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
#define SMBUS_IT_TCI I2C_CR1_TCIE
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
/**
* @}
*/
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
* @brief Flag definition
* Elements values convention: 0xXXXXYYYY
* - XXXXXXXX : Flag mask
* @{
*/
#define SMBUS_FLAG_TXE I2C_ISR_TXE
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define SMBUS_FLAG_AF I2C_ISR_NACKF
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define SMBUS_FLAG_TC I2C_ISR_TC
#define SMBUS_FLAG_TCR I2C_ISR_TCR
#define SMBUS_FLAG_BERR I2C_ISR_BERR
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define SMBUS_FLAG_OVR I2C_ISR_OVR
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define SMBUS_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
* @{
*/
/** @brief Reset SMBUS handle state.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SMBUS flag is set or not.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
* @arg @ref SMBUS_FLAG_BUSY Bus busy
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Enable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
* @{
*/
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
((MASK) == SMBUS_OA2_MASK01) || \
((MASK) == SMBUS_OA2_MASK02) || \
((MASK) == SMBUS_OA2_MASK03) || \
((MASK) == SMBUS_OA2_MASK04) || \
((MASK) == SMBUS_OA2_MASK05) || \
((MASK) == SMBUS_OA2_MASK06) || \
((MASK) == SMBUS_OA2_MASK07))
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
((CALL) == SMBUS_GENERALCALL_ENABLE))
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
((PEC) == SMBUS_PEC_ENABLE))
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
((MODE) == SMBUS_AUTOEND_MODE) || \
((MODE) == SMBUS_SOFTEND_MODE) || \
((MODE) == SMBUS_SENDPEC_MODE) || \
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
((REQUEST) == SMBUS_GENERATE_START_READ) || \
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
((REQUEST) == SMBUS_NO_STARTSTOP))
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
I2C_CR1_PECEN)))
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & \
(I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
(I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
*/
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
HAL_SMBUS_CallbackIDTypeDef CallbackID,
pSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
HAL_SMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
pSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
* @{
*/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/**
* @}
*/
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
* @{
*/
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
/* Private functions are defined in stm32f3xx_hal_smbus.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_SMBUS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_spi.h Normal file
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@@ -0,0 +1,852 @@
/**
******************************************************************************
* @file stm32f3xx_hal_spi.h
* @author MCD Application Team
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_SPI_H
#define STM32F3xx_HAL_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Configuration Structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_Mode */
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
uint32_t DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_Data_Size */
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
This parameter can be a value of @ref SPI_TI_mode */
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_CRC_Calculation */
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
CRC Length is only used with Data8 and Data16, not other data size
This parameter can be a value of @ref SPI_CRC_length */
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
This parameter can be a value of @ref SPI_NSSP_Mode
This mode is activated by the NSSP bit in the SPIx_CR2 register and
it takes effect only if the SPI interface is configured as Motorola SPI
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
CPOL setting is ignored).. */
} SPI_InitTypeDef;
/**
* @brief HAL SPI State structure definition
*/
typedef enum
{
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
} HAL_SPI_StateTypeDef;
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< SPI registers base address */
SPI_InitTypeDef Init; /*!< SPI communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
__IO uint32_t ErrorCode; /*!< SPI Error code */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
} SPI_HandleTypeDef;
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL SPI Callback ID enumeration definition
*/
typedef enum
{
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
} HAL_SPI_CallbackIDTypeDef;
/**
* @brief HAL SPI Callback pointer definition
*/
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SPI_Mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE (0x00000000U)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
*/
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES (0x00000000U)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
* @}
*/
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
#define SPI_DATASIZE_4BIT (0x00000300U)
#define SPI_DATASIZE_5BIT (0x00000400U)
#define SPI_DATASIZE_6BIT (0x00000500U)
#define SPI_DATASIZE_7BIT (0x00000600U)
#define SPI_DATASIZE_8BIT (0x00000700U)
#define SPI_DATASIZE_9BIT (0x00000800U)
#define SPI_DATASIZE_10BIT (0x00000900U)
#define SPI_DATASIZE_11BIT (0x00000A00U)
#define SPI_DATASIZE_12BIT (0x00000B00U)
#define SPI_DATASIZE_13BIT (0x00000C00U)
#define SPI_DATASIZE_14BIT (0x00000D00U)
#define SPI_DATASIZE_15BIT (0x00000E00U)
#define SPI_DATASIZE_16BIT (0x00000F00U)
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW (0x00000000U)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
*/
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE (0x00000000U)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT (0x00000000U)
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
/**
* @}
*/
/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
* @{
*/
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define SPI_NSS_PULSE_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
#define SPI_FIRSTBIT_MSB (0x00000000U)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
*/
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLE (0x00000000U)
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
*/
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
/** @defgroup SPI_CRC_length SPI CRC Length
* @{
* This parameter can be one of the following values:
* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
* SPI_CRC_LENGTH_8BIT : CRC 8bit
* SPI_CRC_LENGTH_16BIT : CRC 16bit
*/
#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define SPI_CRC_LENGTH_8BIT (0x00000001U)
#define SPI_CRC_LENGTH_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
* @{
* This parameter can be one of the following values:
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
* RXNE event is generated if the FIFO
* level is greater or equal to 1/4(8-bits).
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
* level is greater or equal to 1/2(16 bits). */
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
/**
* @}
*/
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
#define SPI_IT_RXNE SPI_CR2_RXNEIE
#define SPI_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
/**
* @}
*/
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
* @{
*/
#define SPI_FTLVL_EMPTY (0x00000000U)
#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define SPI_FTLVL_HALF_FULL (0x00001000U)
#define SPI_FTLVL_FULL (0x00001800U)
/**
* @}
*/
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
*/
#define SPI_FRLVL_EMPTY (0x00000000U)
#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define SPI_FRLVL_HALF_FULL (0x00000400U)
#define SPI_FRLVL_FULL (0x00000600U)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
/** @brief Reset SPI handle state.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Disable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI handle.
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
* @arg SPI_FLAG_MODF: Mode fault flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
* @arg SPI_FLAG_FRE: Frame format error flag
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the SPI CRCERR pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
/** @brief Clear the SPI MODF pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_modf = 0x00U; \
tmpreg_modf = (__HANDLE__)->Instance->SR; \
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
UNUSED(tmpreg_modf); \
} while(0U)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
} while(0U)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
}while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
/** @brief Set the SPI transmit-only mode.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Set the SPI receive-only mode.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Reset the CRC calculation of the SPI.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
* @arg SPI_FLAG_MODF: Mode fault flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
* @arg SPI_FLAG_FRE: Frame format error flag
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
(__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode
* @retval None
*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
((__MODE__) == SPI_MODE_MASTER))
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Direction Mode.
* This parameter can be a value of @ref SPI_Direction
* @retval None
*/
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
((__MODE__) == SPI_DIRECTION_1LINE))
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
* @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
* @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_1LINE))
/** @brief Checks if SPI Data Size parameter is in allowed range.
* @param __DATASIZE__ specifies the SPI Data Size.
* This parameter can be a value of @ref SPI_Data_Size
* @retval None
*/
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
((__DATASIZE__) == SPI_DATASIZE_4BIT))
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the SPI serial clock steady state.
* This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None
*/
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
((__CPOL__) == SPI_POLARITY_HIGH))
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
* @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase
* @retval None
*/
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
((__NSS__) == SPI_NSS_HARD_INPUT) || \
((__NSS__) == SPI_NSS_HARD_OUTPUT))
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
* This parameter can be a value of @ref SPI_NSSP_Mode
* @retval None
*/
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
* @retval None
*/
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None
*/
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
((__BIT__) == SPI_FIRSTBIT_LSB))
/** @brief Checks if SPI TI mode parameter is in allowed range.
* @param __MODE__ specifies the SPI TI mode.
* This parameter can be a value of @ref SPI_TI_mode
* @retval None
*/
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
((__MODE__) == SPI_TIMODE_ENABLE))
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
* This parameter can be a value of @ref SPI_CRC_Calculation
* @retval None
*/
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
/** @brief Checks if SPI CRC length is in allowed range.
* @param __LENGTH__ specifies the SPI CRC length.
* This parameter can be a value of @ref SPI_CRC_length
* @retval None
*/
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
(((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
* @retval None
*/
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
/**
* @}
*/
/* Include SPI HAL Extended module */
#include "stm32f3xx_hal_spi_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_SPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_spi_ex.h
* @author MCD Application Team
* @brief Header file of SPI HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_SPI_EX_H
#define STM32F3xx_HAL_SPI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup SPIEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPIEx_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/* IO operation functions *****************************************************/
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_SPI_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_sram.h
* @author MCD Application Team
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_SRAM_H
#define STM32F3xx_HAL_SRAM_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_ll_fmc.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup SRAM
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SRAM_Exported_Types SRAM Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
} HAL_SRAM_StateTypeDef;
/**
* @brief SRAM handle Structure definition
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
typedef struct __SRAM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
HAL_LockTypeDef Lock; /*!< SRAM locking object */
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
} SRAM_HandleTypeDef;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SRAM Callback ID enumeration definition
*/
typedef enum
{
HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
*/
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
* @{
*/
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
* @retval None
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
* @{
*/
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_SRAM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_tim_ex.h
* @author MCD Application Team
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_TIM_EX_H
#define STM32F3xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#if defined(TIM1)
#define TIM_TIM1_ADC1_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ADC1_AWD1 (0x00000001U) /*!< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ADC1_AWD2 (0x00000002U) /*!< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ADC1_AWD3 (0x00000003U) /*!< TIM1_ETR is connected to ADC1 AWD3 */
#if defined(ADC4)
#define TIM_TIM1_ADC4_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ADC4_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC4 AWD1 */
#define TIM_TIM1_ADC4_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC4 AWD2 */
#define TIM_TIM1_ADC4_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC4 AWD3 */
#elif defined(ADC2)
#define TIM_TIM1_ADC2_NONE (0x00000000U) /*!< TIM1_ETR is not connected to any AWD (analog watchdog)*/
#define TIM_TIM1_ADC2_AWD1 (0x00000004U) /*!< TIM1_ETR is connected to ADC2 AWD1 */
#define TIM_TIM1_ADC2_AWD2 (0x00000008U) /*!< TIM1_ETR is connected to ADC2 AWD2 */
#define TIM_TIM1_ADC2_AWD3 (0x0000000CU) /*!< TIM1_ETR is connected to ADC2 AWD3 */
#endif /* ADC4 */
#endif /* TIM1 */
#if defined(TIM8)
#define TIM_TIM8_ADC2_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
#define TIM_TIM8_ADC2_AWD1 (0x00000001U) /*!< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ADC2_AWD2 (0x00000002U) /*!< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ADC2_AWD3 (0x00000003U) /*!< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ADC3_NONE (0x00000000U) /*!< TIM8_ETR is not connected to any AWD (analog watchdog) */
#define TIM_TIM8_ADC3_AWD1 (0x00000004U) /*!< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ADC3_AWD2 (0x00000008U) /*!< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ADC3_AWD3 (0x0000000CU) /*!< TIM8_ETR is connected to ADC3 AWD3 */
#endif /* TIM8 */
#if defined(TIM14)
#define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */
#define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */
#define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */
#define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */
#endif /* TIM14 */
#if defined(TIM16)
#define TIM_TIM16_GPIO (0x00000000U) /*!< TIM16 TI1 is connected to GPIO */
#define TIM_TIM16_RTC (0x00000001U) /*!< TIM16 TI1 is connected to RTC_clock */
#define TIM_TIM16_HSE (0x00000002U) /*!< TIM16 TI1 is connected to HSE/32 */
#define TIM_TIM16_MCO (0x00000003U) /*!< TIM16 TI1 is connected to MCO */
#endif /* TIM16 */
#if defined(TIM20)
#define TIM_TIM20_ADC3_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
#define TIM_TIM20_ADC3_AWD1 (0x00000001U) /*!< TIM20_ETR is connected to ADC3 AWD1 */
#define TIM_TIM20_ADC3_AWD2 (0x00000002U) /*!< TIM20_ETR is connected to ADC3 AWD2 */
#define TIM_TIM20_ADC3_AWD3 (0x00000003U) /*!< TIM20_ETR is connected to ADC3 AWD3 */
#define TIM_TIM20_ADC4_NONE (0x00000000U) /*!< TIM20_ETR is not connected to any AWD (analog watchdog) */
#define TIM_TIM20_ADC4_AWD1 (0x00000004U) /*!< TIM20_ETR is connected to ADC4 AWD1 */
#define TIM_TIM20_ADC4_AWD2 (0x00000008U) /*!< TIM20_ETR is connected to ADC4 AWD2 */
#define TIM_TIM20_ADC4_AWD3 (0x0000000CU) /*!< TIM20_ETR is connected to ADC4 AWD3 */
#endif /* TIM20 */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
/**
* @}
*/
/* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#if defined(TIM1) && defined(TIM8) && defined(TIM20) && defined(TIM16)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM20) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#elif defined(TIM1) && defined(TIM8) && defined(TIM16)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM8) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#elif defined(TIM1) && defined(TIM16)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
((((__INSTANCE__) == TIM1) && ((((__REMAP__) & 0xFFFFFFF0U) == 0x00000000U))) \
|| (((__INSTANCE__) == TIM16) && ((((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))))
#elif defined(TIM14)
#define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \
(((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U))
#endif /* TIM1 && TIM8 && TIM20 && TIM16 */
/**
* @}
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
#if defined(TIM_CCR5_CCR5)
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
#endif /* TIM_CCR5_CCR5 */
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions
* @{
*/
/* Extended Callback **********************************************************/
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
#if defined(TIM_BDTR_BK2E)
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
#endif /* TIM_BDTR_BK2E */
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
* @brief Extended Peripheral State functions
* @{
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_tsc.h
* @author MCD Application Team
* @brief Header file of TSC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_TSC_H
#define STM32F3xx_HAL_TSC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup TSC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TSC_Exported_Types TSC Exported Types
* @{
*/
/**
* @brief TSC state structure definition
*/
typedef enum
{
HAL_TSC_STATE_RESET = 0x00UL, /*!< TSC registers have their reset value */
HAL_TSC_STATE_READY = 0x01UL, /*!< TSC registers are initialized or acquisition is completed with success */
HAL_TSC_STATE_BUSY = 0x02UL, /*!< TSC initialization or acquisition is on-going */
HAL_TSC_STATE_ERROR = 0x03UL /*!< Acquisition is completed with max count error */
} HAL_TSC_StateTypeDef;
/**
* @brief TSC group status structure definition
*/
typedef enum
{
TSC_GROUP_ONGOING = 0x00UL, /*!< Acquisition on group is on-going or not started */
TSC_GROUP_COMPLETED = 0x01UL /*!< Acquisition on group is completed with success (no max count error) */
} TSC_GroupStatusTypeDef;
/**
* @brief TSC init structure definition
*/
typedef struct
{
uint32_t CTPulseHighLength; /*!< Charge-transfer high pulse length
This parameter can be a value of @ref TSC_CTPulseHL_Config */
uint32_t CTPulseLowLength; /*!< Charge-transfer low pulse length
This parameter can be a value of @ref TSC_CTPulseLL_Config */
FunctionalState SpreadSpectrum; /*!< Spread spectrum activation
This parameter can be set to ENABLE or DISABLE. */
uint32_t SpreadSpectrumDeviation; /*!< Spread spectrum deviation
This parameter must be a number between Min_Data = 0 and Max_Data = 127 */
uint32_t SpreadSpectrumPrescaler; /*!< Spread spectrum prescaler
This parameter can be a value of @ref TSC_SpreadSpec_Prescaler */
uint32_t PulseGeneratorPrescaler; /*!< Pulse generator prescaler
This parameter can be a value of @ref TSC_PulseGenerator_Prescaler */
uint32_t MaxCountValue; /*!< Max count value
This parameter can be a value of @ref TSC_MaxCount_Value */
uint32_t IODefaultMode; /*!< IO default mode
This parameter can be a value of @ref TSC_IO_Default_Mode */
uint32_t SynchroPinPolarity; /*!< Synchro pin polarity
This parameter can be a value of @ref TSC_Synchro_Pin_Polarity */
uint32_t AcquisitionMode; /*!< Acquisition mode
This parameter can be a value of @ref TSC_Acquisition_Mode */
FunctionalState MaxCountInterrupt;/*!< Max count interrupt activation
This parameter can be set to ENABLE or DISABLE. */
uint32_t ChannelIOs; /*!< Channel IOs mask */
uint32_t ShieldIOs; /*!< Shield IOs mask */
uint32_t SamplingIOs; /*!< Sampling IOs mask */
} TSC_InitTypeDef;
/**
* @brief TSC IOs configuration structure definition
*/
typedef struct
{
uint32_t ChannelIOs; /*!< Channel IOs mask */
uint32_t ShieldIOs; /*!< Shield IOs mask */
uint32_t SamplingIOs; /*!< Sampling IOs mask */
} TSC_IOConfigTypeDef;
/**
* @brief TSC handle Structure definition
*/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
typedef struct __TSC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
{
TSC_TypeDef *Instance; /*!< Register base address */
TSC_InitTypeDef Init; /*!< Initialization parameters */
__IO HAL_TSC_StateTypeDef State; /*!< Peripheral state */
HAL_LockTypeDef Lock; /*!< Lock feature */
__IO uint32_t ErrorCode; /*!< TSC Error code */
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Conversion complete callback */
void (* ErrorCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Error callback */
void (* MspInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp Init callback */
void (* MspDeInitCallback)(struct __TSC_HandleTypeDef *htsc); /*!< TSC Msp DeInit callback */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
} TSC_HandleTypeDef;
enum
{
TSC_GROUP1_IDX = 0x00UL,
TSC_GROUP2_IDX,
TSC_GROUP3_IDX,
TSC_GROUP4_IDX,
TSC_GROUP5_IDX,
TSC_GROUP6_IDX,
TSC_GROUP7_IDX,
TSC_GROUP8_IDX,
TSC_NB_OF_GROUPS
};
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL TSC Callback ID enumeration definition
*/
typedef enum
{
HAL_TSC_CONV_COMPLETE_CB_ID = 0x00UL, /*!< TSC Conversion completed callback ID */
HAL_TSC_ERROR_CB_ID = 0x01UL, /*!< TSC Error callback ID */
HAL_TSC_MSPINIT_CB_ID = 0x02UL, /*!< TSC Msp Init callback ID */
HAL_TSC_MSPDEINIT_CB_ID = 0x03UL /*!< TSC Msp DeInit callback ID */
} HAL_TSC_CallbackIDTypeDef;
/**
* @brief HAL TSC Callback pointer definition
*/
typedef void (*pTSC_CallbackTypeDef)(TSC_HandleTypeDef *htsc); /*!< pointer to an TSC callback function */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TSC_Exported_Constants TSC Exported Constants
* @{
*/
/** @defgroup TSC_Error_Code_definition TSC Error Code definition
* @brief TSC Error Code definition
* @{
*/
#define HAL_TSC_ERROR_NONE 0x00000000UL /*!< No error */
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
#define HAL_TSC_ERROR_INVALID_CALLBACK 0x00000001UL /*!< Invalid Callback error */
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup TSC_CTPulseHL_Config CTPulse High Length
* @{
*/
#define TSC_CTPH_1CYCLE 0x00000000UL /*!< Charge transfer pulse high during 1 cycle (PGCLK) */
#define TSC_CTPH_2CYCLES TSC_CR_CTPH_0 /*!< Charge transfer pulse high during 2 cycles (PGCLK) */
#define TSC_CTPH_3CYCLES TSC_CR_CTPH_1 /*!< Charge transfer pulse high during 3 cycles (PGCLK) */
#define TSC_CTPH_4CYCLES (TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 4 cycles (PGCLK) */
#define TSC_CTPH_5CYCLES TSC_CR_CTPH_2 /*!< Charge transfer pulse high during 5 cycles (PGCLK) */
#define TSC_CTPH_6CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 6 cycles (PGCLK) */
#define TSC_CTPH_7CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 7 cycles (PGCLK) */
#define TSC_CTPH_8CYCLES (TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 8 cycles (PGCLK) */
#define TSC_CTPH_9CYCLES TSC_CR_CTPH_3 /*!< Charge transfer pulse high during 9 cycles (PGCLK) */
#define TSC_CTPH_10CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 10 cycles (PGCLK) */
#define TSC_CTPH_11CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 11 cycles (PGCLK) */
#define TSC_CTPH_12CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 12 cycles (PGCLK) */
#define TSC_CTPH_13CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2) /*!< Charge transfer pulse high during 13 cycles (PGCLK) */
#define TSC_CTPH_14CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 14 cycles (PGCLK) */
#define TSC_CTPH_15CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1) /*!< Charge transfer pulse high during 15 cycles (PGCLK) */
#define TSC_CTPH_16CYCLES (TSC_CR_CTPH_3 | TSC_CR_CTPH_2 | TSC_CR_CTPH_1 | TSC_CR_CTPH_0) /*!< Charge transfer pulse high during 16 cycles (PGCLK) */
/**
* @}
*/
/** @defgroup TSC_CTPulseLL_Config CTPulse Low Length
* @{
*/
#define TSC_CTPL_1CYCLE 0x00000000UL /*!< Charge transfer pulse low during 1 cycle (PGCLK) */
#define TSC_CTPL_2CYCLES TSC_CR_CTPL_0 /*!< Charge transfer pulse low during 2 cycles (PGCLK) */
#define TSC_CTPL_3CYCLES TSC_CR_CTPL_1 /*!< Charge transfer pulse low during 3 cycles (PGCLK) */
#define TSC_CTPL_4CYCLES (TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 4 cycles (PGCLK) */
#define TSC_CTPL_5CYCLES TSC_CR_CTPL_2 /*!< Charge transfer pulse low during 5 cycles (PGCLK) */
#define TSC_CTPL_6CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 6 cycles (PGCLK) */
#define TSC_CTPL_7CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 7 cycles (PGCLK) */
#define TSC_CTPL_8CYCLES (TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 8 cycles (PGCLK) */
#define TSC_CTPL_9CYCLES TSC_CR_CTPL_3 /*!< Charge transfer pulse low during 9 cycles (PGCLK) */
#define TSC_CTPL_10CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 10 cycles (PGCLK) */
#define TSC_CTPL_11CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 11 cycles (PGCLK) */
#define TSC_CTPL_12CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 12 cycles (PGCLK) */
#define TSC_CTPL_13CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2) /*!< Charge transfer pulse low during 13 cycles (PGCLK) */
#define TSC_CTPL_14CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 14 cycles (PGCLK) */
#define TSC_CTPL_15CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1) /*!< Charge transfer pulse low during 15 cycles (PGCLK) */
#define TSC_CTPL_16CYCLES (TSC_CR_CTPL_3 | TSC_CR_CTPL_2 | TSC_CR_CTPL_1 | TSC_CR_CTPL_0) /*!< Charge transfer pulse low during 16 cycles (PGCLK) */
/**
* @}
*/
/** @defgroup TSC_SpreadSpec_Prescaler Spread Spectrum Prescaler
* @{
*/
#define TSC_SS_PRESC_DIV1 0x00000000UL /*!< Spread Spectrum Prescaler Div1 */
#define TSC_SS_PRESC_DIV2 TSC_CR_SSPSC /*!< Spread Spectrum Prescaler Div2 */
/**
* @}
*/
/** @defgroup TSC_PulseGenerator_Prescaler Pulse Generator Prescaler
* @{
*/
#define TSC_PG_PRESC_DIV1 0x00000000UL /*!< Pulse Generator HCLK Div1 */
#define TSC_PG_PRESC_DIV2 TSC_CR_PGPSC_0 /*!< Pulse Generator HCLK Div2 */
#define TSC_PG_PRESC_DIV4 TSC_CR_PGPSC_1 /*!< Pulse Generator HCLK Div4 */
#define TSC_PG_PRESC_DIV8 (TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div8 */
#define TSC_PG_PRESC_DIV16 TSC_CR_PGPSC_2 /*!< Pulse Generator HCLK Div16 */
#define TSC_PG_PRESC_DIV32 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div32 */
#define TSC_PG_PRESC_DIV64 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1) /*!< Pulse Generator HCLK Div64 */
#define TSC_PG_PRESC_DIV128 (TSC_CR_PGPSC_2 | TSC_CR_PGPSC_1 | TSC_CR_PGPSC_0) /*!< Pulse Generator HCLK Div128 */
/**
* @}
*/
/** @defgroup TSC_MaxCount_Value Max Count Value
* @{
*/
#define TSC_MCV_255 0x00000000UL /*!< 255 maximum number of charge transfer pulses */
#define TSC_MCV_511 TSC_CR_MCV_0 /*!< 511 maximum number of charge transfer pulses */
#define TSC_MCV_1023 TSC_CR_MCV_1 /*!< 1023 maximum number of charge transfer pulses */
#define TSC_MCV_2047 (TSC_CR_MCV_1 | TSC_CR_MCV_0) /*!< 2047 maximum number of charge transfer pulses */
#define TSC_MCV_4095 TSC_CR_MCV_2 /*!< 4095 maximum number of charge transfer pulses */
#define TSC_MCV_8191 (TSC_CR_MCV_2 | TSC_CR_MCV_0) /*!< 8191 maximum number of charge transfer pulses */
#define TSC_MCV_16383 (TSC_CR_MCV_2 | TSC_CR_MCV_1) /*!< 16383 maximum number of charge transfer pulses */
/**
* @}
*/
/** @defgroup TSC_IO_Default_Mode IO Default Mode
* @{
*/
#define TSC_IODEF_OUT_PP_LOW 0x00000000UL /*!< I/Os are forced to output push-pull low */
#define TSC_IODEF_IN_FLOAT TSC_CR_IODEF /*!< I/Os are in input floating */
/**
* @}
*/
/** @defgroup TSC_Synchro_Pin_Polarity Synchro Pin Polarity
* @{
*/
#define TSC_SYNC_POLARITY_FALLING 0x00000000UL /*!< Falling edge only */
#define TSC_SYNC_POLARITY_RISING TSC_CR_SYNCPOL /*!< Rising edge and high level */
/**
* @}
*/
/** @defgroup TSC_Acquisition_Mode Acquisition Mode
* @{
*/
#define TSC_ACQ_MODE_NORMAL 0x00000000UL /*!< Normal acquisition mode (acquisition starts as soon as START bit is set) */
#define TSC_ACQ_MODE_SYNCHRO TSC_CR_AM /*!< Synchronized acquisition mode (acquisition starts if START bit is set and when the selected signal is detected on the SYNC input pin) */
/**
* @}
*/
/** @defgroup TSC_interrupts_definition Interrupts definition
* @{
*/
#define TSC_IT_EOA TSC_IER_EOAIE /*!< End of acquisition interrupt enable */
#define TSC_IT_MCE TSC_IER_MCEIE /*!< Max count error interrupt enable */
/**
* @}
*/
/** @defgroup TSC_flags_definition Flags definition
* @{
*/
#define TSC_FLAG_EOA TSC_ISR_EOAF /*!< End of acquisition flag */
#define TSC_FLAG_MCE TSC_ISR_MCEF /*!< Max count error flag */
/**
* @}
*/
/** @defgroup TSC_Group_definition Group definition
* @{
*/
#define TSC_GROUP1 (0x1UL << TSC_GROUP1_IDX)
#define TSC_GROUP2 (0x1UL << TSC_GROUP2_IDX)
#define TSC_GROUP3 (0x1UL << TSC_GROUP3_IDX)
#define TSC_GROUP4 (0x1UL << TSC_GROUP4_IDX)
#define TSC_GROUP5 (0x1UL << TSC_GROUP5_IDX)
#define TSC_GROUP6 (0x1UL << TSC_GROUP6_IDX)
#define TSC_GROUP7 (0x1UL << TSC_GROUP7_IDX)
#define TSC_GROUP8 (0x1UL << TSC_GROUP8_IDX)
#define TSC_GROUP1_IO1 TSC_IOCCR_G1_IO1 /*!< TSC Group1 IO1 */
#define TSC_GROUP1_IO2 TSC_IOCCR_G1_IO2 /*!< TSC Group1 IO2 */
#define TSC_GROUP1_IO3 TSC_IOCCR_G1_IO3 /*!< TSC Group1 IO3 */
#define TSC_GROUP1_IO4 TSC_IOCCR_G1_IO4 /*!< TSC Group1 IO4 */
#define TSC_GROUP2_IO1 TSC_IOCCR_G2_IO1 /*!< TSC Group2 IO1 */
#define TSC_GROUP2_IO2 TSC_IOCCR_G2_IO2 /*!< TSC Group2 IO2 */
#define TSC_GROUP2_IO3 TSC_IOCCR_G2_IO3 /*!< TSC Group2 IO3 */
#define TSC_GROUP2_IO4 TSC_IOCCR_G2_IO4 /*!< TSC Group2 IO4 */
#define TSC_GROUP3_IO1 TSC_IOCCR_G3_IO1 /*!< TSC Group3 IO1 */
#define TSC_GROUP3_IO2 TSC_IOCCR_G3_IO2 /*!< TSC Group3 IO2 */
#define TSC_GROUP3_IO3 TSC_IOCCR_G3_IO3 /*!< TSC Group3 IO3 */
#define TSC_GROUP3_IO4 TSC_IOCCR_G3_IO4 /*!< TSC Group3 IO4 */
#define TSC_GROUP4_IO1 TSC_IOCCR_G4_IO1 /*!< TSC Group4 IO1 */
#define TSC_GROUP4_IO2 TSC_IOCCR_G4_IO2 /*!< TSC Group4 IO2 */
#define TSC_GROUP4_IO3 TSC_IOCCR_G4_IO3 /*!< TSC Group4 IO3 */
#define TSC_GROUP4_IO4 TSC_IOCCR_G4_IO4 /*!< TSC Group4 IO4 */
#define TSC_GROUP5_IO1 TSC_IOCCR_G5_IO1 /*!< TSC Group5 IO1 */
#define TSC_GROUP5_IO2 TSC_IOCCR_G5_IO2 /*!< TSC Group5 IO2 */
#define TSC_GROUP5_IO3 TSC_IOCCR_G5_IO3 /*!< TSC Group5 IO3 */
#define TSC_GROUP5_IO4 TSC_IOCCR_G5_IO4 /*!< TSC Group5 IO4 */
#define TSC_GROUP6_IO1 TSC_IOCCR_G6_IO1 /*!< TSC Group6 IO1 */
#define TSC_GROUP6_IO2 TSC_IOCCR_G6_IO2 /*!< TSC Group6 IO2 */
#define TSC_GROUP6_IO3 TSC_IOCCR_G6_IO3 /*!< TSC Group6 IO3 */
#define TSC_GROUP6_IO4 TSC_IOCCR_G6_IO4 /*!< TSC Group6 IO4 */
#define TSC_GROUP7_IO1 TSC_IOCCR_G7_IO1 /*!< TSC Group7 IO1 */
#define TSC_GROUP7_IO2 TSC_IOCCR_G7_IO2 /*!< TSC Group7 IO2 */
#define TSC_GROUP7_IO3 TSC_IOCCR_G7_IO3 /*!< TSC Group7 IO3 */
#define TSC_GROUP7_IO4 TSC_IOCCR_G7_IO4 /*!< TSC Group7 IO4 */
#define TSC_GROUP8_IO1 TSC_IOCCR_G8_IO1 /*!< TSC Group8 IO1 */
#define TSC_GROUP8_IO2 TSC_IOCCR_G8_IO2 /*!< TSC Group8 IO2 */
#define TSC_GROUP8_IO3 TSC_IOCCR_G8_IO3 /*!< TSC Group8 IO3 */
#define TSC_GROUP8_IO4 TSC_IOCCR_G8_IO4 /*!< TSC Group8 IO4 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TSC_Exported_Macros TSC Exported Macros
* @{
*/
/** @brief Reset TSC handle state.
* @param __HANDLE__ TSC handle
* @retval None
*/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_TSC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TSC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TSC_STATE_RESET)
#endif /* (USE_HAL_TSC_REGISTER_CALLBACKS == 1) */
/**
* @brief Enable the TSC peripheral.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_TSCE)
/**
* @brief Disable the TSC peripheral.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_TSCE))
/**
* @brief Start acquisition.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_START_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_START)
/**
* @brief Stop acquisition.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_STOP_ACQ(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_START))
/**
* @brief Set IO default mode to output push-pull low.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_IODEF_OUTPPLOW(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_IODEF))
/**
* @brief Set IO default mode to input floating.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_IODEF_INFLOAT(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_IODEF)
/**
* @brief Set synchronization polarity to falling edge.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_SYNC_POL_FALL(__HANDLE__) ((__HANDLE__)->Instance->CR &= (~TSC_CR_SYNCPOL))
/**
* @brief Set synchronization polarity to rising edge and high level.
* @param __HANDLE__ TSC handle
* @retval None
*/
#define __HAL_TSC_SET_SYNC_POL_RISE_HIGH(__HANDLE__) ((__HANDLE__)->Instance->CR |= TSC_CR_SYNCPOL)
/**
* @brief Enable TSC interrupt.
* @param __HANDLE__ TSC handle
* @param __INTERRUPT__ TSC interrupt
* @retval None
*/
#define __HAL_TSC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disable TSC interrupt.
* @param __HANDLE__ TSC handle
* @param __INTERRUPT__ TSC interrupt
* @retval None
*/
#define __HAL_TSC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Check whether the specified TSC interrupt source is enabled or not.
* @param __HANDLE__ TSC Handle
* @param __INTERRUPT__ TSC interrupt
* @retval SET or RESET
*/
#define __HAL_TSC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET :\
RESET)
/**
* @brief Check whether the specified TSC flag is set or not.
* @param __HANDLE__ TSC handle
* @param __FLAG__ TSC flag
* @retval SET or RESET
*/
#define __HAL_TSC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR\
& (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/**
* @brief Clear the TSC's pending flag.
* @param __HANDLE__ TSC handle
* @param __FLAG__ TSC flag
* @retval None
*/
#define __HAL_TSC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_ENABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR |= (__GX_IOY_MASK__))
/**
* @brief Disable schmitt trigger hysteresis on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_DISABLE_HYSTERESIS(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOHCR\
&= (~(__GX_IOY_MASK__)))
/**
* @brief Open analog switch on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_OPEN_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR\
&= (~(__GX_IOY_MASK__)))
/**
* @brief Close analog switch on a group of IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_CLOSE_ANALOG_SWITCH(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOASCR |= (__GX_IOY_MASK__))
/**
* @brief Enable a group of IOs in channel mode.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_ENABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR |= (__GX_IOY_MASK__))
/**
* @brief Disable a group of channel IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_DISABLE_CHANNEL(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOCCR\
&= (~(__GX_IOY_MASK__)))
/**
* @brief Enable a group of IOs in sampling mode.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_ENABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR |= (__GX_IOY_MASK__))
/**
* @brief Disable a group of sampling IOs.
* @param __HANDLE__ TSC handle
* @param __GX_IOY_MASK__ IOs mask
* @retval None
*/
#define __HAL_TSC_DISABLE_SAMPLING(__HANDLE__, __GX_IOY_MASK__) ((__HANDLE__)->Instance->IOSCR &= (~(__GX_IOY_MASK__)))
/**
* @brief Enable acquisition groups.
* @param __HANDLE__ TSC handle
* @param __GX_MASK__ Groups mask
* @retval None
*/
#define __HAL_TSC_ENABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR |= (__GX_MASK__))
/**
* @brief Disable acquisition groups.
* @param __HANDLE__ TSC handle
* @param __GX_MASK__ Groups mask
* @retval None
*/
#define __HAL_TSC_DISABLE_GROUP(__HANDLE__, __GX_MASK__) ((__HANDLE__)->Instance->IOGCSR &= (~(__GX_MASK__)))
/** @brief Gets acquisition group status.
* @param __HANDLE__ TSC Handle
* @param __GX_INDEX__ Group index
* @retval SET or RESET
*/
#define __HAL_TSC_GET_GROUP_STATUS(__HANDLE__, __GX_INDEX__) \
((((__HANDLE__)->Instance->IOGCSR & (uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) == \
(uint32_t)(1UL << (((__GX_INDEX__) & 0xFUL) + 16UL))) ? TSC_GROUP_COMPLETED : TSC_GROUP_ONGOING)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup TSC_Private_Macros TSC Private Macros
* @{
*/
#define IS_TSC_CTPH(__VALUE__) (((__VALUE__) == TSC_CTPH_1CYCLE) || \
((__VALUE__) == TSC_CTPH_2CYCLES) || \
((__VALUE__) == TSC_CTPH_3CYCLES) || \
((__VALUE__) == TSC_CTPH_4CYCLES) || \
((__VALUE__) == TSC_CTPH_5CYCLES) || \
((__VALUE__) == TSC_CTPH_6CYCLES) || \
((__VALUE__) == TSC_CTPH_7CYCLES) || \
((__VALUE__) == TSC_CTPH_8CYCLES) || \
((__VALUE__) == TSC_CTPH_9CYCLES) || \
((__VALUE__) == TSC_CTPH_10CYCLES) || \
((__VALUE__) == TSC_CTPH_11CYCLES) || \
((__VALUE__) == TSC_CTPH_12CYCLES) || \
((__VALUE__) == TSC_CTPH_13CYCLES) || \
((__VALUE__) == TSC_CTPH_14CYCLES) || \
((__VALUE__) == TSC_CTPH_15CYCLES) || \
((__VALUE__) == TSC_CTPH_16CYCLES))
#define IS_TSC_CTPL(__VALUE__) (((__VALUE__) == TSC_CTPL_1CYCLE) || \
((__VALUE__) == TSC_CTPL_2CYCLES) || \
((__VALUE__) == TSC_CTPL_3CYCLES) || \
((__VALUE__) == TSC_CTPL_4CYCLES) || \
((__VALUE__) == TSC_CTPL_5CYCLES) || \
((__VALUE__) == TSC_CTPL_6CYCLES) || \
((__VALUE__) == TSC_CTPL_7CYCLES) || \
((__VALUE__) == TSC_CTPL_8CYCLES) || \
((__VALUE__) == TSC_CTPL_9CYCLES) || \
((__VALUE__) == TSC_CTPL_10CYCLES) || \
((__VALUE__) == TSC_CTPL_11CYCLES) || \
((__VALUE__) == TSC_CTPL_12CYCLES) || \
((__VALUE__) == TSC_CTPL_13CYCLES) || \
((__VALUE__) == TSC_CTPL_14CYCLES) || \
((__VALUE__) == TSC_CTPL_15CYCLES) || \
((__VALUE__) == TSC_CTPL_16CYCLES))
#define IS_TSC_SS(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
|| ((FunctionalState)(__VALUE__) == ENABLE))
#define IS_TSC_SSD(__VALUE__) (((__VALUE__) == 0UL) || (((__VALUE__) > 0UL) && ((__VALUE__) < 128UL)))
#define IS_TSC_SS_PRESC(__VALUE__) (((__VALUE__) == TSC_SS_PRESC_DIV1) || ((__VALUE__) == TSC_SS_PRESC_DIV2))
#define IS_TSC_PG_PRESC(__VALUE__) (((__VALUE__) == TSC_PG_PRESC_DIV1) || \
((__VALUE__) == TSC_PG_PRESC_DIV2) || \
((__VALUE__) == TSC_PG_PRESC_DIV4) || \
((__VALUE__) == TSC_PG_PRESC_DIV8) || \
((__VALUE__) == TSC_PG_PRESC_DIV16) || \
((__VALUE__) == TSC_PG_PRESC_DIV32) || \
((__VALUE__) == TSC_PG_PRESC_DIV64) || \
((__VALUE__) == TSC_PG_PRESC_DIV128))
#define IS_TSC_PG_PRESC_VS_CTPL(__PGPSC__, __CTPL__) ((((__PGPSC__) == TSC_PG_PRESC_DIV1) && \
((__CTPL__) > TSC_CTPL_2CYCLES)) || \
(((__PGPSC__) == TSC_PG_PRESC_DIV2) && \
((__CTPL__) > TSC_CTPL_1CYCLE)) || \
(((__PGPSC__) > TSC_PG_PRESC_DIV2) && \
(((__CTPL__) == TSC_CTPL_1CYCLE) || \
((__CTPL__) > TSC_CTPL_1CYCLE))))
#define IS_TSC_MCV(__VALUE__) (((__VALUE__) == TSC_MCV_255) || \
((__VALUE__) == TSC_MCV_511) || \
((__VALUE__) == TSC_MCV_1023) || \
((__VALUE__) == TSC_MCV_2047) || \
((__VALUE__) == TSC_MCV_4095) || \
((__VALUE__) == TSC_MCV_8191) || \
((__VALUE__) == TSC_MCV_16383))
#define IS_TSC_IODEF(__VALUE__) (((__VALUE__) == TSC_IODEF_OUT_PP_LOW) || ((__VALUE__) == TSC_IODEF_IN_FLOAT))
#define IS_TSC_SYNC_POL(__VALUE__) (((__VALUE__) == TSC_SYNC_POLARITY_FALLING)\
|| ((__VALUE__) == TSC_SYNC_POLARITY_RISING))
#define IS_TSC_ACQ_MODE(__VALUE__) (((__VALUE__) == TSC_ACQ_MODE_NORMAL) || ((__VALUE__) == TSC_ACQ_MODE_SYNCHRO))
#define IS_TSC_MCE_IT(__VALUE__) (((FunctionalState)(__VALUE__) == DISABLE)\
|| ((FunctionalState)(__VALUE__) == ENABLE))
#define IS_TSC_GROUP_INDEX(__VALUE__) (((__VALUE__) == 0UL)\
|| (((__VALUE__) > 0UL) && ((__VALUE__) < (uint32_t)TSC_NB_OF_GROUPS)))
#define IS_TSC_GROUP(__VALUE__) (((__VALUE__) == 0UL) ||\
(((__VALUE__) & TSC_GROUP1_IO1) == TSC_GROUP1_IO1) ||\
(((__VALUE__) & TSC_GROUP1_IO2) == TSC_GROUP1_IO2) ||\
(((__VALUE__) & TSC_GROUP1_IO3) == TSC_GROUP1_IO3) ||\
(((__VALUE__) & TSC_GROUP1_IO4) == TSC_GROUP1_IO4) ||\
(((__VALUE__) & TSC_GROUP2_IO1) == TSC_GROUP2_IO1) ||\
(((__VALUE__) & TSC_GROUP2_IO2) == TSC_GROUP2_IO2) ||\
(((__VALUE__) & TSC_GROUP2_IO3) == TSC_GROUP2_IO3) ||\
(((__VALUE__) & TSC_GROUP2_IO4) == TSC_GROUP2_IO4) ||\
(((__VALUE__) & TSC_GROUP3_IO1) == TSC_GROUP3_IO1) ||\
(((__VALUE__) & TSC_GROUP3_IO2) == TSC_GROUP3_IO2) ||\
(((__VALUE__) & TSC_GROUP3_IO3) == TSC_GROUP3_IO3) ||\
(((__VALUE__) & TSC_GROUP3_IO4) == TSC_GROUP3_IO4) ||\
(((__VALUE__) & TSC_GROUP4_IO1) == TSC_GROUP4_IO1) ||\
(((__VALUE__) & TSC_GROUP4_IO2) == TSC_GROUP4_IO2) ||\
(((__VALUE__) & TSC_GROUP4_IO3) == TSC_GROUP4_IO3) ||\
(((__VALUE__) & TSC_GROUP4_IO4) == TSC_GROUP4_IO4) ||\
(((__VALUE__) & TSC_GROUP5_IO1) == TSC_GROUP5_IO1) ||\
(((__VALUE__) & TSC_GROUP5_IO2) == TSC_GROUP5_IO2) ||\
(((__VALUE__) & TSC_GROUP5_IO3) == TSC_GROUP5_IO3) ||\
(((__VALUE__) & TSC_GROUP5_IO4) == TSC_GROUP5_IO4) ||\
(((__VALUE__) & TSC_GROUP6_IO1) == TSC_GROUP6_IO1) ||\
(((__VALUE__) & TSC_GROUP6_IO2) == TSC_GROUP6_IO2) ||\
(((__VALUE__) & TSC_GROUP6_IO3) == TSC_GROUP6_IO3) ||\
(((__VALUE__) & TSC_GROUP6_IO4) == TSC_GROUP6_IO4) ||\
(((__VALUE__) & TSC_GROUP7_IO1) == TSC_GROUP7_IO1) ||\
(((__VALUE__) & TSC_GROUP7_IO2) == TSC_GROUP7_IO2) ||\
(((__VALUE__) & TSC_GROUP7_IO3) == TSC_GROUP7_IO3) ||\
(((__VALUE__) & TSC_GROUP7_IO4) == TSC_GROUP7_IO4) ||\
(((__VALUE__) & TSC_GROUP8_IO1) == TSC_GROUP8_IO1) ||\
(((__VALUE__) & TSC_GROUP8_IO2) == TSC_GROUP8_IO2) ||\
(((__VALUE__) & TSC_GROUP8_IO3) == TSC_GROUP8_IO3) ||\
(((__VALUE__) & TSC_GROUP8_IO4) == TSC_GROUP8_IO4))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TSC_Exported_Functions
* @{
*/
/** @addtogroup TSC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef *htsc);
void HAL_TSC_MspInit(TSC_HandleTypeDef *htsc);
void HAL_TSC_MspDeInit(TSC_HandleTypeDef *htsc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TSC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TSC_RegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID,
pTSC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TSC_UnRegisterCallback(TSC_HandleTypeDef *htsc, HAL_TSC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TSC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup TSC_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_TSC_Start(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Start_IT(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Stop(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_Stop_IT(TSC_HandleTypeDef *htsc);
HAL_StatusTypeDef HAL_TSC_PollForAcquisition(TSC_HandleTypeDef *htsc);
TSC_GroupStatusTypeDef HAL_TSC_GroupGetStatus(TSC_HandleTypeDef *htsc, uint32_t gx_index);
uint32_t HAL_TSC_GroupGetValue(TSC_HandleTypeDef *htsc, uint32_t gx_index);
/**
* @}
*/
/** @addtogroup TSC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_TSC_IOConfig(TSC_HandleTypeDef *htsc, TSC_IOConfigTypeDef *config);
HAL_StatusTypeDef HAL_TSC_IODischarge(TSC_HandleTypeDef *htsc, FunctionalState choice);
/**
* @}
*/
/** @addtogroup TSC_Exported_Functions_Group4 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_TSC_StateTypeDef HAL_TSC_GetState(TSC_HandleTypeDef *htsc);
/**
* @}
*/
/** @addtogroup TSC_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* TSC IRQHandler and Callbacks used in Interrupt mode */
void HAL_TSC_IRQHandler(TSC_HandleTypeDef *htsc);
void HAL_TSC_ConvCpltCallback(TSC_HandleTypeDef *htsc);
void HAL_TSC_ErrorCallback(TSC_HandleTypeDef *htsc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_TSC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_uart_ex.h
* @author MCD Application Team
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_UART_EX_H
#define STM32F3xx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#if defined(USART_CR1_M1)
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#endif /* USART_CR1_M1 */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#if defined (USART_CR1_M0)
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
#else
#define UART_WORDLENGTH_9B USART_CR1_M /*!< 9-bit long UART frame */
#endif /* USART_CR1_M0 */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
* @{
*/
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || STM32F302xC || STM32F303xC || STM32F358xx */
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#if defined (USART_CR1_M1)
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
#else
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
#endif /* USART_CR1_M1 */
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#if defined (USART_CR1_M1)
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
#else
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
#endif /* USART_CR1_M1 */
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__ UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_UART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_usart.h
* @author MCD Application Team
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_USART_H
#define STM32F3xx_HAL_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types USART Exported Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
Baud Rate Register[15:4] = ((2 * fclk_pres) /
((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
Baud Rate Register[2:0] = (((2 * fclk_pres) /
((huart->Init.BaudRate)))[3:0]) >> 1
where fclk_pres is the USART input clock frequency
@note Oversampling by 8 is systematically applied to
achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode. */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity. */
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase. */
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit. */
} USART_InitTypeDef;
/**
* @brief HAL USART State structures definition
*/
typedef enum
{
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
} HAL_USART_StateTypeDef;
/**
* @brief USART clock sources definitions
*/
typedef enum
{
USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
} USART_ClockSourceTypeDef;
/**
* @brief USART handle Structure definition
*/
typedef struct __USART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< USART registers base address */
USART_InitTypeDef Init; /*!< USART communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
uint16_t TxXferSize; /*!< USART Tx Transfer size */
__IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
uint16_t RxXferSize; /*!< USART Rx Transfer size */
__IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
uint16_t Mask; /*!< USART Rx RDR register mask */
void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_USART_StateTypeDef State; /*!< USART communication state */
__IO uint32_t ErrorCode; /*!< USART Error code */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
} USART_HandleTypeDef;
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL USART Callback ID enumeration definition
*/
typedef enum
{
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
} HAL_USART_CallbackIDTypeDef;
/**
* @brief HAL USART Callback pointer definition
*/
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */
#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */
#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */
/**
* @}
*/
/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE 0x00000000U /*!< No parity */
#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
/** @defgroup USART_Mode USART Mode
* @{
*/
#define USART_MODE_RX USART_CR1_RE /*!< RX mode */
#define USART_MODE_TX USART_CR1_TE /*!< TX mode */
#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
/** @defgroup USART_Clock USART Clock
* @{
*/
#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */
#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */
/**
* @}
*/
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */
#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */
/**
* @}
*/
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */
#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */
/**
* @}
*/
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */
#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
/** @defgroup USART_Request_Parameters USART Request Parameters
* @{
*/
#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
/** @defgroup USART_Flags USART Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
#define USART_FLAG_CTS USART_ISR_CTS /*!< USART clear to send flag */
#define USART_FLAG_CTSIF USART_ISR_CTSIF /*!< USART clear to send interrupt flag */
#define USART_FLAG_LBDF USART_ISR_LBDF /*!< USART LIN break detection flag */
#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
/**
* @}
*/
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define USART_IT_PE 0x0028U /*!< USART parity error interruption */
#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
#define USART_IT_ERR 0x0060U /*!< USART error interruption */
#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
#define USART_IT_NE 0x0200U /*!< USART noise error interruption */
#define USART_IT_FE 0x0100U /*!< USART frame error interruption */
/**
* @}
*/
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
* @{
*/
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
* @{
*/
#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */
#define USART_CR_MASK 0x00E0U /*!< USART control register mask */
#define USART_CR_POS 5U /*!< USART control register position */
#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */
#define USART_ISR_POS 8U /*!< USART ISR register position */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup USART_Exported_Macros USART Exported Macros
* @{
*/
/** @brief Reset USART handle state.
* @param __HANDLE__ USART handle.
* @retval None
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** @brief Flush the USART Data registers
* @param __HANDLE__ specifies the USART Handle.
*/
#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
* @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref USART_FLAG_BUSY Busy flag
* @arg @ref USART_FLAG_CTS CTS Change flag
* @arg @ref USART_FLAG_TXE Transmit data register empty flag
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
* @arg @ref USART_FLAG_FE Framing Error flag
* @arg @ref USART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified USART pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_CTSF
* @retval None
*/
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the USART PE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
/** @brief Clear the USART NE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
/** @brief Clear the USART ORE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
/** @brief Clear the USART IDLE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
/** @brief Enable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_ORE OverRun Error interrupt
* @arg @ref USART_IT_NE Noise Error interrupt
* @arg @ref USART_IT_FE Framing Error interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_ORE OverRun Error interrupt
* @arg @ref USART_IT_NE Noise Error interrupt
* @arg @ref USART_IT_FE Framing Error interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
(__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U <<\
(((uint16_t)(__INTERRUPT__)) &\
USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt.
* This parameter can be one of the following values:
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_CTSF CTS Interrupt Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific USART request flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __REQ__ specifies the request flag to set.
* This parameter can be one of the following values:
* @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
/** @brief Enable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup USART_Private_Macros USART Private Macros
* @{
*/
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
* @retval Division result
*/
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Check USART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on F3 (i.e. 72 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 9000000U)
/**
* @brief Ensure that USART frame number of stop bits is valid.
* @param __STOPBITS__ USART frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
((__STOPBITS__) == USART_STOPBITS_1) || \
((__STOPBITS__) == USART_STOPBITS_1_5) || \
((__STOPBITS__) == USART_STOPBITS_2))
/**
* @brief Ensure that USART frame parity is valid.
* @param __PARITY__ USART frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
((__PARITY__) == USART_PARITY_EVEN) || \
((__PARITY__) == USART_PARITY_ODD))
/**
* @brief Ensure that USART communication mode is valid.
* @param __MODE__ USART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
*/
#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
((__CLOCK__) == USART_CLOCK_ENABLE))
/**
* @brief Ensure that USART frame polarity is valid.
* @param __CPOL__ USART frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
/**
* @brief Ensure that USART frame phase is valid.
* @param __CPHA__ USART frame phase.
* @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
*/
#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
/**
* @brief Ensure that USART frame last bit clock pulse setting is valid.
* @param __LASTBIT__ USART frame last bit clock pulse setting.
* @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
*/
#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
((__LASTBIT__) == USART_LASTBIT_ENABLE))
/**
* @brief Ensure that USART request parameter is valid.
* @param __PARAM__ USART request parameter.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
/* Include USART HAL Extended module */
#include "stm32f3xx_hal_usart_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_Exported_Functions USART Exported Functions
* @{
*/
/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_USART_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_usart_ex.h
* @author MCD Application Team
* @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_USART_EX_H
#define STM32F3xx_HAL_USART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup USARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
* @{
*/
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
#elif defined(USART_CR1_M)
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M) /*!< 9-bit long USART frame */
#endif
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
* @{
*/
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval USART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* STM32F302xE || STM32F303xE || STM32F398xx || STM32F302xC || STM32F303xC || STM32F358xx */
/** @brief Compute the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the USART Handle.
* @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
*/
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
#elif defined(USART_CR1_M)
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
#endif
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__ USART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#if defined(USART_CR1_M0)&& defined(USART_CR1_M1)
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
#elif defined(USART_CR1_M)
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
#endif
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USARTEx_Exported_Functions
* @{
*/
/** @addtogroup USARTEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
/**
* @}
*/
/** @addtogroup USARTEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_USART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_hal_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_HAL_WWDG_H
#define STM32F3xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
/**
* @brief WWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/**
* @brief HAL WWDG common Callback ID enumeration definition
*/
typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
*/
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
((__PRESCALER__) == WWDG_PRESCALER_2) || \
((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
((__MODE__) == WWDG_EWI_DISABLE))
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
*/
/**
* @brief Enable the WWDG peripheral.
* @param __HANDLE__ WWDG handle
* @retval None
*/
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
* @brief Enable the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
* @brief Check whether the selected WWDG interrupt has occurred or not.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
/** @brief Clear the WWDG interrupt pending bits.
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
* @brief Check whether the specified WWDG flag is set or not.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the WWDG's pending flags.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
* @param __HANDLE__ WWDG Handle.
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup WWDG_Exported_Functions
* @{
*/
/** @addtogroup WWDG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(MPU services provided only on some devices)
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_LL_CORTEX_H
#define __STM32F3xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x0: revision 0)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Constant number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant
* @retval Value should be equal to 0xF for Cortex-M4 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC24 for Cortex-M4
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_LL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_ll_crc.h
* @author MCD Application Team
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_LL_CRC_H
#define STM32F3xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
#if defined(CRC)
/** @defgroup CRC_LL CRC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
* @{
*/
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
/**
* @}
*/
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
* @{
*/
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
/**
* @}
*/
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
* @{
*/
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
* @brief Normal representation of this polynomial value is
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
* @{
*/
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
* @{
*/
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
* @{
*/
/**
* @brief Reset the CRC calculation unit.
* @note If Programmable Initial CRC value feature
* is available, also set the Data Register to the value stored in the
* CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
* @brief Configure size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
* @param CRCx CRC Instance
* @param PolySize This parameter can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
{
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
}
/**
* @brief Return size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
/**
* @brief Configure the reversal of the bit order of the input data
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
}
/**
* @brief Return type of reversal for input data bit order
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
/**
* @brief Configure the reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
}
/**
* @brief Configure the reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
/**
* @brief Initialize the Programmable initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to write the correct value
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
* @rmtoll INIT INIT LL_CRC_SetInitialData
* @param CRCx CRC Instance
* @param InitCrc Value to be programmed in Programmable initial CRC value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
{
WRITE_REG(CRCx->INIT, InitCrc);
}
/**
* @brief Return current Initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to read the correct value
* @rmtoll INIT INIT LL_CRC_GetInitialData
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
/**
* @brief Initialize the Programmable polynomial value
* (coefficients of the polynomial to be used for CRC calculation).
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
* @param CRCx CRC Instance
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
{
WRITE_REG(CRCx->POL, PolynomCoef);
}
/**
* @brief Return current Programmable polynomial value
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
/**
* @}
*/
/** @defgroup CRC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write given 32-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData32
* @param CRCx CRC Instance
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
{
WRITE_REG(CRCx->DR, InData);
}
/**
* @brief Write given 16-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData16
* @param CRCx CRC Instance
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
__IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = InData;
}
/**
* @brief Write given 8-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData8
* @param CRCx CRC Instance
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
{
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
}
/**
* @brief Return current CRC calculation result. 32 bits value is returned.
* @rmtoll DR DR LL_CRC_ReadData32
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
/**
* @brief Return current CRC calculation result. 16 bits value is returned.
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData16
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 8 bits value is returned.
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData8
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 7 bits value is returned.
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData7
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
/**
* @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 8-bit data register).
*/
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
/**
* @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one byte.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{
*((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData;
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_LL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_ll_fmc.h
* @author MCD Application Team
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_LL_FMC_H
#define STM32F3xx_LL_FMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup FMC_LL
* @{
*/
/** @addtogroup FMC_LL_Private_Macros
* @{
*/
#if defined(FMC_BANK1)
#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
((__BANK__) == FMC_NORSRAM_BANK2) || \
((__BANK__) == FMC_NORSRAM_BANK3) || \
((__BANK__) == FMC_NORSRAM_BANK4))
#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
((__MODE__) == FMC_ACCESS_MODE_B) || \
((__MODE__) == FMC_ACCESS_MODE_C) || \
((__MODE__) == FMC_ACCESS_MODE_D))
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
((__MODE__) == FMC_WRAP_MODE_ENABLE))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
((__STATE__) == FMC_NAND_ECC_ENABLE))
#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
#endif /* FMC_BANK4 */
/**
* @}
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
* @{
*/
#if defined(FMC_BANK1)
#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
#endif /* FMC_BANK4 */
#if defined(FMC_BANK1)
#define FMC_NORSRAM_DEVICE FMC_Bank1
#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_DEVICE FMC_Bank2_3
#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
#define FMC_PCCARD_DEVICE FMC_Bank4
#endif /* FMC_BANK4 */
#if defined(FMC_BANK1)
/**
* @brief FMC NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
memory, valid only when accessing Flash memories in burst mode.
This parameter can be a value of @ref FMC_Wrap_Mode */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
This parameter can be a value of @ref FMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
This parameter is only enabled through the FMC_BCR1 register,
and don't care through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
} FMC_NORSRAM_InitTypeDef;
/**
* @brief FMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and
Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17
in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
} FMC_NORSRAM_TimingTypeDef;
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/**
* @brief FMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
This parameter can be a value of @ref FMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
} FMC_NAND_InitTypeDef;
#endif
#if defined(FMC_BANK3) || defined(FMC_BANK4)
/**
* @brief FMC NAND Timing parameters structure definition
*/
typedef struct
{
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
} FMC_NAND_PCC_TimingTypeDef;
#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
/**
* @brief FMC PCCARD Configuration Structure definition
*/
typedef struct
{
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
}FMC_PCCARD_InitTypeDef;
#endif
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
* @{
*/
#if defined(FMC_BANK1)
/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
* @{
*/
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
#define FMC_NORSRAM_BANK1 (0x00000000U)
#define FMC_NORSRAM_BANK2 (0x00000002U)
#define FMC_NORSRAM_BANK3 (0x00000004U)
#define FMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
#define FMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
* @{
*/
#define FMC_WRAP_MODE_DISABLE (0x00000000U)
#define FMC_WRAP_MODE_ENABLE (0x00000400U)
/**
* @}
*/
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
#define FMC_WRITE_BURST_DISABLE (0x00000000U)
#define FMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
#define FMC_ACCESS_MODE_A (0x00000000U)
#define FMC_ACCESS_MODE_B (0x10000000U)
#define FMC_ACCESS_MODE_C (0x20000000U)
#define FMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3) || defined(FMC_BANK4)
/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
* @{
*/
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
#define FMC_NAND_BANK2 (0x00000010U)
#define FMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
#if defined(FMC_BANK4)
#define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
#endif
#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
/** @defgroup FMC_ECC FMC ECC
* @{
*/
#define FMC_NAND_ECC_DISABLE (0x00000000U)
#define FMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK3 */
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{
*/
#if defined(FMC_BANK3) || defined(FMC_BANK4)
#define FMC_IT_RISING_EDGE (0x00000008U)
#define FMC_IT_LEVEL (0x00000010U)
#define FMC_IT_FALLING_EDGE (0x00000020U)
#endif /* FMC_BANK3 */
/**
* @}
*/
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @{
*/
#if defined(FMC_BANK3) || defined(FMC_BANK4)
#define FMC_FLAG_RISING_EDGE (0x00000001U)
#define FMC_FLAG_LEVEL (0x00000002U)
#define FMC_FLAG_FALLING_EDGE (0x00000004U)
#define FMC_FLAG_FEMPT (0x00000040U)
#endif /* FMC_BANK3 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
* @{
*/
#if defined(FMC_BANK1)
/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
&= ~FMC_BCRx_MBKEN)
/**
* @}
*/
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCRx_PBKEN): \
((__INSTANCE__)->PCR3 |= FMC_PCRx_PBKEN))
/**
* @brief Disable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCRx_PBKEN): \
CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCRx_PBKEN))
/**
* @}
*/
#endif
#if defined(FMC_BANK4)
/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
* @brief macros to handle PCCARD read/write operations
* @{
*/
/**
* @brief Enable the PCCARD device access.
* @param __INSTANCE__ FMC_PCCARD Instance
* @retval None
*/
#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
/**
* @brief Disable the PCCARD device access.
* @param __INSTANCE__ FMC_PCCARD Instance
* @retval None
*/
#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
/**
* @}
*/
#endif
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
* @brief macros to handle NAND interrupts
* @{
*/
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND instance
* @param __BANK__ FMC_NAND Bank
* @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \
((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
/**
* @brief Disable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
((__INSTANCE__)->SR3 &= ~(__FLAG__)))
/**
* @}
*/
#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
/** @defgroup FMC_LL_PCCARD_Interrupt FMC PCCARD Interrupt
* @brief macros to handle PCCARD interrupts
* @{
*/
/**
* @brief Enable the PCCARD device interrupt.
* @param __INSTANCE__ FMC_PCCARD instance
* @param __INTERRUPT__ FMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
/**
* @brief Disable the PCCARD device interrupt.
* @param __INSTANCE__ FMC_PCCARD instance
* @param __INTERRUPT__ FMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
/**
* @brief Get flag status of the PCCARD device.
* @param __INSTANCE__ FMC_PCCARD instance
* @param __FLAG__ FMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the PCCARD device.
* @param __INSTANCE__ FMC_PCCARD instance
* @param __FLAG__ FMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
/**
* @}
*/
#endif
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
* @{
*/
#if defined(FMC_BANK1)
/** @defgroup FMC_LL_NORSRAM NOR SRAM
* @{
*/
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND NAND
* @{
*/
/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
* @{
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK3 */
#if defined(FMC_BANK4)
/** @defgroup FMC_LL_PCCARD PCCARD
* @{
*/
/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init);
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing);
HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK4 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_LL_FMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_gpio.h Normal file
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@@ -0,0 +1,980 @@
/**
******************************************************************************
* @file stm32f3xx_ll_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_LL_GPIO_H
#define __STM32F3xx_LL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH)
/** @defgroup GPIO_LL GPIO
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
* @{
*/
/**
* @brief LL GPIO Init Structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_LL_EC_PIN */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_MODE.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_PULL.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_AF.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
} LL_GPIO_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_LL_EC_PIN PIN
* @{
*/
#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */
#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */
#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */
#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */
#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */
#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */
#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */
#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */
#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */
#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */
#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */
#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */
#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */
#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */
#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */
#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \
GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \
GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \
GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
GPIO_BSRR_BS_15) /*!< Select all pins */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_MODE Mode
* @{
*/
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
* @{
*/
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_SPEED Output Speed
* @{
*/
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
* @{
*/
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_AF Alternate Function
* @{
*/
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
* @{
*/
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
* @{
*/
/**
* @brief Configure gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->MODER,
(GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @param OutputType This parameter can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
}
/**
* @brief Return gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
}
/**
* @brief Configure gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Speed This parameter can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
{
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
(Speed << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
(GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Pull This parameter can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
{
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->PUPDR,
(GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
(Alternate << (POSITION_VAL(Pin) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
(GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
(GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
}
/**
* @brief Lock configuration of several pins for a dedicated port.
* @note When the lock sequence has been applied on a port bit, the
* value of this port bit can no longer be modified until the
* next reset.
* @note Each lock bit freezes a specific configuration register
* (control and alternate function registers).
* @rmtoll LCKR LCKK LL_GPIO_LockPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
__IO uint32_t temp;
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
WRITE_REG(GPIOx->LCKR, PinMask);
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
temp = READ_REG(GPIOx->LCKR);
(void) temp;
}
/**
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
}
/**
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
* @param GPIOx GPIO Port
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
{
return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
}
/**
* @}
*/
/** @defgroup GPIO_LL_EF_Data_Access Data Access
* @{
*/
/**
* @brief Return full input data register value for a dedicated port.
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->IDR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
}
/**
* @brief Write output data register for the port.
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
* @param GPIOx GPIO Port
* @param PortValue Level value for each pin of the port
* @retval None
*/
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
{
WRITE_REG(GPIOx->ODR, PortValue);
}
/**
* @brief Return full output data register value for a dedicated port.
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
* @param GPIOx GPIO Port
* @retval Output data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->ODR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
}
/**
* @brief Set several pins to high level on dedicated gpio port.
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BSRR, PinMask);
}
/**
* @brief Set several pins to low level on dedicated gpio port.
* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BRR, PinMask);
}
/**
* @brief Toggle data value for several pin of dedicated port.
* @rmtoll ODR ODy LL_GPIO_TogglePin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
uint32_t odr = READ_REG(GPIOx->ODR);
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_LL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_ll_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_LL_IWDG_H
#define STM32F3xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
#if defined(IWDG)
/** @defgroup IWDG_LL IWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
* @{
*/
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
/**
* @}
*/
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
* @{
*/
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
* @{
*/
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Start the Independent Watchdog
* @note Except if the hardware watchdog option is selected
* @rmtoll KR KEY LL_IWDG_Enable
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* @rmtoll KR KEY LL_IWDG_ReloadCounter
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
* @brief Select the prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_SetPrescaler
* @param IWDGx IWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
{
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
}
/**
* @brief Get the selected prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_GetPrescaler
* @param IWDGx IWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
/**
* @brief Specify the IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
* @param IWDGx IWDG Instance
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
{
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
}
/**
* @brief Get the specified IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
/**
* @brief Specify high limit of the window value to be compared to the down-counter.
* @rmtoll WINR WIN LL_IWDG_SetWindow
* @param IWDGx IWDG Instance
* @param Window Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
{
WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
}
/**
* @brief Get the high limit of the window value specified.
* @rmtoll WINR WIN LL_IWDG_GetWindow
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->WINR));
}
/**
* @}
*/
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if flag Prescaler Value Update is set or not
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Reload Value Update is set or not
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Window Value Update is set or not
* @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
}
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
* SR RVU LL_IWDG_IsReady\n
* SR WVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* IWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_LL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_opamp.h Normal file
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/**
******************************************************************************
* @file stm32f3xx_ll_opamp.h
* @author MCD Application Team
* @brief Header file of OPAMP LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_LL_OPAMP_H
#define STM32F3xx_LL_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4)
/** @defgroup OPAMP_LL OPAMP
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
* @{
*/
/* Internal mask for OPAMP trimming of transistors differential pair NMOS */
/* or PMOS. */
/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */
/* - OPAMP trimming selection of transistors differential pair */
/* - OPAMP trimming values of transistors differential pair */
#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFSET__ Offset to be applied (unit: number of registers).
* @retval Register address
*/
#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of OPAMP instance.
*/
typedef struct
{
uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
@note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection.
This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
uint32_t InputInverting; /*!< Set OPAMP inverting input connection.
This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
@note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
} LL_OPAMP_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
* @{
*/
/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
* @{
*/
#define LL_OPAMP_MODE_FUNCTIONAL (0x00000000U) /*!< OPAMP functional mode */
#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
* @{
*/
#define LL_OPAMP_MODE_STANDALONE (0x00000000U) /*!< OPAMP functional mode, OPAMP operation in standalone */
#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0) /*!< OPAMP functional mode, OPAMP operation in follower */
#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA */
#define LL_OPAMP_MODE_PGA_EXT_FILT_IO0 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO0. */
#define LL_OPAMP_MODE_PGA_EXT_FILT_IO1 (OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA with external filtering on OPAMP input IO1. */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
* @{
*/
#define LL_OPAMP_PGA_GAIN_2 (0x00000000U) /*!< OPAMP PGA gain 2 */
#define LL_OPAMP_PGA_GAIN_4 (OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4 */
#define LL_OPAMP_PGA_GAIN_8 (OPAMP_CSR_PGGAIN_1) /*!< OPAMP PGA gain 8 */
#define LL_OPAMP_PGA_GAIN_16 (OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0 ) /*!< OPAMP PGA gain 16 */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
* @{
*/
#define LL_OPAMP_INPUT_NONINVERT_IO0 (OPAMP_CSR_VPSEL) /*!< OPAMP non inverting input connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO1 (0x00000000) /*!< OPAMP non inverting input connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO2 (OPAMP_CSR_VPSEL_1) /*!< OPAMP non inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PA4 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO3 (OPAMP_CSR_VPSEL_0) /*!< OPAMP non inverting input connected to GPIO pin (pin PA5 for OPAMP1, pin PB14 for OPAMP2, pin PA5 for OPAMP3, pin PB11 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINV_DAC1_CH1 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
#define LL_OPAMP_INPUT_NONINV_DAC1_CH2 (LL_OPAMP_INPUT_NONINVERT_IO3) /*!< OPAMP non inverting input connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
* @{
*/
#define LL_OPAMP_INPUT_INVERT_IO0 (0x00000000U) /*!< OPAMP inverting input connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
#define LL_OPAMP_INPUT_INVERT_IO1 (OPAMP_CSR_VMSEL_0) /*!< OPAMP inverting input connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (OPAMP_CSR_VMSEL_1) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA without external capacitors for filtering). Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING_SECONDARY OPAMP input non-inverting secondary
* @{
*/
#define LL_OPAMP_INPUT_NONINVERT_IO0_SEC (LL_OPAMP_INPUT_NONINVERT_IO0 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA1 for OPAMP1, pin PA7 for OPAMP2, pin PB0 for OPAMP3, pin PB13 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO1_SEC (LL_OPAMP_INPUT_NONINVERT_IO1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA7 for OPAMP1, pin PD14 for OPAMP2, pin PB13 for OPAMP3, pin PD11 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO2_SEC (LL_OPAMP_INPUT_NONINVERT_IO2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PB0 for OPAMP2, pin PA1 for OPAMP3, pin PB11 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINVERT_IO3_SEC (LL_OPAMP_INPUT_NONINVERT_IO3 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to GPIO pin (pin PA5 for OPAMP1, pin PD14 for OPAMP2, pin PA5 for OPAMP3, pin PA4 for OPAMP4) */
#define LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH1 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel1 output (specific to OPAMP instances: OPAMP4) */
#define LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (LL_OPAMP_INPUT_NONINV_DAC1_CH2 << (OPAMP_CSR_VPSSEL_Pos - OPAMP_CSR_VPSEL_Pos)) /*!< OPAMP non inverting input secondary connected to DAC1 channel2 output (specific to OPAMP instances: OPAMP1, OPAMP3) */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_INVERTING_SECONDARY OPAMP input inverting secondary
* @{
*/
#define LL_OPAMP_INPUT_INVERT_IO0_SEC (LL_OPAMP_INPUT_INVERT_IO0 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PC5 for OPAMP1, pin PC5 for OPAMP2, pin PB10 for OPAMP3, pin PB10 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
#define LL_OPAMP_INPUT_INVERT_IO1_SEC (LL_OPAMP_INPUT_INVERT_IO1 << (OPAMP_CSR_VMSSEL_Pos - OPAMP_CSR_VMSEL_Pos)) /*!< OPAMP inverting input secondary connected to GPIO pin (pin PA3 for OPAMP1, pin PA5 for OPAMP2, pin PB2 for OPAMP3, pin PD8 for OPAMP4). Note: OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_MUX_MODE OPAMP inputs multiplexer mode
* @{
*/
#define LL_OPAMP_INPUT_MUX_DISABLE (0x00000000U) /*!< OPAMP inputs multiplexer mode dosabled. */
#define LL_OPAMP_INPUT_MUX_TIM1_CH6 (OPAMP_CSR_TCMEN) /*!< OPAMP inputs multiplexer mode enabled, controlled by TIM1 CC6. */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_VREF_OUTPUT OPAMP internal reference voltage path state to output
* @{
*/
#define LL_OPAMP_VREF_OUTPUT_DISABLE (0x00000000U) /*!< OPAMP internal reference voltage path to output is disabled. */
#define LL_OPAMP_VREF_OUTPUT_ENABLE (OPAMP_CSR_TSTREF) /*!< OPAMP internal reference voltage path to output is enabled. */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
* @{
*/
#define LL_OPAMP_TRIMMING_FACTORY (0x00000000U) /*!< OPAMP trimming factors set to factory values */
#define LL_OPAMP_TRIMMING_USER (OPAMP_CSR_USERTRIM) /*!< OPAMP trimming factors set to user values */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
* @{
*/
#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 ) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP ) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
#define LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
#define LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
* @note Only OPAMP IP HW delays are defined in OPAMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for OPAMP startup time (transition from state disable to enable). */
/* Note: OPAMP startup time depends on board application environment: */
/* impedance connected to OPAMP output. */
/* The delay below is specified under conditions: */
/* - OPAMP in functional mode follower */
/* - load impedance of 4kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define LL_OPAMP_DELAY_STARTUP_US (5U) /*!< Delay for OPAMP startup time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
* @{
*/
/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
* @{
*/
/**
* @brief Write a value in OPAMP register
* @param __INSTANCE__ OPAMP Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in OPAMP register
* @param __INSTANCE__ OPAMP Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
* @{
*/
/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
* @{
*/
/**
* @brief Set OPAMP mode calibration or functional.
* @note OPAMP mode corresponds to functional or calibration mode:
* - functional mode: OPAMP operation in standalone, follower, ...
* Set functional mode using function
* @ref LL_OPAMP_SetFunctionalMode().
* - calibration mode: offset calibration of the selected
* transistors differential pair NMOS or PMOS.
* @rmtoll CSR CALON LL_OPAMP_SetMode
* @param OPAMPx OPAMP instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_MODE_FUNCTIONAL
* @arg @ref LL_OPAMP_MODE_CALIBRATION
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
}
/**
* @brief Get OPAMP mode calibration or functional.
* @note OPAMP mode corresponds to functional or calibration mode:
* - functional mode: OPAMP operation in standalone, follower, ...
* Set functional mode using function
* @ref LL_OPAMP_SetFunctionalMode().
* - calibration mode: offset calibration of the selected
* transistors differential pair NMOS or PMOS.
* @rmtoll CSR CALON LL_OPAMP_GetMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_MODE_FUNCTIONAL
* @arg @ref LL_OPAMP_MODE_CALIBRATION
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
}
/**
* @brief Set OPAMP functional mode by setting internal connections.
* OPAMP operation in standalone, follower, ...
* @note This function reset bit of calibration mode to ensure
* to be in functional mode, in order to have OPAMP parameters
* (inputs selection, ...) set with the corresponding OPAMP mode
* to be effective.
* @rmtoll CSR VMSEL LL_OPAMP_SetFunctionalMode
* @param OPAMPx OPAMP instance
* @param FunctionalMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_MODE_STANDALONE
* @arg @ref LL_OPAMP_MODE_FOLLOWER
* @arg @ref LL_OPAMP_MODE_PGA
* @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
* @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
{
/* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
}
/**
* @brief Get OPAMP functional mode from setting of internal connections.
* OPAMP operation in standalone, follower, ...
* @rmtoll CSR VMSEL LL_OPAMP_GetFunctionalMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_MODE_STANDALONE
* @arg @ref LL_OPAMP_MODE_FOLLOWER
* @arg @ref LL_OPAMP_MODE_PGA
* @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO0
* @arg @ref LL_OPAMP_MODE_PGA_EXT_FILT_IO1
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL));
}
/**
* @brief Set OPAMP PGA gain.
* @note Preliminarily, OPAMP must be set in mode PGA
* using function @ref LL_OPAMP_SetFunctionalMode().
* @rmtoll CSR PGGAIN LL_OPAMP_SetPGAGain
* @param OPAMPx OPAMP instance
* @param PGAGain This parameter can be one of the following values:
* @arg @ref LL_OPAMP_PGA_GAIN_2
* @arg @ref LL_OPAMP_PGA_GAIN_4
* @arg @ref LL_OPAMP_PGA_GAIN_8
* @arg @ref LL_OPAMP_PGA_GAIN_16
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
}
/**
* @brief Get OPAMP PGA gain.
* @note Preliminarily, OPAMP must be set in mode PGA
* using function @ref LL_OPAMP_SetFunctionalMode().
* @rmtoll CSR PGGAIN LL_OPAMP_GetPGAGain
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_PGA_GAIN_2
* @arg @ref LL_OPAMP_PGA_GAIN_4
* @arg @ref LL_OPAMP_PGA_GAIN_8
* @arg @ref LL_OPAMP_PGA_GAIN_16
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
* @{
*/
/**
* @brief Set OPAMP non-inverting input connection.
* @rmtoll CSR VPSEL LL_OPAMP_SetInputNonInverting
* @param OPAMPx OPAMP instance
* @param InputNonInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
*
* (1) Parameter specific to OPAMP instances: OPAMP4.\n
* (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
}
/**
* @brief Get OPAMP non-inverting input connection.
* @rmtoll CSR VPSEL LL_OPAMP_GetInputNonInverting
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 (1)
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2 (2)
*
* (1) Parameter specific to OPAMP instances: OPAMP4.\n
* (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
}
/**
* @brief Set OPAMP inverting input connection.
* @note OPAMP inverting input is used with OPAMP in mode standalone
* or PGA with external capacitors for filtering circuit.
* Otherwise (OPAMP in mode follower), OPAMP inverting input
* is not used (not connected to GPIO pin).
* @rmtoll CSR VMSEL LL_OPAMP_SetInputInverting
* @param OPAMPx OPAMP instance
* @param InputInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1
* @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
{
/* Manage cases of OPAMP inverting input not connected (0x10 and 0x11) */
/* to not modify OPAMP mode follower or PGA. */
/* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
}
/**
* @brief Get OPAMP inverting input connection.
* @rmtoll CSR VMSEL LL_OPAMP_GetInputInverting
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1
* @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
{
uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
/* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */
/* input not connected. */
return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
}
/**
* @brief Set OPAMP non-inverting input secondary connection.
* @rmtoll CSR VPSSEL LL_OPAMP_SetInputNonInvertingSecondary
* @param OPAMPx OPAMP instance
* @param InputNonInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
*
* (1) Parameter specific to OPAMP instances: OPAMP4.\n
* (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSSEL, InputNonInverting);
}
/**
* @brief Get OPAMP non-inverting input secondary connection.
* @rmtoll CSR VPSSEL LL_OPAMP_GetInputNonInvertingSecondary
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1_SEC (1)
* @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH2_SEC (2)
*
* (1) Parameter specific to OPAMP instances: OPAMP4.\n
* (2) Parameter specific to OPAMP instances: OPAMP1, OPAMP3.
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSSEL));
}
/**
* @brief Set OPAMP inverting input secondary connection.
* @note OPAMP inverting input is used with OPAMP in mode standalone
* or PGA with external capacitors for filtering circuit.
* Otherwise (OPAMP in mode follower), OPAMP inverting input
* is not used (not connected to GPIO pin).
* @rmtoll CSR VMSSEL LL_OPAMP_SetInputInvertingSecondary
* @param OPAMPx OPAMP instance
* @param InputInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VMSSEL, InputInverting);
}
/**
* @brief Get OPAMP inverting input secondary connection.
* @rmtoll CSR VMSSEL LL_OPAMP_GetInputInvertingSecondary
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSSEL));
}
/**
* @brief Set OPAMP inputs multiplexer mode.
* @rmtoll CSR TCMEN LL_OPAMP_SetInputsMuxMode
* @param OPAMPx OPAMP instance
* @param InputsMuxMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
* @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TCMEN, InputsMuxMode);
}
/**
* @brief Get OPAMP inputs multiplexer mode.
* @rmtoll CSR TCMEN LL_OPAMP_GetInputsMuxMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
* @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TCMEN));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
* @{
*/
/**
* @brief Set OPAMP trimming mode.
* @rmtoll CSR USERTRIM LL_OPAMP_SetTrimmingMode
* @param OPAMPx OPAMP instance
* @param TrimmingMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_FACTORY
* @arg @ref LL_OPAMP_TRIMMING_USER
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
}
/**
* @brief Get OPAMP trimming mode.
* @rmtoll CSR USERTRIM LL_OPAMP_GetTrimmingMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_FACTORY
* @arg @ref LL_OPAMP_TRIMMING_USER
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
}
/**
* @brief Set OPAMP offset to calibrate the selected transistors
* differential pair NMOS or PMOS.
* @note Preliminarily, OPAMP must be set in mode calibration
* using function @ref LL_OPAMP_SetMode().
* @rmtoll CSR CALSEL LL_OPAMP_SetCalibrationSelection
* @param OPAMPx OPAMP instance
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
* @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
*
* (1) Default parameters to be used for calibration
* using two trimming steps (one with each transistors differential
* pair NMOS and PMOS)
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
{
/* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */
/* containing other bits reserved for other purpose. */
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
}
/**
* @brief Get OPAMP offset to calibrate the selected transistors
* differential pair NMOS or PMOS.
* @note Preliminarily, OPAMP must be set in mode calibration
* using function @ref LL_OPAMP_SetMode().
* @rmtoll CSR CALSEL LL_OPAMP_GetCalibrationSelection
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
* @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
*
* (1) Default parameters to be used for calibration
* using two trimming steps (one with each transistors differential
* pair NMOS and PMOS)
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
{
uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
return (CalibrationSelection |
(((CalibrationSelection & OPAMP_CSR_CALSEL) == 0UL) ? OPAMP_CSR_TRIMOFFSETN : OPAMP_CSR_TRIMOFFSETP));
}
/**
* @brief Set OPAMP calibration internal reference voltage to output.
* @rmtoll CSR TSTREF LL_OPAMP_SetCalibrationVrefOutput
* @param OPAMPx OPAMP instance
* @param CalibrationVrefOutput This parameter can be one of the following values:
* @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
* @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx, uint32_t CalibrationVrefOutput)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_TSTREF, CalibrationVrefOutput);
}
/**
* @brief Get OPAMP calibration internal reference voltage to output.
* @rmtoll CSR TSTREF LL_OPAMP_GetCalibrationVrefOutput
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_VREF_OUTPUT_DISABLE
* @arg @ref LL_OPAMP_VREF_OUTPUT_ENABLE
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationVrefOutput(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_TSTREF));
}
/**
* @brief Get OPAMP calibration result of toggling output.
* @note This functions returns:
* 0 if OPAMP calibration output is reset
* 1 if OPAMP calibration output is set
* @rmtoll CSR OUTCAL LL_OPAMP_IsCalibrationOutputSet
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OUTCAL) == OPAMP_CSR_OUTCAL) ? 1UL : 0UL);
}
/**
* @brief Set OPAMP trimming factor for the selected transistors
* differential pair NMOS or PMOS, corresponding to the selected
* power mode.
* @rmtoll CSR TRIMOFFSETN LL_OPAMP_SetTrimmingValue\n
* CSR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
* @param OPAMPx OPAMP instance
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
* @param TrimmingValue 0x00...0x1F
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)
{
MODIFY_REG(OPAMPx->CSR,
(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
TrimmingValue << ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos));
}
/**
* @brief Get OPAMP trimming factor for the selected transistors
* differential pair NMOS or PMOS, corresponding to the selected
* power mode.
* @rmtoll CSR TRIMOFFSETN LL_OPAMP_GetTrimmingValue\n
* CSR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
* @param OPAMPx OPAMP instance
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
* @retval 0x0...0x1F
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t TransistorsDiffPair)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
>> ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
* @{
*/
/**
* @brief Enable OPAMP instance.
* @note After enable from off state, OPAMP requires a delay
* to fullfill wake up time specification.
* Refer to device datasheet, parameter "tWAKEUP".
* @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
{
SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
}
/**
* @brief Disable OPAMP instance.
* @rmtoll CSR OPAMPXEN LL_OPAMP_Disable
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
{
CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
}
/**
* @brief Get OPAMP instance enable state
* (0: OPAMP is disabled, 1: OPAMP is enabled)
* @rmtoll CSR OPAMPXEN LL_OPAMP_IsEnabled
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)) ? 1UL : 0UL);
}
/**
* @brief Lock OPAMP instance.
* @note Once locked, OPAMP configuration can be accessed in read-only.
* @note The only way to unlock the OPAMP is a device hardware reset.
* @rmtoll CSR LOCK LL_OPAMP_Lock
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
{
SET_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK);
}
/**
* @brief Get OPAMP lock state
* (0: OPAMP is unlocked, 1: OPAMP is locked).
* @note Once locked, OPAMP configuration can be accessed in read-only.
* @note The only way to unlock the OPAMP is a device hardware reset.
* @rmtoll CSR LOCK LL_OPAMP_IsLocked
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK) == (OPAMP_CSR_LOCK)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_LL_OPAMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h Normal file
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@@ -0,0 +1,554 @@
/**
******************************************************************************
* @file stm32f3xx_ll_pwr.h
* @author MCD Application Team
* @brief Header file of PWR LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_LL_PWR_H
#define __STM32F3xx_LL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_PWR_WriteReg function
* @{
*/
#define LL_PWR_CR_CSBF PWR_CR_CSBF /*!< Clear standby flag */
#define LL_PWR_CR_CWUF PWR_CR_CWUF /*!< Clear wakeup flag */
/**
* @}
*/
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_PWR_ReadReg function
* @{
*/
#define LL_PWR_CSR_WUF PWR_CSR_WUF /*!< Wakeup flag */
#define LL_PWR_CSR_SBF PWR_CSR_SBF /*!< Standby flag */
#if defined(PWR_PVD_SUPPORT)
#define LL_PWR_CSR_PVDO PWR_CSR_PVDO /*!< Power voltage detector output flag */
#endif /* PWR_PVD_SUPPORT */
#if defined(PWR_CSR_VREFINTRDYF)
#define LL_PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF /*!< VREFINT ready flag */
#endif /* PWR_CSR_VREFINTRDYF */
#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1 /*!< Enable WKUP pin 1 */
#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2 /*!< Enable WKUP pin 2 */
#if defined(PWR_CSR_EWUP3)
#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3 /*!< Enable WKUP pin 3 */
#endif /* PWR_CSR_EWUP3 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
* @{
*/
#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode when the CPU enters deepsleep */
#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS) /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS) /*!< Enter Standby mode when the CPU enters deepsleep */
/**
* @}
*/
#if defined(PWR_CR_LPDS)
/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
* @{
*/
#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS) /*!< Voltage Regulator in low-power mode during deepsleep mode */
/**
* @}
*/
#endif /* PWR_CR_LPDS */
#if defined(PWR_PVD_SUPPORT)
/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
* @{
*/
#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0) /*!< Voltage threshold detected by PVD 2.2 V */
#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1) /*!< Voltage threshold detected by PVD 2.3 V */
#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2) /*!< Voltage threshold detected by PVD 2.4 V */
#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3) /*!< Voltage threshold detected by PVD 2.5 V */
#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4) /*!< Voltage threshold detected by PVD 2.6 V */
#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5) /*!< Voltage threshold detected by PVD 2.7 V */
#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6) /*!< Voltage threshold detected by PVD 2.8 V */
#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7) /*!< Voltage threshold detected by PVD 2.9 V */
/**
* @}
*/
#endif /* PWR_PVD_SUPPORT */
/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
* @{
*/
#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1) /*!< WKUP pin 1 : PA0 */
#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2) /*!< WKUP pin 2 : PC13 */
#if defined(PWR_CSR_EWUP3)
#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3) /*!< WKUP pin 3 : PE6 or PA2 according to device */
#endif /* PWR_CSR_EWUP3 */
/**
* @}
*/
/** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx
* @{
*/
#if defined(SDADC1)
#define LL_PWR_SDADC_ANALOG1 (PWR_CR_ENSD1) /*!< Enable SDADC1 */
#endif /* SDADC1 */
#if defined(SDADC2)
#define LL_PWR_SDADC_ANALOG2 (PWR_CR_ENSD2) /*!< Enable SDADC2 */
#endif /* SDADC2 */
#if defined(SDADC3)
#define LL_PWR_SDADC_ANALOG3 (PWR_CR_ENSD3) /*!< Enable SDADC3 */
#endif /* SDADC3 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
* @{
*/
/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in PWR register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
/**
* @brief Read a value in PWR register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enables the SDADC peripheral functionality
* @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
* CR ENSD2 LL_PWR_EnableSDADC\n
* CR ENSD3 LL_PWR_EnableSDADC
* @param Analogx This parameter can be a combination of the following values:
* @arg @ref LL_PWR_SDADC_ANALOG1
* @arg @ref LL_PWR_SDADC_ANALOG2
* @arg @ref LL_PWR_SDADC_ANALOG3
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
{
SET_BIT(PWR->CR, Analogx);
}
/**
* @brief Disables the SDADC peripheral functionality
* @rmtoll CR ENSD1 LL_PWR_EnableSDADC\n
* CR ENSD2 LL_PWR_EnableSDADC\n
* CR ENSD3 LL_PWR_EnableSDADC
* @param Analogx This parameter can be a combination of the following values:
* @arg @ref LL_PWR_SDADC_ANALOG1
* @arg @ref LL_PWR_SDADC_ANALOG2
* @arg @ref LL_PWR_SDADC_ANALOG3
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
{
CLEAR_BIT(PWR->CR, Analogx);
}
/**
* @brief Check if SDADCx has been enabled or not
* @rmtoll CR ENSD1 LL_PWR_IsEnabledSDADC\n
* CR ENSD2 LL_PWR_IsEnabledSDADC\n
* CR ENSD3 LL_PWR_IsEnabledSDADC
* @param Analogx This parameter can be a combination of the following values:
* @arg @ref LL_PWR_SDADC_ANALOG1
* @arg @ref LL_PWR_SDADC_ANALOG2
* @arg @ref LL_PWR_SDADC_ANALOG3
* @retval None
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
{
return (READ_BIT(PWR->CR, Analogx) == (Analogx));
}
/**
* @brief Enable access to the backup domain
* @rmtoll CR DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Disable access to the backup domain
* @rmtoll CR DBP LL_PWR_DisableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_DBP);
}
/**
* @brief Check if the backup domain is enabled
* @rmtoll CR DBP LL_PWR_IsEnabledBkUpAccess
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
}
#if defined(PWR_CR_LPDS)
/**
* @brief Set voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_SetRegulModeDS
* @param RegulMode This parameter can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
{
MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
}
/**
* @brief Get voltage Regulator mode during deep sleep mode
* @rmtoll CR LPDS LL_PWR_GetRegulModeDS
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_DSMODE_MAIN
* @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
}
#endif /* PWR_CR_LPDS */
/**
* @brief Set Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_SetPowerMode\n
* @rmtoll CR LPDS LL_PWR_SetPowerMode
* @param PDMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
{
MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
}
/**
* @brief Get Power Down mode when CPU enters deepsleep
* @rmtoll CR PDDS LL_PWR_GetPowerMode\n
* @rmtoll CR LPDS LL_PWR_GetPowerMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP_MAINREGU
* @arg @ref LL_PWR_MODE_STOP_LPREGU
* @arg @ref LL_PWR_MODE_STANDBY
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
}
#if defined(PWR_PVD_SUPPORT)
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector
* @rmtoll CR PLS LL_PWR_SetPVDLevel
* @param PVDLevel This parameter can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
}
/**
* @brief Get the voltage threshold detection
* @rmtoll CR PLS LL_PWR_GetPVDLevel
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
*/
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
{
return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
}
/**
* @brief Enable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_EnablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Disable Power Voltage Detector
* @rmtoll CR PVDE LL_PWR_DisablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
}
/**
* @brief Check if Power Voltage Detector is enabled
* @rmtoll CR PVDE LL_PWR_IsEnabledPVD
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
{
return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
}
#endif /* PWR_PVD_SUPPORT */
/**
* @brief Enable the WakeUp PINx functionality
* @rmtoll CSR EWUP1 LL_PWR_EnableWakeUpPin\n
* @rmtoll CSR EWUP2 LL_PWR_EnableWakeUpPin\n
* @rmtoll CSR EWUP3 LL_PWR_EnableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
*
* (*) not available on all devices
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
SET_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Disable the WakeUp PINx functionality
* @rmtoll CSR EWUP1 LL_PWR_DisableWakeUpPin\n
* @rmtoll CSR EWUP2 LL_PWR_DisableWakeUpPin\n
* @rmtoll CSR EWUP3 LL_PWR_DisableWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
*
* (*) not available on all devices
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->CSR, WakeUpPin);
}
/**
* @brief Check if the WakeUp PINx functionality is enabled
* @rmtoll CSR EWUP1 LL_PWR_IsEnabledWakeUpPin\n
* @rmtoll CSR EWUP2 LL_PWR_IsEnabledWakeUpPin\n
* @rmtoll CSR EWUP3 LL_PWR_IsEnabledWakeUpPin
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3 (*)
*
* (*) not available on all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
}
/**
* @}
*/
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Wake-up Flag
* @rmtoll CSR WUF LL_PWR_IsActiveFlag_WU
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
}
/**
* @brief Get Standby Flag
* @rmtoll CSR SBF LL_PWR_IsActiveFlag_SB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
}
#if defined(PWR_PVD_SUPPORT)
/**
* @brief Indicate whether VDD voltage is below the selected PVD threshold
* @rmtoll CSR PVDO LL_PWR_IsActiveFlag_PVDO
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
}
#endif /* PWR_PVD_SUPPORT */
#if defined(PWR_CSR_VREFINTRDYF)
/**
* @brief Get Internal Reference VrefInt Flag
* @rmtoll CSR VREFINTRDYF LL_PWR_IsActiveFlag_VREFINTRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
{
return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
}
#endif /* PWR_CSR_VREFINTRDYF */
/**
* @brief Clear Standby Flag
* @rmtoll CR CSBF LL_PWR_ClearFlag_SB
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
{
SET_BIT(PWR->CR, PWR_CR_CSBF);
}
/**
* @brief Clear Wake-up Flags
* @rmtoll CR CWUF LL_PWR_ClearFlag_WU
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
{
SET_BIT(PWR->CR, PWR_CR_CWUF);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup PWR_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_PWR_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_LL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_ll_usb.h
* @author MCD Application Team
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_LL_USB_H
#define STM32F3xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx_hal_def.h"
#if defined (USB)
/** @addtogroup STM32F3xx_HAL_Driver
* @{
*/
/** @addtogroup USB_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USB Mode definition
*/
typedef enum
{
USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
/**
* @brief USB Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral
This parameter is added to ensure compatibility across USB peripherals */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
/**
* @}
*/
#define BTABLE_ADDRESS 0x000U
#if defined(STM32F303xC) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F301x8) || defined(STM32F373xC) || defined(STM32F378xx) || defined(STM32F302xC)
#define PMA_ACCESS 2U
#endif /* STM32F303xC || */
/* STM32F303x8 || STM32F334x8 || */
/* STM32F301x8 || */
/* STM32F373xC || STM32F378xx */
#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F302x8)
#define PMA_ACCESS 1U
#endif /* STM32F302xE || STM32F303xE || */
/* STM32F302xC || */
/* STM32F302x8 */
#define EP_ADDR_MSK 0x7U
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_LL_USB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f3xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_LL_UTILS_H
#define __STM32F3xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
#else
uint32_t Prediv; /*!< Division factor for HSE used as PLL clock source.
This parameter can be a value of @ref RCC_LL_EC_PREDIV_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
#endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
#if defined(FLASH_ACR_LATENCY)
ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
#endif /* FLASH_ACR_LATENCY */
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_LL_UTILS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_wwdg.h Normal file
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@@ -0,0 +1,319 @@
/**
******************************************************************************
* @file stm32f3xx_ll_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG LL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F3xx_LL_WWDG_H
#define STM32F3xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f3xx.h"
/** @addtogroup STM32F3xx_LL_Driver
* @{
*/
#if defined (WWDG)
/** @defgroup WWDG_LL WWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
* @{
*/
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
* @{
*/
/**
* @brief Write a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
* then it cannot be disabled again except by a reset.
* This bit is set by software and only cleared by hardware after a reset.
* When WDGA = 1, the watchdog can generate a reset.
* @rmtoll CR WDGA LL_WWDG_Enable
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
}
/**
* @brief Checks if Window Watchdog is enabled
* @rmtoll CR WDGA LL_WWDG_IsEnabled
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
* @rmtoll CR T LL_WWDG_SetCounter
* @param WWDGx WWDG Instance
* @param Counter 0..0x7F (7 bit counter value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
{
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
}
/**
* @brief Return current Watchdog Counter Value (7 bits counter value)
* @rmtoll CR T LL_WWDG_GetCounter
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
* @brief Set the time base of the prescaler (WDGTB).
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
* is decremented every (4096 x 2expWDGTB) PCLK cycles
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
* @param WWDGx WWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
}
/**
* @brief Return current Watchdog Prescaler Value
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
* @param WWDGx WWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
* @note This window value defines when write in the WWDG_CR register
* to program Watchdog counter is allowed.
* Watchdog counter value update must occur only when the counter value
* is lower than the Watchdog window register value.
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
* (in the control register) is refreshed before the downcounter has reached
* the watchdog window register value.
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
* @rmtoll CFR W LL_WWDG_SetWindow
* @param WWDGx WWDG Instance
* @param Window 0x00..0x7F (7 bit Window value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
}
/**
* @brief Return current Watchdog Window Value (7 bits value)
* @rmtoll CFR W LL_WWDG_GetWindow
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
* @note This bit is set by hardware when the counter has reached the value 0x40.
* It must be cleared by software by writing 0.
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable the Early Wakeup Interrupt.
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
* This interrupt is only cleared by hardware after a reset
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
}
/**
* @brief Check if Early Wakeup Interrupt is enabled
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* WWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32F3xx_LL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/