45 lines
2.5 KiB
C
45 lines
2.5 KiB
C
// Author: https://github.com/MajicDesigns/MD_AD9833
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#pragma once
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/** @}*/
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// AD9833 Control Register bit definitions
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#define AD_B28 13 ///< B28 = 1 allows a complete word to be loaded into a frequency register in
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///< two consecutive writes. When B28 = 0, the 28-bit frequency register
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///< operates as two 14-bit registers.
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#define AD_HLB 12 ///< Control bit allows the user to continuously load the MSBs or LSBs of a
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///< frequency register while ignoring the remaining 14 bits. HLB is used
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///< in conjunction with B28; when B28 = 1, this control bit is ignored.
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#define AD_FSELECT 11 ///< Defines whether the FREQ0 register or the FREQ1 register is used in
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///< the phase accumulator.
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#define AD_PSELECT 10 ///< Defines whether the PHASE0 register or the PHASE1 register data is
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///< added to the output of the phase accumulator.
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#define AD_RESET 8 ///< Reset = 1 resets internal registers to 0, which corresponds to an
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///< analog output of midscale. Reset = 0 disables reset.
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#define AD_SLEEP1 7 ///< When SLEEP1 = 1, the internal MCLK clock is disabled, and the DAC output
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///< remains at its present value. When SLEEP1 = 0, MCLK is enabled.
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#define AD_SLEEP12 6 ///< SLEEP12 = 1 powers down the on-chip DAC. SLEEP12 = 0 implies that
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///< the DAC is active.
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#define AD_OPBITEN 5 ///< When OPBITEN = 1, the output of the DAC is no longer available at the
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///< VOUT pin, replaced by MSB (or MSB/2) of the DAC. When OPBITEN = 0, the
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///< DAC is connected to VOUT.
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#define AD_DIV2 3 ///< When DIV2 = 1, the MSB of the DAC data is passed to the VOUT pin. When
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///< DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin.
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#define AD_MODE 1 ///< When MODE = 1, the SIN ROM is bypassed, resulting in a triangle output
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///< from the DAC. When MODE = 0, the SIN ROM is used which results in a
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///< sinusoidal signal at the output.
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// AD9833 Frequency and Phase register bit definitions
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#define AD_FREQ1 15 ///< Select frequency 1 register
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#define AD_FREQ0 14 ///< Select frequency 0 register
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#define AD_PHASE 13 ///< Select the phase register
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// AD9833 Freq and Phase register address identifiers
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#define SEL_FREQ0 (1 << AD_FREQ0)
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#define SEL_FREQ1 (1 << AD_FREQ1)
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#define SEL_PHASE0 (1 << AD_FREQ0 | 1 << AD_FREQ1 | 0 << AD_PHASE)
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#define SEL_PHASE1 (1 << AD_FREQ0 | 1 << AD_FREQ1 | 1 << AD_PHASE)
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// AD9833 frequency and phase calculation macros
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#define AD_2POW28 (1ULL << 28) ///< Used when calculating output frequency
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