#include "main.h" #include "spi.h" #include "i2c.h" #include "ctrl_app_types.h" #include "ad9833.h" #include "ltc2631.h" #include "mcp41x.h" #include "ctrl_generator.h" typedef struct FG_handle_s FG_handle_t; typedef struct { GPIO_TypeDef *port; uint16_t pin; } GEN_led_t; struct FG_handle_s { ad9833_handle_t hdds; ltc2631_handle_t hoffs; mcp41x_handle_t hampl; FG_handle_t *link[2]; GEN_led_t hled; }; typedef uint8_t timer_handle_t; typedef struct { timer_handle_t hpwm; ltc2631_handle_t hoffs; mcp41x_handle_t hampl; GEN_led_t hled; } PWM_handle_t; typedef enum { FG_CHAN1, FG_CHAN2, FG_CHAN3, FG_CHAN_MAX, } FG_channel_t; typedef enum { PWM_CHAN1, PWM_CHAN2, PWM_CHAN3, PWM_CHAN_MAX, } PWM_channel_t; FG_handle_t dds_gen[FG_CHAN_MAX]; PWM_handle_t pwm_gen[PWM_CHAN_MAX]; uint8_t ch_to_gen_ch[CHANNEL_MAX] = {FG_CHAN1, FG_CHAN2, FG_CHAN3, PWM_CHAN1, PWM_CHAN2, PWM_CHAN3}; // #define DDS1_CS_PORT GPIOC // #define DDS2_CS_PORT GPIOC // #define DDS3_CS_PORT GPIOC // #define DDS1_CS_PIN GPIO_PIN_0 // #define DDS2_CS_PIN GPIO_PIN_0 // #define DDS3_CS_PIN GPIO_PIN_0 // #define AMP1_CS_PORT GPIOC // #define AMP2_CS_PORT GPIOC // #define AMP3_CS_PORT GPIOC // #define AMP1_CS_PIN GPIO_PIN_0 // #define AMP2_CS_PIN GPIO_PIN_0 // #define AMP3_CS_PIN GPIO_PIN_0 void led_init(GEN_led_t *hled, GPIO_TypeDef *port, uint16_t pin) { hled->port = port; hled->pin = pin; HAL_GPIO_WritePin(port, pin, GPIO_PIN_SET); } void led_on(GEN_led_t *hled) { HAL_GPIO_WritePin(hled->port, hled->pin, GPIO_PIN_RESET); } void led_off(GEN_led_t *hled) { HAL_GPIO_WritePin(hled->port, hled->pin, GPIO_PIN_SET); } void gen_init() { ad9833_init(&dds_gen[FG_CHAN1].hdds, &hspi2, DDS1_CS_GPIO_Port, DDS1_CS_Pin); ad9833_init(&dds_gen[FG_CHAN2].hdds, &hspi2, DDS2_CS_GPIO_Port, DDS2_CS_Pin); // ad9833_init(&dds_gen[FG_CHAN3].hdds, &hspi2, DDS3_CS_PORT, DDS3_CS_PIN); // ltc2631_init(&dds_gen[FG_CHAN1].hoffs, &hi2c1, 0x00, LTC2631_8BIT, LTC_REF_2V5); // ltc2631_init(&dds_gen[FG_CHAN2].hoffs, &hi2c1, 0x01, LTC2631_8BIT, LTC_REF_2V5); // ltc2631_init(&dds_gen[FG_CHAN3].hoffs, &hi2c1, 0x02, LTC2631_8BIT, LTC_REF_2V5); mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP1_CS_GPIO_Port, AMP1_CS_Pin, MCP41X_10K); mcp41x_init(&dds_gen[FG_CHAN2].hampl, &hspi2, AMP2_CS_GPIO_Port, AMP2_CS_Pin, MCP41X_10K); // mcp41x_init(&dds_gen[FG_CHAN3].hampl, &hspi2, AMP3_CS_PORT, AMP3_CS_PIN, MCP41X_10K); led_init(&dds_gen[FG_CHAN1].hled, LED_CH1_GPIO_Port, LED_CH1_Pin); led_init(&dds_gen[FG_CHAN2].hled, LED_CH2_GPIO_Port, LED_CH2_Pin); } static void _setAmpliude(mcp41x_handle_t *hampl, uint16_t ampl_x100) { uint8_t value = (ampl_x100 * UINT8_MAX) / MAX_VOLT_POS; ULOG_DEBUG("(%d:_setAmplitude) ampl_x100: %d, value: %d", __LINE__, ampl_x100, value); mcp41x_setValue(hampl, value); } static void _setOffset(ltc2631_handle_t *hoffs, int16_t offs_x100) { uint32_t value = (offs_x100 + MAX_VOLT_POS) * LTC_REF_2V5; ULOG_DEBUG("(%d:_setOffset) offs_x100: %d, value: %d", __LINE__, offs_x100, value); ltc2631_setOutputVoltage_u(hoffs, value); } static void _setFreqDdsGen(ad9833_handle_t *hdds, uint32_t freq) { ULOG_DEBUG("(%d:_setFreqDdsGen) freq: %d", __LINE__, freq); ad9833_setFrequency(hdds, CHAN_0, freq); } static void _setPhaseDdsGen(ad9833_handle_t *hdds, uint32_t phas) { ULOG_DEBUG("(%d:_setPhaseDdsGen) phase: %d", __LINE__, phas); ad9833_setPhase(hdds, CHAN_0, phas); } static void _setWaveDdsGen(ad9833_handle_t *hdds, GEN_wave_t wave) { ULOG_DEBUG("(%d:_setWaveDdsGen) wave: %d", __LINE__, wave); switch (wave) { case GEN_SIN: ad9833_setMode(hdds, MODE_SINE); break; case GEN_TRI: ad9833_setMode(hdds, MODE_TRIANGLE); break; case GEN_SQR: ad9833_setMode(hdds, MODE_SQUARE1); break; default: ULOG_ERROR("%s:%d: Unknown wave type: %d", __FILE__, __LINE__, wave); break; } } static void _setEnabledDdsGen(FG_handle_t *hfg, GEN_fg_t *gen) { ULOG_DEBUG("(%d:_setEnabledDdsGen) enabled: %d", __LINE__, gen->enabled); switch (gen->enabled) { case FALSE: ad9833_setMode(&hfg->hdds, MODE_OFF); led_off(&hfg->hled); break; case TRUE: _setWaveDdsGen(&hfg->hdds, gen->wave); led_on(&hfg->hled); break; default: ULOG_ERROR("%s:%d: Value out of range: %d", __FILE__, __LINE__, gen->enabled); break; } } static void _setFreqPwmGen(timer_handle_t *hpwm, uint32_t freq) { } static void _setPhasePwmGen(timer_handle_t *hpwm, uint16_t phas) { } static void _setDutyPwmGen(timer_handle_t *hpwm, uint8_t duty) { } static void _setEnabledPwmGen(PWM_handle_t *hpwm, bool_t en) { } void setFreq(GEN_sig_t *gen, GEN_channel_t channel) { switch (gen->type) { case GEN_FG_TYPE: _setFreqDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->frequency); break; case GEN_PWM_TYPE: _setFreqPwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->frequency); break; default: ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type); break; } } void setAmplitude(GEN_sig_t *gen, GEN_channel_t channel) { switch (gen->type) { case GEN_FG_TYPE: _setAmpliude(&dds_gen[ch_to_gen_ch[channel]].hampl, ((GEN_fg_t *)gen->gen)->amplitude); break; case GEN_PWM_TYPE: _setAmpliude(&pwm_gen[ch_to_gen_ch[channel]].hampl, ((GEN_pwm_t *)gen->gen)->amplitude); break; default: ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type); break; } } void setOfsset(GEN_sig_t *gen, GEN_channel_t channel) { switch (gen->type) { case GEN_FG_TYPE: _setOffset(&dds_gen[ch_to_gen_ch[channel]].hoffs, ((GEN_fg_t *)gen->gen)->offset); break; case GEN_PWM_TYPE: _setOffset(&pwm_gen[ch_to_gen_ch[channel]].hoffs, ((GEN_pwm_t *)gen->gen)->offset); break; default: ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type); break; } } void setPhase(GEN_sig_t *gen, GEN_channel_t channel) { switch (gen->type) { case GEN_FG_TYPE: _setPhaseDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->phase); break; case GEN_PWM_TYPE: _setPhasePwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->phase); break; default: ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type); break; } } void setWave(GEN_sig_t *gen, GEN_channel_t channel) { switch (gen->type) { case GEN_FG_TYPE: _setWaveDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->wave); break; default: ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type); break; } } void setDuty(GEN_sig_t *gen, GEN_channel_t channel) { switch (gen->type) { case GEN_PWM_TYPE: _setDutyPwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->duty); break; default: ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type); break; } } void setEnabled(GEN_sig_t *gen, GEN_channel_t channel) { switch (gen->type) { case GEN_FG_TYPE: _setEnabledDdsGen(&dds_gen[ch_to_gen_ch[channel]], ((GEN_fg_t *)gen->gen)); break; case GEN_PWM_TYPE: _setEnabledPwmGen(&pwm_gen[ch_to_gen_ch[channel]], ((GEN_pwm_t *)gen->gen)->enabled); break; default: ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->type); break; } } void setLink(GEN_sig_t *source_gen, GEN_channel_t source_ch, GEN_sig_t *dest_gen, GEN_channel_t dest_ch) { }