diff --git a/firmware/func_gen_stm32f303re_nucleo/.mxproject b/firmware/func_gen_stm32f303re_nucleo/.mxproject index b01b633..027aaa1 100644 --- a/firmware/func_gen_stm32f303re_nucleo/.mxproject +++ b/firmware/func_gen_stm32f303re_nucleo/.mxproject @@ -1,29 +1,31 @@ +[PreviousLibFiles] +LibFiles=Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_spi.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_spi_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_def.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_bus.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_crs.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_system.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_utils.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_exti.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_exti.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_usart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart_ex.h;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart_ex.c;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_spi.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_spi_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_def.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_bus.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_crs.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_system.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_utils.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_exti.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_exti.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_usart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32F3xx\Include\stm32f303xe.h;Drivers\CMSIS\Device\ST\STM32F3xx\Include\stm32f3xx.h;Drivers\CMSIS\Device\ST\STM32F3xx\Include\system_stm32f3xx.h;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; + +[PreviousUsedMakefileFiles] +SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\spi.c;Core\Src\usart.c;Core\Src\stm32f3xx_it.c;Core\Src\stm32f3xx_hal_msp.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Core\Src\system_stm32f3xx.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_spi_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Core\Src\system_stm32f3xx.c;;; +HeaderPath=Drivers\STM32F3xx_HAL_Driver\Inc;Drivers\STM32F3xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F3xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F303xE;USE_HAL_DRIVER;USE_HAL_DRIVER; + [PreviousGenFiles] AdvancedFolderStructure=true -HeaderFileListSize=5 +HeaderFileListSize=6 HeaderFiles#0=..\Core\Inc\gpio.h -HeaderFiles#1=..\Core\Inc\usart.h -HeaderFiles#2=..\Core\Inc\stm32f3xx_it.h -HeaderFiles#3=..\Core\Inc\stm32f3xx_hal_conf.h -HeaderFiles#4=..\Core\Inc\main.h +HeaderFiles#1=..\Core\Inc\spi.h +HeaderFiles#2=..\Core\Inc\usart.h +HeaderFiles#3=..\Core\Inc\stm32f3xx_it.h +HeaderFiles#4=..\Core\Inc\stm32f3xx_hal_conf.h +HeaderFiles#5=..\Core\Inc\main.h HeaderFolderListSize=1 HeaderPath#0=..\Core\Inc HeaderFiles=; -SourceFileListSize=5 +SourceFileListSize=6 SourceFiles#0=..\Core\Src\gpio.c -SourceFiles#1=..\Core\Src\usart.c -SourceFiles#2=..\Core\Src\stm32f3xx_it.c -SourceFiles#3=..\Core\Src\stm32f3xx_hal_msp.c -SourceFiles#4=..\Core\Src\main.c +SourceFiles#1=..\Core\Src\spi.c +SourceFiles#2=..\Core\Src\usart.c +SourceFiles#3=..\Core\Src\stm32f3xx_it.c +SourceFiles#4=..\Core\Src\stm32f3xx_hal_msp.c +SourceFiles#5=..\Core\Src\main.c SourceFolderListSize=1 SourcePath#0=..\Core\Src SourceFiles=; -[PreviousLibFiles] -LibFiles=Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_usart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_def.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_bus.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_crs.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_system.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_utils.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_exti.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_exti.h;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_tim_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_usart.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_uart_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_def.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_rcc_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_bus.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_rcc.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_crs.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_system.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_utils.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_gpio_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_gpio.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_dma.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_cortex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_pwr_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_pwr.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_flash_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_i2c_ex.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_hal_exti.h;Drivers\STM32F3xx_HAL_Driver\Inc\stm32f3xx_ll_exti.h;Drivers\CMSIS\Device\ST\STM32F3xx\Include\stm32f303xe.h;Drivers\CMSIS\Device\ST\STM32F3xx\Include\stm32f3xx.h;Drivers\CMSIS\Device\ST\STM32F3xx\Include\system_stm32f3xx.h;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h; - -[PreviousUsedMakefileFiles] -SourceFiles=Core\Src\main.c;Core\Src\gpio.c;Core\Src\usart.c;Core\Src\stm32f3xx_it.c;Core\Src\stm32f3xx_hal_msp.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Core\Src\system_stm32f3xx.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_tim_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_uart_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_rcc_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_gpio.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_dma.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_cortex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_pwr_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_flash_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_i2c_ex.c;Drivers\STM32F3xx_HAL_Driver\Src\stm32f3xx_hal_exti.c;Drivers\CMSIS\Device\ST\STM32F3xx\Source\Templates\system_stm32f3xx.c;Core\Src\system_stm32f3xx.c;;; -HeaderPath=Drivers\STM32F3xx_HAL_Driver\Inc;Drivers\STM32F3xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F3xx\Include;Drivers\CMSIS\Include;Core\Inc; -CDefines=USE_HAL_DRIVER;STM32F303xE;USE_HAL_DRIVER;USE_HAL_DRIVER; - diff --git a/firmware/func_gen_stm32f303re_nucleo/Core/Inc/spi.h b/firmware/func_gen_stm32f303re_nucleo/Core/Inc/spi.h new file mode 100644 index 0000000..522da13 --- /dev/null +++ b/firmware/func_gen_stm32f303re_nucleo/Core/Inc/spi.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.h + * @brief This file contains all the function prototypes for + * the spi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern SPI_HandleTypeDef hspi2; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SPI2_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ + diff --git a/firmware/func_gen_stm32f303re_nucleo/Core/Inc/stm32f3xx_hal_conf.h b/firmware/func_gen_stm32f303re_nucleo/Core/Inc/stm32f3xx_hal_conf.h index 94469fa..157f7a7 100644 --- a/firmware/func_gen_stm32f303re_nucleo/Core/Inc/stm32f3xx_hal_conf.h +++ b/firmware/func_gen_stm32f303re_nucleo/Core/Inc/stm32f3xx_hal_conf.h @@ -56,7 +56,7 @@ /*#define HAL_LPTIM_MODULE_ENABLED */ /*#define HAL_RNG_MODULE_ENABLED */ /*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED /*#define HAL_TIM_MODULE_ENABLED */ #define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ diff --git a/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c b/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c index 06414bb..d574d98 100644 --- a/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c +++ b/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c @@ -18,6 +18,7 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" +#include "spi.h" #include "usart.h" #include "gpio.h" @@ -58,92 +59,94 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ - /* USER CODE END SysInit */ + /* USER CODE END SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART2_UART_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART2_UART_Init(); + MX_SPI2_Init(); + /* USER CODE BEGIN 2 */ - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ while (1) { - /* USER CODE END WHILE */ + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ + /* USER CODE BEGIN 3 */ } - /* USER CODE END 3 */ + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; - PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -151,33 +154,33 @@ void SystemClock_Config(void) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { } - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ + /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/firmware/func_gen_stm32f303re_nucleo/Core/Src/spi.c b/firmware/func_gen_stm32f303re_nucleo/Core/Src/spi.c new file mode 100644 index 0000000..8dc448c --- /dev/null +++ b/firmware/func_gen_stm32f303re_nucleo/Core/Src/spi.c @@ -0,0 +1,121 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.c + * @brief This file provides code for the configuration + * of the SPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "spi.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +SPI_HandleTypeDef hspi2; + +/* SPI2 init function */ +void MX_SPI2_Init(void) +{ + + /* USER CODE BEGIN SPI2_Init 0 */ + + /* USER CODE END SPI2_Init 0 */ + + /* USER CODE BEGIN SPI2_Init 1 */ + + /* USER CODE END SPI2_Init 1 */ + hspi2.Instance = SPI2; + hspi2.Init.Mode = SPI_MODE_MASTER; + hspi2.Init.Direction = SPI_DIRECTION_2LINES; + hspi2.Init.DataSize = SPI_DATASIZE_8BIT; + hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi2.Init.NSS = SPI_NSS_SOFT; + hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_32; + hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi2.Init.TIMode = SPI_TIMODE_DISABLE; + hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi2.Init.CRCPolynomial = 7; + hspi2.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI2_Init 2 */ + + /* USER CODE END SPI2_Init 2 */ + +} + +void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(spiHandle->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspInit 0 */ + + /* USER CODE END SPI2_MspInit 0 */ + /* SPI2 clock enable */ + __HAL_RCC_SPI2_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI2_MspInit 1 */ + + /* USER CODE END SPI2_MspInit 1 */ + } +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) +{ + + if(spiHandle->Instance==SPI2) + { + /* USER CODE BEGIN SPI2_MspDeInit 0 */ + + /* USER CODE END SPI2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI2_CLK_DISABLE(); + + /**SPI2 GPIO Configuration + PB13 ------> SPI2_SCK + PB14 ------> SPI2_MISO + PB15 ------> SPI2_MOSI + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15); + + /* USER CODE BEGIN SPI2_MspDeInit 1 */ + + /* USER CODE END SPI2_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/firmware/func_gen_stm32f303re_nucleo/Makefile b/firmware/func_gen_stm32f303re_nucleo/Makefile index c975d32..a66ab33 100644 --- a/firmware/func_gen_stm32f303re_nucleo/Makefile +++ b/firmware/func_gen_stm32f303re_nucleo/Makefile @@ -1,5 +1,5 @@ ########################################################################################################################## -# File automatically-generated by tool: [projectgenerator] version: [3.17.1] date: [Sat Mar 25 17:33:18 CET 2023] +# File automatically-generated by tool: [projectgenerator] version: [3.17.1] date: [Sat Mar 25 18:27:37 CET 2023] ########################################################################################################################## # ------------------------------------------------ @@ -58,7 +58,16 @@ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_flash_ex.c \ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c.c \ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_i2c_ex.c \ Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_exti.c \ -Core/Src/system_stm32f3xx.c +Core/Src/system_stm32f3xx.c \ +Core/Src/spi.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi.c \ +Drivers/STM32F3xx_HAL_Driver/Src/stm32f3xx_hal_spi_ex.c + +###################################### +# shared libs source +###################################### +# ad9833 +C_SOURCES += ../shared_libs/drivers/ad9833/ad9833.c # ASM sources ASM_SOURCES = \ @@ -121,6 +130,8 @@ C_INCLUDES = \ -IDrivers/CMSIS/Device/ST/STM32F3xx/Include \ -IDrivers/CMSIS/Include +# ad9833 includes +C_INCLUDES += -I../shared_libs/drivers/ad9833 # compile gcc flags ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections @@ -191,4 +202,4 @@ clean: ####################################### -include $(wildcard $(BUILD_DIR)/*.d) -# *** EOF *** \ No newline at end of file +# *** EOF *** diff --git a/firmware/func_gen_stm32f303re_nucleo/func_gen_stm32f303re_nucleo.ioc b/firmware/func_gen_stm32f303re_nucleo/func_gen_stm32f303re_nucleo.ioc index e3d3f4b..3dc78a6 100644 --- a/firmware/func_gen_stm32f303re_nucleo/func_gen_stm32f303re_nucleo.ioc +++ b/firmware/func_gen_stm32f303re_nucleo/func_gen_stm32f303re_nucleo.ioc @@ -1,28 +1,33 @@ #MicroXplorer Configuration settings - do not modify File.Version=6 +GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.CPN=STM32F303RET6 Mcu.Family=STM32F3 Mcu.IP0=NVIC Mcu.IP1=RCC -Mcu.IP2=SYS -Mcu.IP3=USART2 -Mcu.IPNb=4 +Mcu.IP2=SPI2 +Mcu.IP3=SYS +Mcu.IP4=USART2 +Mcu.IPNb=5 Mcu.Name=STM32F303R(D-E)Tx Mcu.Package=LQFP64 Mcu.Pin0=PC13 Mcu.Pin1=PC14-OSC32_IN -Mcu.Pin10=PB3 -Mcu.Pin11=VP_SYS_VS_Systick +Mcu.Pin10=PB15 +Mcu.Pin11=PA13 +Mcu.Pin12=PA14 +Mcu.Pin13=PB3 +Mcu.Pin14=VP_SYS_VS_Systick Mcu.Pin2=PC15-OSC32_OUT Mcu.Pin3=PF0-OSC_IN Mcu.Pin4=PF1-OSC_OUT Mcu.Pin5=PA2 Mcu.Pin6=PA3 Mcu.Pin7=PA5 -Mcu.Pin8=PA13 -Mcu.Pin9=PA14 -Mcu.PinsNb=12 +Mcu.Pin8=PB13 +Mcu.Pin9=PB14 +Mcu.PinsNb=15 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F303RETx @@ -72,6 +77,12 @@ PA5.GPIO_PuPd=GPIO_NOPULL PA5.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA5.Locked=true PA5.Signal=GPIO_Output +PB13.Mode=Full_Duplex_Master +PB13.Signal=SPI2_SCK +PB14.Mode=Full_Duplex_Master +PB14.Signal=SPI2_MISO +PB15.Mode=Full_Duplex_Master +PB15.Signal=SPI2_MOSI PB3.GPIOParameters=GPIO_Label PB3.GPIO_Label=SWO PB3.Locked=true @@ -171,6 +182,14 @@ RCC.USBFreq_Value=72000000 RCC.VCOOutput2Freq_Value=8000000 SH.GPXTI13.0=GPIO_EXTI13 SH.GPXTI13.ConfNb=1 +SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_32 +SPI2.CalculateBaudRate=1.125 MBits/s +SPI2.DataSize=SPI_DATASIZE_8BIT +SPI2.Direction=SPI_DIRECTION_2LINES +SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,DataSize,NSSPMode,BaudRatePrescaler +SPI2.Mode=SPI_MODE_MASTER +SPI2.NSSPMode=SPI_NSS_PULSE_ENABLE +SPI2.VirtualType=VM_MASTER USART2.IPParameters=VirtualMode-Asynchronous USART2.VirtualMode-Asynchronous=VM_ASYNC VP_SYS_VS_Systick.Mode=SysTick diff --git a/firmware/shared_libs/drivers/ad9833/ad9833.c b/firmware/shared_libs/drivers/ad9833/ad9833.c new file mode 100644 index 0000000..04d5137 --- /dev/null +++ b/firmware/shared_libs/drivers/ad9833/ad9833.c @@ -0,0 +1,217 @@ +// Author: https://github.com/MajicDesigns/MD_AD9833 +#include "main.h" +#include "ad9833_def.h" +#include "ad9833.h" + +// Convenience calculations +static uint32_t ad9833_calcFreq(float f); // Calculate AD9833 frequency register from a frequency +static uint16_t ad9833_calcPhase(float a); // Calculate AD9833 phase register from phase + +static void ad9833_transmit16(ad9833_handle_t *hfg, uint16_t data) +{ + uint8_t data8; + HAL_GPIO_WritePin(hfg->cs_port, hfg->cs_pin, GPIO_PIN_RESET); + data8 = (uint8_t)((data >> 8) & 0x00FF); + HAL_SPI_Transmit(hfg->hspi, &data8, 1, 1); + data8 = (uint8_t)(data & 0x00FF); + HAL_SPI_Transmit(hfg->hspi, &data8, 1, 1); + HAL_GPIO_WritePin(hfg->cs_port, hfg->cs_pin, GPIO_PIN_SET); +} + +void ad9833_reset(ad9833_handle_t *hfg, uint8_t hold) +// Reset is done on a 1 to 0 transition +{ + hfg->_regCtl |= (1 << AD_RESET); + ad9833_transmit16(hfg, hfg->_regCtl); + + if (!hold) + { + hfg->_regCtl &= ~(1 << AD_RESET); + ad9833_transmit16(hfg, hfg->_regCtl); + } +} + +void ad9833_init(ad9833_handle_t *hfg, SPI_HandleTypeDef *hspi, GPIO_TypeDef *cs_port, uint16_t cs_pin) +// Initialise the AD9833 and then set up safe values for the AD9833 device +// Procedure from Figure 27 of in the AD9833 Data Sheet +{ + // initialise our preferred CS pin (could be same as SS) + hfg->hspi = hspi; + hfg->cs_port = cs_port; + hfg->cs_pin = cs_pin; + + hfg->_regCtl = 0; + hfg->_regCtl |= (1 << AD_B28); // always write 2 words consecutively for frequency + ad9833_transmit16(hfg, hfg->_regCtl); + + ad9833_reset(hfg, 1); // Reset and hold + ad9833_setFrequency(hfg, CHAN_0, AD_DEFAULT_FREQ); + ad9833_setFrequency(hfg, CHAN_1, AD_DEFAULT_FREQ); + ad9833_setPhase(hfg, CHAN_0, AD_DEFAULT_PHASE); + ad9833_setPhase(hfg, CHAN_1, AD_DEFAULT_PHASE); + ad9833_reset(hfg, 0); // full transition + + ad9833_setMode(hfg, MODE_OFF); + ad9833_setActiveChannelFreq(hfg, CHAN_0); + ad9833_setActiveChannelPhase(hfg, CHAN_0); +} + +void ad9833_setActiveChannelFreq(ad9833_handle_t *hfg, AD_channel_t chan) +{ + // PRINT("\nsetActiveFreq CHAN_", chan); + + switch (chan) + { + case CHAN_0: + hfg->_regCtl &= ~(1 << AD_FSELECT); + break; + case CHAN_1: + hfg->_regCtl |= (1 << AD_FSELECT); + break; + } + + ad9833_transmit16(hfg, hfg->_regCtl); +} + +AD_channel_t ad9833_getActiveChannelFreq(ad9833_handle_t *hfg) +{ + return (hfg->_regCtl & (1 << AD_FSELECT)) ? CHAN_1 : CHAN_0; +}; + +void ad9833_setActiveChannelPhase(ad9833_handle_t *hfg, AD_channel_t chan) +{ + // PRINT("\nsetActivePhase CHAN_", chan); + + switch (chan) + { + case CHAN_0: + hfg->_regCtl &= ~(1 << AD_PSELECT); + break; + case CHAN_1: + hfg->_regCtl |= (1 << AD_PSELECT); + break; + } + + ad9833_transmit16(hfg, hfg->_regCtl); +} + +AD_channel_t ad9833_getActiveChannelPhase(ad9833_handle_t *hfg) +{ + return (hfg->_regCtl & (1 << AD_PSELECT)) ? CHAN_1 : CHAN_0; +}; + +void ad9833_setMode(ad9833_handle_t *hfg, AD_mode_t mode) +{ + // PRINTS("\nsetWave "); + hfg->_mode = mode; + + switch (mode) + { + case MODE_OFF: + hfg->_regCtl &= ~(1 << AD_OPBITEN); + hfg->_regCtl &= ~(1 << AD_MODE); + hfg->_regCtl |= (1 << AD_SLEEP1); + hfg->_regCtl |= (1 << AD_SLEEP12); + break; + case MODE_SINE: + hfg->_regCtl &= ~(1 << AD_OPBITEN); + hfg->_regCtl &= ~(1 << AD_MODE); + hfg->_regCtl &= ~(1 << AD_SLEEP1); + hfg->_regCtl &= ~(1 << AD_SLEEP12); + break; + case MODE_SQUARE1: + hfg->_regCtl |= (1 << AD_OPBITEN); + hfg->_regCtl &= ~(1 << AD_MODE); + hfg->_regCtl |= (1 << AD_DIV2); + hfg->_regCtl &= ~(1 << AD_SLEEP1); + hfg->_regCtl &= ~(1 << AD_SLEEP12); + break; + case MODE_SQUARE2: + hfg->_regCtl |= (1 << AD_OPBITEN); + hfg->_regCtl &= ~(1 << AD_MODE); + hfg->_regCtl &= ~(1 << AD_DIV2); + hfg->_regCtl &= ~(1 << AD_SLEEP1); + hfg->_regCtl &= ~(1 << AD_SLEEP12); + break; + case MODE_TRIANGLE: + hfg->_regCtl &= ~(1 << AD_OPBITEN); + hfg->_regCtl |= (1 << AD_MODE); + hfg->_regCtl &= ~(1 << AD_SLEEP1); + hfg->_regCtl &= ~(1 << AD_SLEEP12); + break; + } + + ad9833_transmit16(hfg, hfg->_regCtl); +} + +static uint32_t ad9833_calcFreq(float f) +// Calculate register value for AD9833 frequency register from a frequency +{ + return (uint32_t)((f * AD_2POW28 / AD_MCLK) + 0.5); +} + +static uint16_t ad9833_calcPhase(float a) +// Calculate the value for AD9833 phase register from given phase in tenths of a degree +{ + return (uint16_t)((512.0 * (a / 10) / 45) + 0.5); +} + +void ad9833_setFrequency(ad9833_handle_t *hfg, AD_channel_t chan, float freq) +{ + // PRINT("\nsetFreq CHAN_", chan); + uint16_t freq_channel = 0; + + hfg->_freq[chan] = freq; + + hfg->_regFreq[chan] = ad9833_calcFreq(freq); + + // select the address mask + + switch (chan) + { + case CHAN_0: + freq_channel = SEL_FREQ0; + break; + case CHAN_1: + freq_channel = SEL_FREQ1; + break; + default: + // error + break; + } + + // Assumes B28 is on so we can send consecutive words + // B28 is set by default for the library, so just send it here + // Now send the two parts of the frequency 14 bits at a time, + // LSBs first + + // spiSend(_regCtl); // set B28 + ad9833_transmit16(hfg, freq_channel | (uint16_t)(hfg->_regFreq[chan] & 0x3fff)); + ad9833_transmit16(hfg, freq_channel | (uint16_t)((hfg->_regFreq[chan] >> 14) & 0x3fff)); +} + +void ad9833_setPhase(ad9833_handle_t *hfg, AD_channel_t chan, uint16_t phase) +{ + // PRINT("\nsetPhase CHAN_", chan); + uint16_t phase_channel = 0; + + hfg->_phase[chan] = phase; + hfg->_regPhase[chan] = ad9833_calcPhase(phase); + + // select the address mask + switch (chan) + { + case CHAN_0: + phase_channel = SEL_PHASE0; + break; + case CHAN_1: + phase_channel = SEL_PHASE1; + break; + default: + // error + break; + } + + // Now send the phase as 12 bits with appropriate address bits + ad9833_transmit16(hfg, phase_channel | (0xfff & hfg->_regPhase[chan])); +} \ No newline at end of file diff --git a/firmware/shared_libs/drivers/ad9833/ad9833.h b/firmware/shared_libs/drivers/ad9833/ad9833.h new file mode 100644 index 0000000..fb465a3 --- /dev/null +++ b/firmware/shared_libs/drivers/ad9833/ad9833.h @@ -0,0 +1,56 @@ +#pragma once + +#define AD_DEFAULT_FREQ 1000U ///< Default initialisation frequency (Hz) +#define AD_DEFAULT_PHASE 0 ///< Default initialisation phase angle (degrees) +#define AD_MCLK 25000000UL ///< Clock speed of the AD9833 reference clock in Hz +/** + * Channel enumerated type. + * + * This enumerated type is used with the to specify which channel + * is being invoked on operations that could be channel related. + */ +typedef enum +{ + CHAN_0 = 0, ///< Channel 0 definition + CHAN_1 = 1, ///< Channel 1 definition +} AD_channel_t; + +/** + * Output mode request enumerated type. + * + * This enumerated type is used with the \ref setMode() methods to identify + * the mode request. + */ +typedef enum +{ + MODE_OFF, ///< Set output all off + MODE_SINE, ///< Set output to a sine wave at selected frequency + MODE_SQUARE1, ///< Set output to a square wave at selected frequency + MODE_SQUARE2, ///< Set output to a square wave at half selected frequency + MODE_TRIANGLE, ///< Set output to a triangle wave at selected frequency +} AD_mode_t; + +typedef struct +{ + uint16_t _regCtl; // control register image + uint32_t _regFreq[2]; // frequency registers + uint32_t _regPhase[2]; // phase registers + + AD_mode_t _mode; // last set mode + float _freq[2]; // last frequencies set + uint16_t _phase[2]; // last phase setting + + SPI_HandleTypeDef *hspi; + GPIO_TypeDef *cs_port; + uint16_t cs_pin; +} ad9833_handle_t; + +void ad9833_init(ad9833_handle_t *hfg, SPI_HandleTypeDef *hspi, GPIO_TypeDef *cs_port, uint16_t cs_pin); +void ad9833_reset(ad9833_handle_t *hfg, uint8_t hold); +void ad9833_setActiveChannelFreq(ad9833_handle_t *hfg, AD_channel_t chan); +AD_channel_t ad9833_getActiveChannelFreq(ad9833_handle_t *hfg); +void ad9833_setActiveChannelPhase(ad9833_handle_t *hfg, AD_channel_t chan); +AD_channel_t ad9833_getActiveChannelPhase(ad9833_handle_t *hfg); +void ad9833_setMode(ad9833_handle_t *hfg, AD_mode_t mode); +void ad9833_setFrequency(ad9833_handle_t *hfg, AD_channel_t chan, float freq); +void ad9833_setPhase(ad9833_handle_t *hfg, AD_channel_t chan, uint16_t phase); \ No newline at end of file diff --git a/firmware/shared_libs/drivers/ad9833/ad9833_def.h b/firmware/shared_libs/drivers/ad9833/ad9833_def.h new file mode 100644 index 0000000..638cb27 --- /dev/null +++ b/firmware/shared_libs/drivers/ad9833/ad9833_def.h @@ -0,0 +1,46 @@ +// Author: https://github.com/MajicDesigns/MD_AD9833 +#pragma once + +#include "main.h" + +/** @}*/ + +// AD9833 Control Register bit definitions +#define AD_B28 13 ///< B28 = 1 allows a complete word to be loaded into a frequency register in + ///< two consecutive writes. When B28 = 0, the 28-bit frequency register + ///< operates as two 14-bit registers. +#define AD_HLB 12 ///< Control bit allows the user to continuously load the MSBs or LSBs of a + ///< frequency register while ignoring the remaining 14 bits. HLB is used + ///< in conjunction with B28; when B28 = 1, this control bit is ignored. +#define AD_FSELECT 11 ///< Defines whether the FREQ0 register or the FREQ1 register is used in + ///< the phase accumulator. +#define AD_PSELECT 10 ///< Defines whether the PHASE0 register or the PHASE1 register data is + ///< added to the output of the phase accumulator. +#define AD_RESET 8 ///< Reset = 1 resets internal registers to 0, which corresponds to an + ///< analog output of midscale. Reset = 0 disables reset. +#define AD_SLEEP1 7 ///< When SLEEP1 = 1, the internal MCLK clock is disabled, and the DAC output + ///< remains at its present value. When SLEEP1 = 0, MCLK is enabled. +#define AD_SLEEP12 6 ///< SLEEP12 = 1 powers down the on-chip DAC. SLEEP12 = 0 implies that + ///< the DAC is active. +#define AD_OPBITEN 5 ///< When OPBITEN = 1, the output of the DAC is no longer available at the + ///< VOUT pin, replaced by MSB (or MSB/2) of the DAC. When OPBITEN = 0, the + ///< DAC is connected to VOUT. +#define AD_DIV2 3 ///< When DIV2 = 1, the MSB of the DAC data is passed to the VOUT pin. When + ///< DIV2 = 0, the MSB/2 of the DAC data is output at the VOUT pin. +#define AD_MODE 1 ///< When MODE = 1, the SIN ROM is bypassed, resulting in a triangle output + ///< from the DAC. When MODE = 0, the SIN ROM is used which results in a + ///< sinusoidal signal at the output. + +// AD9833 Frequency and Phase register bit definitions +#define AD_FREQ1 15 ///< Select frequency 1 register +#define AD_FREQ0 14 ///< Select frequency 0 register +#define AD_PHASE 13 ///< Select the phase register + +// AD9833 Freq and Phase register address identifiers +#define SEL_FREQ0 (1 << AD_FREQ0) +#define SEL_FREQ1 (1 << AD_FREQ1) +#define SEL_PHASE0 (1 << AD_FREQ0 | 1 << AD_FREQ1 | 0 << AD_PHASE) +#define SEL_PHASE1 (1 << AD_FREQ0 | 1 << AD_FREQ1 | 1 << AD_PHASE) + +// AD9833 frequency and phase calculation macros +#define AD_2POW28 (1UL << 28) ///< Used when calculating output frequency