From 42c8f0bc1b5a5d12a4c7e1fc0a68b8a9f3873a49 Mon Sep 17 00:00:00 2001 From: bartool Date: Sat, 25 Mar 2023 17:58:36 +0100 Subject: [PATCH] configure vscode --- .../.cortex-debug.peripherals.state.json | 1 + .../.cortex-debug.registers.state.json | 1 + firmware/.vscode/c_cpp_properties.json | 24 + firmware/.vscode/launch.json | 33 + firmware/.vscode/tasks.json | 22 + .../func_gen_stm32f303re_nucleo/.gitignore | 1 + .../Core/Src/main.c | 201 +- .../STM32F303xE.svd | 36562 ++++++++++++++++ 8 files changed, 36744 insertions(+), 101 deletions(-) create mode 100644 firmware/.vscode/.cortex-debug.peripherals.state.json create mode 100644 firmware/.vscode/.cortex-debug.registers.state.json create mode 100644 firmware/.vscode/c_cpp_properties.json create mode 100644 firmware/.vscode/launch.json create mode 100644 firmware/.vscode/tasks.json create mode 100644 firmware/func_gen_stm32f303re_nucleo/.gitignore create mode 100644 firmware/func_gen_stm32f303re_nucleo/STM32F303xE.svd diff --git a/firmware/.vscode/.cortex-debug.peripherals.state.json b/firmware/.vscode/.cortex-debug.peripherals.state.json new file mode 100644 index 0000000..0637a08 --- /dev/null +++ b/firmware/.vscode/.cortex-debug.peripherals.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/firmware/.vscode/.cortex-debug.registers.state.json b/firmware/.vscode/.cortex-debug.registers.state.json new file mode 100644 index 0000000..0637a08 --- /dev/null +++ b/firmware/.vscode/.cortex-debug.registers.state.json @@ -0,0 +1 @@ +[] \ No newline at end of file diff --git a/firmware/.vscode/c_cpp_properties.json b/firmware/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..a2d1f65 --- /dev/null +++ b/firmware/.vscode/c_cpp_properties.json @@ -0,0 +1,24 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + "${workspaceFolder}/func_gen_stm32f303re_nucleo/Core/**", + "${workspaceFolder}/func_gen_stm32f303re_nucleo/Drivers/**", + "${workspaceFolder}/shared_libs/**" + ], + "defines": [ + "_DEBUG", + "UNICODE", + "_UNICODE", + "STM32F303xE", + "USE_HAL_DRIVER" + ], + "compilerPath": "C:/MyApps/arm-gcc/gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi-gcc.exe", + "cStandard": "c11", + "cppStandard": "gnu++17", + "intelliSenseMode": "windows-gcc-arm" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/firmware/.vscode/launch.json b/firmware/.vscode/launch.json new file mode 100644 index 0000000..4c19ddc --- /dev/null +++ b/firmware/.vscode/launch.json @@ -0,0 +1,33 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "Cortex Debug Nucloe", + "cwd": "${workspaceFolder}/func_gen_stm32f303re_nucleo/", + "executable": "./build/func_gen_stm32f303re_nucleo.elf", + "request": "launch", + "type": "cortex-debug", + "runToEntryPoint": "main", + "servertype": "jlink", + "device": "STM32F303RE", + "interface": "swd", + "runToMain": true, + "svdFile": "STM32F303xE.svd", + // "swoConfig": { + // "enabled": false, + // "cpuFrequency": 8000000, + // "swoFrequency": 2000000, + // "source": "probe", + // "decoders": [{ + // "type": "console", + // "label": "ITM", + // "port": 0 + // } + // ] + // }] + } + ] +} \ No newline at end of file diff --git a/firmware/.vscode/tasks.json b/firmware/.vscode/tasks.json new file mode 100644 index 0000000..2283851 --- /dev/null +++ b/firmware/.vscode/tasks.json @@ -0,0 +1,22 @@ +{ + // See https://go.microsoft.com/fwlink/?LinkId=733558 + // for the documentation about the tasks.json format + "version": "2.0.0", + "tasks": [ + { + "type": "shell", + "label": "f303re", + "command": "C:/MyApps/mingw64/bin/make.exe", + "options": { + "cwd": "${workspaceFolder}/func_gen_stm32f303re_nucleo" + }, + "args": [ + "-j" + ], + "group": { + "kind": "build", + "isDefault": true + } + } + ] +} \ No newline at end of file diff --git a/firmware/func_gen_stm32f303re_nucleo/.gitignore b/firmware/func_gen_stm32f303re_nucleo/.gitignore new file mode 100644 index 0000000..c795b05 --- /dev/null +++ b/firmware/func_gen_stm32f303re_nucleo/.gitignore @@ -0,0 +1 @@ +build \ No newline at end of file diff --git a/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c b/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c index 83fef54..06414bb 100644 --- a/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c +++ b/firmware/func_gen_stm32f303re_nucleo/Core/Src/main.c @@ -1,20 +1,20 @@ /* USER CODE BEGIN Header */ /** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" @@ -58,93 +58,92 @@ void SystemClock_Config(void); /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ + * @brief The application entry point. + * @retval int + */ int main(void) { - /* USER CODE BEGIN 1 */ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ - /* USER CODE END SysInit */ + /* USER CODE END SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART2_UART_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART2_UART_Init(); + /* USER CODE BEGIN 2 */ - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ + /* USER CODE BEGIN 3 */ + } + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ + * @brief System Clock Configuration + * @retval None + */ void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; - RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { - Error_Handler(); - } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; - PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART2; + PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } } /* USER CODE BEGIN 4 */ @@ -152,33 +151,33 @@ void SystemClock_Config(void) /* USER CODE END 4 */ /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ + * @brief This function is executed in case of error occurrence. + * @retval None + */ void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + { + } + /* USER CODE END Error_Handler_Debug */ } -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ void assert_failed(uint8_t *file, uint32_t line) { - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/firmware/func_gen_stm32f303re_nucleo/STM32F303xE.svd b/firmware/func_gen_stm32f303re_nucleo/STM32F303xE.svd new file mode 100644 index 0000000..aea3e99 --- /dev/null +++ b/firmware/func_gen_stm32f303re_nucleo/STM32F303xE.svd @@ -0,0 +1,36562 @@ + + +STM32F303xE +1.0 +STM32F303xE + + +8 + +32 + +0x20 +0x0 +0xFFFFFFFF + + +GPIOA +General-purpose I/Os +GPIO +0x48000000 + +0x0 +0x400 +registers + + + +MODER +MODER +GPIO port mode register +0x0 +0x20 +read-write +0x28000000 + + +MODER15 +Port x configuration bits (y = 0..15) +30 +2 + + +MODER14 +Port x configuration bits (y = 0..15) +28 +2 + + +MODER13 +Port x configuration bits (y = 0..15) +26 +2 + + +MODER12 +Port x configuration bits (y = 0..15) +24 +2 + + +MODER11 +Port x configuration bits (y = 0..15) +22 +2 + + +MODER10 +Port x configuration bits (y = 0..15) +20 +2 + + +MODER9 +Port x configuration bits (y = 0..15) +18 +2 + + +MODER8 +Port x configuration bits (y = 0..15) +16 +2 + + +MODER7 +Port x configuration bits (y = 0..15) +14 +2 + + +MODER6 +Port x configuration bits (y = 0..15) +12 +2 + + +MODER5 +Port x configuration bits (y = 0..15) +10 +2 + + +MODER4 +Port x configuration bits (y = 0..15) +8 +2 + + +MODER3 +Port x configuration bits (y = 0..15) +6 +2 + + +MODER2 +Port x configuration bits (y = 0..15) +4 +2 + + +MODER1 +Port x configuration bits (y = 0..15) +2 +2 + + +MODER0 +Port x configuration bits (y = 0..15) +0 +2 + + + + +OTYPER +OTYPER +GPIO port output type register +0x4 +0x20 +read-write +0x00000000 + + +OT15 +Port x configuration bits (y = 0..15) +15 +1 + + +OT14 +Port x configuration bits (y = 0..15) +14 +1 + + +OT13 +Port x configuration bits (y = 0..15) +13 +1 + + +OT12 +Port x configuration bits (y = 0..15) +12 +1 + + +OT11 +Port x configuration bits (y = 0..15) +11 +1 + + +OT10 +Port x configuration bits (y = 0..15) +10 +1 + + +OT9 +Port x configuration bits (y = 0..15) +9 +1 + + +OT8 +Port x configuration bits (y = 0..15) +8 +1 + + +OT7 +Port x configuration bits (y = 0..15) +7 +1 + + +OT6 +Port x configuration bits (y = 0..15) +6 +1 + + +OT5 +Port x configuration bits (y = 0..15) +5 +1 + + +OT4 +Port x configuration bits (y = 0..15) +4 +1 + + +OT3 +Port x configuration bits (y = 0..15) +3 +1 + + +OT2 +Port x configuration bits (y = 0..15) +2 +1 + + +OT1 +Port x configuration bits (y = 0..15) +1 +1 + + +OT0 +Port x configuration bits (y = 0..15) +0 +1 + + + + +OSPEEDR +OSPEEDR +GPIO port output speed register +0x8 +0x20 +read-write +0x00000000 + + +OSPEEDR15 +Port x configuration bits (y = 0..15) +30 +2 + + +OSPEEDR14 +Port x configuration bits (y = 0..15) +28 +2 + + +OSPEEDR13 +Port x configuration bits (y = 0..15) +26 +2 + + +OSPEEDR12 +Port x configuration bits (y = 0..15) +24 +2 + + +OSPEEDR11 +Port x configuration bits (y = 0..15) +22 +2 + + +OSPEEDR10 +Port x configuration bits (y = 0..15) +20 +2 + + +OSPEEDR9 +Port x configuration bits (y = 0..15) +18 +2 + + +OSPEEDR8 +Port x configuration bits (y = 0..15) +16 +2 + + +OSPEEDR7 +Port x configuration bits (y = 0..15) +14 +2 + + +OSPEEDR6 +Port x configuration bits (y = 0..15) +12 +2 + + +OSPEEDR5 +Port x configuration bits (y = 0..15) +10 +2 + + +OSPEEDR4 +Port x configuration bits (y = 0..15) +8 +2 + + +OSPEEDR3 +Port x configuration bits (y = 0..15) +6 +2 + + +OSPEEDR2 +Port x configuration bits (y = 0..15) +4 +2 + + +OSPEEDR1 +Port x configuration bits (y = 0..15) +2 +2 + + +OSPEEDR0 +Port x configuration bits (y = 0..15) +0 +2 + + + + +PUPDR +PUPDR +GPIO port pull-up/pull-down register +0xC +0x20 +read-write +0x24000000 + + +PUPDR15 +Port x configuration bits (y = 0..15) +30 +2 + + +PUPDR14 +Port x configuration bits (y = 0..15) +28 +2 + + +PUPDR13 +Port x configuration bits (y = 0..15) +26 +2 + + +PUPDR12 +Port x configuration bits (y = 0..15) +24 +2 + + +PUPDR11 +Port x configuration bits (y = 0..15) +22 +2 + + +PUPDR10 +Port x configuration bits (y = 0..15) +20 +2 + + +PUPDR9 +Port x configuration bits (y = 0..15) +18 +2 + + +PUPDR8 +Port x configuration bits (y = 0..15) +16 +2 + + +PUPDR7 +Port x configuration bits (y = 0..15) +14 +2 + + +PUPDR6 +Port x configuration bits (y = 0..15) +12 +2 + + +PUPDR5 +Port x configuration bits (y = 0..15) +10 +2 + + +PUPDR4 +Port x configuration bits (y = 0..15) +8 +2 + + +PUPDR3 +Port x configuration bits (y = 0..15) +6 +2 + + +PUPDR2 +Port x configuration bits (y = 0..15) +4 +2 + + +PUPDR1 +Port x configuration bits (y = 0..15) +2 +2 + + +PUPDR0 +Port x configuration bits (y = 0..15) +0 +2 + + + + +IDR +IDR +GPIO port input data register +0x10 +0x20 +read-only +0x00000000 + + +IDR15 +Port input data (y = 0..15) +15 +1 + + +IDR14 +Port input data (y = 0..15) +14 +1 + + +IDR13 +Port input data (y = 0..15) +13 +1 + + +IDR12 +Port input data (y = 0..15) +12 +1 + + +IDR11 +Port input data (y = 0..15) +11 +1 + + +IDR10 +Port input data (y = 0..15) +10 +1 + + +IDR9 +Port input data (y = 0..15) +9 +1 + + +IDR8 +Port input data (y = 0..15) +8 +1 + + +IDR7 +Port input data (y = 0..15) +7 +1 + + +IDR6 +Port input data (y = 0..15) +6 +1 + + +IDR5 +Port input data (y = 0..15) +5 +1 + + +IDR4 +Port input data (y = 0..15) +4 +1 + + +IDR3 +Port input data (y = 0..15) +3 +1 + + +IDR2 +Port input data (y = 0..15) +2 +1 + + +IDR1 +Port input data (y = 0..15) +1 +1 + + +IDR0 +Port input data (y = 0..15) +0 +1 + + + + +ODR +ODR +GPIO port output data register +0x14 +0x20 +read-write +0x00000000 + + +ODR15 +Port output data (y = 0..15) +15 +1 + + +ODR14 +Port output data (y = 0..15) +14 +1 + + +ODR13 +Port output data (y = 0..15) +13 +1 + + +ODR12 +Port output data (y = 0..15) +12 +1 + + +ODR11 +Port output data (y = 0..15) +11 +1 + + +ODR10 +Port output data (y = 0..15) +10 +1 + + +ODR9 +Port output data (y = 0..15) +9 +1 + + +ODR8 +Port output data (y = 0..15) +8 +1 + + +ODR7 +Port output data (y = 0..15) +7 +1 + + +ODR6 +Port output data (y = 0..15) +6 +1 + + +ODR5 +Port output data (y = 0..15) +5 +1 + + +ODR4 +Port output data (y = 0..15) +4 +1 + + +ODR3 +Port output data (y = 0..15) +3 +1 + + +ODR2 +Port output data (y = 0..15) +2 +1 + + +ODR1 +Port output data (y = 0..15) +1 +1 + + +ODR0 +Port output data (y = 0..15) +0 +1 + + + + +BSRR +BSRR +GPIO port bit set/reset register +0x18 +0x20 +write-only +0x00000000 + + +BR15 +Port x reset bit y (y = 0..15) +31 +1 + + +BR14 +Port x reset bit y (y = 0..15) +30 +1 + + +BR13 +Port x reset bit y (y = 0..15) +29 +1 + + +BR12 +Port x reset bit y (y = 0..15) +28 +1 + + +BR11 +Port x reset bit y (y = 0..15) +27 +1 + + +BR10 +Port x reset bit y (y = 0..15) +26 +1 + + +BR9 +Port x reset bit y (y = 0..15) +25 +1 + + +BR8 +Port x reset bit y (y = 0..15) +24 +1 + + +BR7 +Port x reset bit y (y = 0..15) +23 +1 + + +BR6 +Port x reset bit y (y = 0..15) +22 +1 + + +BR5 +Port x reset bit y (y = 0..15) +21 +1 + + +BR4 +Port x reset bit y (y = 0..15) +20 +1 + + +BR3 +Port x reset bit y (y = 0..15) +19 +1 + + +BR2 +Port x reset bit y (y = 0..15) +18 +1 + + +BR1 +Port x reset bit y (y = 0..15) +17 +1 + + +BR0 +Port x set bit y (y= 0..15) +16 +1 + + +BS15 +Port x set bit y (y= 0..15) +15 +1 + + +BS14 +Port x set bit y (y= 0..15) +14 +1 + + +BS13 +Port x set bit y (y= 0..15) +13 +1 + + +BS12 +Port x set bit y (y= 0..15) +12 +1 + + +BS11 +Port x set bit y (y= 0..15) +11 +1 + + +BS10 +Port x set bit y (y= 0..15) +10 +1 + + +BS9 +Port x set bit y (y= 0..15) +9 +1 + + +BS8 +Port x set bit y (y= 0..15) +8 +1 + + +BS7 +Port x set bit y (y= 0..15) +7 +1 + + +BS6 +Port x set bit y (y= 0..15) +6 +1 + + +BS5 +Port x set bit y (y= 0..15) +5 +1 + + +BS4 +Port x set bit y (y= 0..15) +4 +1 + + +BS3 +Port x set bit y (y= 0..15) +3 +1 + + +BS2 +Port x set bit y (y= 0..15) +2 +1 + + +BS1 +Port x set bit y (y= 0..15) +1 +1 + + +BS0 +Port x set bit y (y= 0..15) +0 +1 + + + + +LCKR +LCKR +GPIO port configuration lock register +0x1C +0x20 +read-write +0x00000000 + + +LCKK +Lok Key +16 +1 + + +LCK15 +Port x lock bit y (y= 0..15) +15 +1 + + +LCK14 +Port x lock bit y (y= 0..15) +14 +1 + + +LCK13 +Port x lock bit y (y= 0..15) +13 +1 + + +LCK12 +Port x lock bit y (y= 0..15) +12 +1 + + +LCK11 +Port x lock bit y (y= 0..15) +11 +1 + + +LCK10 +Port x lock bit y (y= 0..15) +10 +1 + + +LCK9 +Port x lock bit y (y= 0..15) +9 +1 + + +LCK8 +Port x lock bit y (y= 0..15) +8 +1 + + +LCK7 +Port x lock bit y (y= 0..15) +7 +1 + + +LCK6 +Port x lock bit y (y= 0..15) +6 +1 + + +LCK5 +Port x lock bit y (y= 0..15) +5 +1 + + +LCK4 +Port x lock bit y (y= 0..15) +4 +1 + + +LCK3 +Port x lock bit y (y= 0..15) +3 +1 + + +LCK2 +Port x lock bit y (y= 0..15) +2 +1 + + +LCK1 +Port x lock bit y (y= 0..15) +1 +1 + + +LCK0 +Port x lock bit y (y= 0..15) +0 +1 + + + + +AFRL +AFRL +GPIO alternate function low register +0x20 +0x20 +read-write +0x00000000 + + +AFRL7 +Alternate function selection for port x bit y (y = 0..7) +28 +4 + + +AFRL6 +Alternate function selection for port x bit y (y = 0..7) +24 +4 + + +AFRL5 +Alternate function selection for port x bit y (y = 0..7) +20 +4 + + +AFRL4 +Alternate function selection for port x bit y (y = 0..7) +16 +4 + + +AFRL3 +Alternate function selection for port x bit y (y = 0..7) +12 +4 + + +AFRL2 +Alternate function selection for port x bit y (y = 0..7) +8 +4 + + +AFRL1 +Alternate function selection for port x bit y (y = 0..7) +4 +4 + + +AFRL0 +Alternate function selection for port x bit y (y = 0..7) +0 +4 + + + + +AFRH +AFRH +GPIO alternate function high register +0x24 +0x20 +read-write +0x00000000 + + +AFRH15 +Alternate function selection for port x bit y (y = 8..15) +28 +4 + + +AFRH14 +Alternate function selection for port x bit y (y = 8..15) +24 +4 + + +AFRH13 +Alternate function selection for port x bit y (y = 8..15) +20 +4 + + +AFRH12 +Alternate function selection for port x bit y (y = 8..15) +16 +4 + + +AFRH11 +Alternate function selection for port x bit y (y = 8..15) +12 +4 + + +AFRH10 +Alternate function selection for port x bit y (y = 8..15) +8 +4 + + +AFRH9 +Alternate function selection for port x bit y (y = 8..15) +4 +4 + + +AFRH8 +Alternate function selection for port x bit y (y = 8..15) +0 +4 + + + + +BRR +BRR +Port bit reset register +0x28 +0x20 +write-only +0x00000000 + + +BR0 +Port x Reset bit y +0 +1 + + +BR1 +Port x Reset bit y +1 +1 + + +BR2 +Port x Reset bit y +2 +1 + + +BR3 +Port x Reset bit y +3 +1 + + +BR4 +Port x Reset bit y +4 +1 + + +BR5 +Port x Reset bit y +5 +1 + + +BR6 +Port x Reset bit y +6 +1 + + +BR7 +Port x Reset bit y +7 +1 + + +BR8 +Port x Reset bit y +8 +1 + + +BR9 +Port x Reset bit y +9 +1 + + +BR10 +Port x Reset bit y +10 +1 + + +BR11 +Port x Reset bit y +11 +1 + + +BR12 +Port x Reset bit y +12 +1 + + +BR13 +Port x Reset bit y +13 +1 + + +BR14 +Port x Reset bit y +14 +1 + + +BR15 +Port x Reset bit y +15 +1 + + + + + + +GPIOB +General-purpose I/Os +GPIO +0x48000400 + +0x0 +0x400 +registers + + + +MODER +MODER +GPIO port mode register +0x0 +0x20 +read-write +0x00000000 + + +MODER15 +Port x configuration bits (y = 0..15) +30 +2 + + +MODER14 +Port x configuration bits (y = 0..15) +28 +2 + + +MODER13 +Port x configuration bits (y = 0..15) +26 +2 + + +MODER12 +Port x configuration bits (y = 0..15) +24 +2 + + +MODER11 +Port x configuration bits (y = 0..15) +22 +2 + + +MODER10 +Port x configuration bits (y = 0..15) +20 +2 + + +MODER9 +Port x configuration bits (y = 0..15) +18 +2 + + +MODER8 +Port x configuration bits (y = 0..15) +16 +2 + + +MODER7 +Port x configuration bits (y = 0..15) +14 +2 + + +MODER6 +Port x configuration bits (y = 0..15) +12 +2 + + +MODER5 +Port x configuration bits (y = 0..15) +10 +2 + + +MODER4 +Port x configuration bits (y = 0..15) +8 +2 + + +MODER3 +Port x configuration bits (y = 0..15) +6 +2 + + +MODER2 +Port x configuration bits (y = 0..15) +4 +2 + + +MODER1 +Port x configuration bits (y = 0..15) +2 +2 + + +MODER0 +Port x configuration bits (y = 0..15) +0 +2 + + + + +OTYPER +OTYPER +GPIO port output type register +0x4 +0x20 +read-write +0x00000000 + + +OT15 +Port x configuration bit 15 +15 +1 + + +OT14 +Port x configuration bit 14 +14 +1 + + +OT13 +Port x configuration bit 13 +13 +1 + + +OT12 +Port x configuration bit 12 +12 +1 + + +OT11 +Port x configuration bit 11 +11 +1 + + +OT10 +Port x configuration bit 10 +10 +1 + + +OT9 +Port x configuration bit 9 +9 +1 + + +OT8 +Port x configuration bit 8 +8 +1 + + +OT7 +Port x configuration bit 7 +7 +1 + + +OT6 +Port x configuration bit 6 +6 +1 + + +OT5 +Port x configuration bit 5 +5 +1 + + +OT4 +Port x configuration bit 4 +4 +1 + + +OT3 +Port x configuration bit 3 +3 +1 + + +OT2 +Port x configuration bit 2 +2 +1 + + +OT1 +Port x configuration bit 1 +1 +1 + + +OT0 +Port x configuration bit 0 +0 +1 + + + + +OSPEEDR +OSPEEDR +GPIO port output speed register +0x8 +0x20 +read-write +0x00000000 + + +OSPEEDR15 +Port x configuration bits (y = 0..15) +30 +2 + + +OSPEEDR14 +Port x configuration bits (y = 0..15) +28 +2 + + +OSPEEDR13 +Port x configuration bits (y = 0..15) +26 +2 + + +OSPEEDR12 +Port x configuration bits (y = 0..15) +24 +2 + + +OSPEEDR11 +Port x configuration bits (y = 0..15) +22 +2 + + +OSPEEDR10 +Port x configuration bits (y = 0..15) +20 +2 + + +OSPEEDR9 +Port x configuration bits (y = 0..15) +18 +2 + + +OSPEEDR8 +Port x configuration bits (y = 0..15) +16 +2 + + +OSPEEDR7 +Port x configuration bits (y = 0..15) +14 +2 + + +OSPEEDR6 +Port x configuration bits (y = 0..15) +12 +2 + + +OSPEEDR5 +Port x configuration bits (y = 0..15) +10 +2 + + +OSPEEDR4 +Port x configuration bits (y = 0..15) +8 +2 + + +OSPEEDR3 +Port x configuration bits (y = 0..15) +6 +2 + + +OSPEEDR2 +Port x configuration bits (y = 0..15) +4 +2 + + +OSPEEDR1 +Port x configuration bits (y = 0..15) +2 +2 + + +OSPEEDR0 +Port x configuration bits (y = 0..15) +0 +2 + + + + +PUPDR +PUPDR +GPIO port pull-up/pull-down register +0xC +0x20 +read-write +0x00000000 + + +PUPDR15 +Port x configuration bits (y = 0..15) +30 +2 + + +PUPDR14 +Port x configuration bits (y = 0..15) +28 +2 + + +PUPDR13 +Port x configuration bits (y = 0..15) +26 +2 + + +PUPDR12 +Port x configuration bits (y = 0..15) +24 +2 + + +PUPDR11 +Port x configuration bits (y = 0..15) +22 +2 + + +PUPDR10 +Port x configuration bits (y = 0..15) +20 +2 + + +PUPDR9 +Port x configuration bits (y = 0..15) +18 +2 + + +PUPDR8 +Port x configuration bits (y = 0..15) +16 +2 + + +PUPDR7 +Port x configuration bits (y = 0..15) +14 +2 + + +PUPDR6 +Port x configuration bits (y = 0..15) +12 +2 + + +PUPDR5 +Port x configuration bits (y = 0..15) +10 +2 + + +PUPDR4 +Port x configuration bits (y = 0..15) +8 +2 + + +PUPDR3 +Port x configuration bits (y = 0..15) +6 +2 + + +PUPDR2 +Port x configuration bits (y = 0..15) +4 +2 + + +PUPDR1 +Port x configuration bits (y = 0..15) +2 +2 + + +PUPDR0 +Port x configuration bits (y = 0..15) +0 +2 + + + + +IDR +IDR +GPIO port input data register +0x10 +0x20 +read-only +0x00000000 + + +IDR15 +Port input data (y = 0..15) +15 +1 + + +IDR14 +Port input data (y = 0..15) +14 +1 + + +IDR13 +Port input data (y = 0..15) +13 +1 + + +IDR12 +Port input data (y = 0..15) +12 +1 + + +IDR11 +Port input data (y = 0..15) +11 +1 + + +IDR10 +Port input data (y = 0..15) +10 +1 + + +IDR9 +Port input data (y = 0..15) +9 +1 + + +IDR8 +Port input data (y = 0..15) +8 +1 + + +IDR7 +Port input data (y = 0..15) +7 +1 + + +IDR6 +Port input data (y = 0..15) +6 +1 + + +IDR5 +Port input data (y = 0..15) +5 +1 + + +IDR4 +Port input data (y = 0..15) +4 +1 + + +IDR3 +Port input data (y = 0..15) +3 +1 + + +IDR2 +Port input data (y = 0..15) +2 +1 + + +IDR1 +Port input data (y = 0..15) +1 +1 + + +IDR0 +Port input data (y = 0..15) +0 +1 + + + + +ODR +ODR +GPIO port output data register +0x14 +0x20 +read-write +0x00000000 + + +ODR15 +Port output data (y = 0..15) +15 +1 + + +ODR14 +Port output data (y = 0..15) +14 +1 + + +ODR13 +Port output data (y = 0..15) +13 +1 + + +ODR12 +Port output data (y = 0..15) +12 +1 + + +ODR11 +Port output data (y = 0..15) +11 +1 + + +ODR10 +Port output data (y = 0..15) +10 +1 + + +ODR9 +Port output data (y = 0..15) +9 +1 + + +ODR8 +Port output data (y = 0..15) +8 +1 + + +ODR7 +Port output data (y = 0..15) +7 +1 + + +ODR6 +Port output data (y = 0..15) +6 +1 + + +ODR5 +Port output data (y = 0..15) +5 +1 + + +ODR4 +Port output data (y = 0..15) +4 +1 + + +ODR3 +Port output data (y = 0..15) +3 +1 + + +ODR2 +Port output data (y = 0..15) +2 +1 + + +ODR1 +Port output data (y = 0..15) +1 +1 + + +ODR0 +Port output data (y = 0..15) +0 +1 + + + + +BSRR +BSRR +GPIO port bit set/reset register +0x18 +0x20 +write-only +0x00000000 + + +BR15 +Port x reset bit y (y = 0..15) +31 +1 + + +BR14 +Port x reset bit y (y = 0..15) +30 +1 + + +BR13 +Port x reset bit y (y = 0..15) +29 +1 + + +BR12 +Port x reset bit y (y = 0..15) +28 +1 + + +BR11 +Port x reset bit y (y = 0..15) +27 +1 + + +BR10 +Port x reset bit y (y = 0..15) +26 +1 + + +BR9 +Port x reset bit y (y = 0..15) +25 +1 + + +BR8 +Port x reset bit y (y = 0..15) +24 +1 + + +BR7 +Port x reset bit y (y = 0..15) +23 +1 + + +BR6 +Port x reset bit y (y = 0..15) +22 +1 + + +BR5 +Port x reset bit y (y = 0..15) +21 +1 + + +BR4 +Port x reset bit y (y = 0..15) +20 +1 + + +BR3 +Port x reset bit y (y = 0..15) +19 +1 + + +BR2 +Port x reset bit y (y = 0..15) +18 +1 + + +BR1 +Port x reset bit y (y = 0..15) +17 +1 + + +BR0 +Port x set bit y (y= 0..15) +16 +1 + + +BS15 +Port x set bit y (y= 0..15) +15 +1 + + +BS14 +Port x set bit y (y= 0..15) +14 +1 + + +BS13 +Port x set bit y (y= 0..15) +13 +1 + + +BS12 +Port x set bit y (y= 0..15) +12 +1 + + +BS11 +Port x set bit y (y= 0..15) +11 +1 + + +BS10 +Port x set bit y (y= 0..15) +10 +1 + + +BS9 +Port x set bit y (y= 0..15) +9 +1 + + +BS8 +Port x set bit y (y= 0..15) +8 +1 + + +BS7 +Port x set bit y (y= 0..15) +7 +1 + + +BS6 +Port x set bit y (y= 0..15) +6 +1 + + +BS5 +Port x set bit y (y= 0..15) +5 +1 + + +BS4 +Port x set bit y (y= 0..15) +4 +1 + + +BS3 +Port x set bit y (y= 0..15) +3 +1 + + +BS2 +Port x set bit y (y= 0..15) +2 +1 + + +BS1 +Port x set bit y (y= 0..15) +1 +1 + + +BS0 +Port x set bit y (y= 0..15) +0 +1 + + + + +LCKR +LCKR +GPIO port configuration lock register +0x1C +0x20 +read-write +0x00000000 + + +LCKK +Lok Key +16 +1 + + +LCK15 +Port x lock bit y (y= 0..15) +15 +1 + + +LCK14 +Port x lock bit y (y= 0..15) +14 +1 + + +LCK13 +Port x lock bit y (y= 0..15) +13 +1 + + +LCK12 +Port x lock bit y (y= 0..15) +12 +1 + + +LCK11 +Port x lock bit y (y= 0..15) +11 +1 + + +LCK10 +Port x lock bit y (y= 0..15) +10 +1 + + +LCK9 +Port x lock bit y (y= 0..15) +9 +1 + + +LCK8 +Port x lock bit y (y= 0..15) +8 +1 + + +LCK7 +Port x lock bit y (y= 0..15) +7 +1 + + +LCK6 +Port x lock bit y (y= 0..15) +6 +1 + + +LCK5 +Port x lock bit y (y= 0..15) +5 +1 + + +LCK4 +Port x lock bit y (y= 0..15) +4 +1 + + +LCK3 +Port x lock bit y (y= 0..15) +3 +1 + + +LCK2 +Port x lock bit y (y= 0..15) +2 +1 + + +LCK1 +Port x lock bit y (y= 0..15) +1 +1 + + +LCK0 +Port x lock bit y (y= 0..15) +0 +1 + + + + +AFRL +AFRL +GPIO alternate function low register +0x20 +0x20 +read-write +0x00000000 + + +AFRL7 +Alternate function selection for port x bit y (y = 0..7) +28 +4 + + +AFRL6 +Alternate function selection for port x bit y (y = 0..7) +24 +4 + + +AFRL5 +Alternate function selection for port x bit y (y = 0..7) +20 +4 + + +AFRL4 +Alternate function selection for port x bit y (y = 0..7) +16 +4 + + +AFRL3 +Alternate function selection for port x bit y (y = 0..7) +12 +4 + + +AFRL2 +Alternate function selection for port x bit y (y = 0..7) +8 +4 + + +AFRL1 +Alternate function selection for port x bit y (y = 0..7) +4 +4 + + +AFRL0 +Alternate function selection for port x bit y (y = 0..7) +0 +4 + + + + +AFRH +AFRH +GPIO alternate function high register +0x24 +0x20 +read-write +0x00000000 + + +AFRH15 +Alternate function selection for port x bit y (y = 8..15) +28 +4 + + +AFRH14 +Alternate function selection for port x bit y (y = 8..15) +24 +4 + + +AFRH13 +Alternate function selection for port x bit y (y = 8..15) +20 +4 + + +AFRH12 +Alternate function selection for port x bit y (y = 8..15) +16 +4 + + +AFRH11 +Alternate function selection for port x bit y (y = 8..15) +12 +4 + + +AFRH10 +Alternate function selection for port x bit y (y = 8..15) +8 +4 + + +AFRH9 +Alternate function selection for port x bit y (y = 8..15) +4 +4 + + +AFRH8 +Alternate function selection for port x bit y (y = 8..15) +0 +4 + + + + +BRR +BRR +Port bit reset register +0x28 +0x20 +write-only +0x00000000 + + +BR0 +Port x Reset bit y +0 +1 + + +BR1 +Port x Reset bit y +1 +1 + + +BR2 +Port x Reset bit y +2 +1 + + +BR3 +Port x Reset bit y +3 +1 + + +BR4 +Port x Reset bit y +4 +1 + + +BR5 +Port x Reset bit y +5 +1 + + +BR6 +Port x Reset bit y +6 +1 + + +BR7 +Port x Reset bit y +7 +1 + + +BR8 +Port x Reset bit y +8 +1 + + +BR9 +Port x Reset bit y +9 +1 + + +BR10 +Port x Reset bit y +10 +1 + + +BR11 +Port x Reset bit y +11 +1 + + +BR12 +Port x Reset bit y +12 +1 + + +BR13 +Port x Reset bit y +13 +1 + + +BR14 +Port x Reset bit y +14 +1 + + +BR15 +Port x Reset bit y +15 +1 + + + + + + +GPIOC +0x48000800 + + +GPIOD +0x48000C00 + + +GPIOE +0x48001000 + + +GPIOF +0x48001400 + + +GPIOG +0x48001800 + + +GPIOH +0x48001C00 + + +TSC +Touch sensing controller +TSC +0x40024000 + +0x0 +0x400 +registers + + +EXTI2_TSC +EXTI Line2 and Touch sensing + interrupts +8 + + + +CR +CR +control register +0x0 +0x20 +read-write +0x00000000 + + +CTPH +Charge transfer pulse high +28 +4 + + +CTPL +Charge transfer pulse low +24 +4 + + +SSD +Spread spectrum deviation +17 +7 + + +SSE +Spread spectrum enable +16 +1 + + +SSPSC +Spread spectrum prescaler +15 +1 + + +PGPSC +pulse generator prescaler +12 +3 + + +MCV +Max count value +5 +3 + + +IODEF +I/O Default mode +4 +1 + + +SYNCPOL +Synchronization pin polarity +3 +1 + + +AM +Acquisition mode +2 +1 + + +START +Start a new acquisition +1 +1 + + +TSCE +Touch sensing controller enable +0 +1 + + + + +IER +IER +interrupt enable register +0x4 +0x20 +read-write +0x00000000 + + +MCEIE +Max count error interrupt enable +1 +1 + + +EOAIE +End of acquisition interrupt enable +0 +1 + + + + +ICR +ICR +interrupt clear register +0x8 +0x20 +read-write +0x00000000 + + +MCEIC +Max count error interrupt clear +1 +1 + + +EOAIC +End of acquisition interrupt clear +0 +1 + + + + +ISR +ISR +interrupt status register +0xC +0x20 +read-write +0x00000000 + + +MCEF +Max count error flag +1 +1 + + +EOAF +End of acquisition flag +0 +1 + + + + +IOHCR +IOHCR +I/O hysteresis control register +0x10 +0x20 +read-write +0xFFFFFFFF + + +G1_IO1 +G1_IO1 Schmitt trigger hysteresis mode +0 +1 + + +G1_IO2 +G1_IO2 Schmitt trigger hysteresis mode +1 +1 + + +G1_IO3 +G1_IO3 Schmitt trigger hysteresis mode +2 +1 + + +G1_IO4 +G1_IO4 Schmitt trigger hysteresis mode +3 +1 + + +G2_IO1 +G2_IO1 Schmitt trigger hysteresis mode +4 +1 + + +G2_IO2 +G2_IO2 Schmitt trigger hysteresis mode +5 +1 + + +G2_IO3 +G2_IO3 Schmitt trigger hysteresis mode +6 +1 + + +G2_IO4 +G2_IO4 Schmitt trigger hysteresis mode +7 +1 + + +G3_IO1 +G3_IO1 Schmitt trigger hysteresis mode +8 +1 + + +G3_IO2 +G3_IO2 Schmitt trigger hysteresis mode +9 +1 + + +G3_IO3 +G3_IO3 Schmitt trigger hysteresis mode +10 +1 + + +G3_IO4 +G3_IO4 Schmitt trigger hysteresis mode +11 +1 + + +G4_IO1 +G4_IO1 Schmitt trigger hysteresis mode +12 +1 + + +G4_IO2 +G4_IO2 Schmitt trigger hysteresis mode +13 +1 + + +G4_IO3 +G4_IO3 Schmitt trigger hysteresis mode +14 +1 + + +G4_IO4 +G4_IO4 Schmitt trigger hysteresis mode +15 +1 + + +G5_IO1 +G5_IO1 Schmitt trigger hysteresis mode +16 +1 + + +G5_IO2 +G5_IO2 Schmitt trigger hysteresis mode +17 +1 + + +G5_IO3 +G5_IO3 Schmitt trigger hysteresis mode +18 +1 + + +G5_IO4 +G5_IO4 Schmitt trigger hysteresis mode +19 +1 + + +G6_IO1 +G6_IO1 Schmitt trigger hysteresis mode +20 +1 + + +G6_IO2 +G6_IO2 Schmitt trigger hysteresis mode +21 +1 + + +G6_IO3 +G6_IO3 Schmitt trigger hysteresis mode +22 +1 + + +G6_IO4 +G6_IO4 Schmitt trigger hysteresis mode +23 +1 + + +G7_IO1 +G7_IO1 Schmitt trigger hysteresis mode +24 +1 + + +G7_IO2 +G7_IO2 Schmitt trigger hysteresis mode +25 +1 + + +G7_IO3 +G7_IO3 Schmitt trigger hysteresis mode +26 +1 + + +G7_IO4 +G7_IO4 Schmitt trigger hysteresis mode +27 +1 + + +G8_IO1 +G8_IO1 Schmitt trigger hysteresis mode +28 +1 + + +G8_IO2 +G8_IO2 Schmitt trigger hysteresis mode +29 +1 + + +G8_IO3 +G8_IO3 Schmitt trigger hysteresis mode +30 +1 + + +G8_IO4 +G8_IO4 Schmitt trigger hysteresis mode +31 +1 + + + + +IOASCR +IOASCR +I/O analog switch control register +0x18 +0x20 +read-write +0x00000000 + + +G1_IO1 +G1_IO1 analog switch enable +0 +1 + + +G1_IO2 +G1_IO2 analog switch enable +1 +1 + + +G1_IO3 +G1_IO3 analog switch enable +2 +1 + + +G1_IO4 +G1_IO4 analog switch enable +3 +1 + + +G2_IO1 +G2_IO1 analog switch enable +4 +1 + + +G2_IO2 +G2_IO2 analog switch enable +5 +1 + + +G2_IO3 +G2_IO3 analog switch enable +6 +1 + + +G2_IO4 +G2_IO4 analog switch enable +7 +1 + + +G3_IO1 +G3_IO1 analog switch enable +8 +1 + + +G3_IO2 +G3_IO2 analog switch enable +9 +1 + + +G3_IO3 +G3_IO3 analog switch enable +10 +1 + + +G3_IO4 +G3_IO4 analog switch enable +11 +1 + + +G4_IO1 +G4_IO1 analog switch enable +12 +1 + + +G4_IO2 +G4_IO2 analog switch enable +13 +1 + + +G4_IO3 +G4_IO3 analog switch enable +14 +1 + + +G4_IO4 +G4_IO4 analog switch enable +15 +1 + + +G5_IO1 +G5_IO1 analog switch enable +16 +1 + + +G5_IO2 +G5_IO2 analog switch enable +17 +1 + + +G5_IO3 +G5_IO3 analog switch enable +18 +1 + + +G5_IO4 +G5_IO4 analog switch enable +19 +1 + + +G6_IO1 +G6_IO1 analog switch enable +20 +1 + + +G6_IO2 +G6_IO2 analog switch enable +21 +1 + + +G6_IO3 +G6_IO3 analog switch enable +22 +1 + + +G6_IO4 +G6_IO4 analog switch enable +23 +1 + + +G7_IO1 +G7_IO1 analog switch enable +24 +1 + + +G7_IO2 +G7_IO2 analog switch enable +25 +1 + + +G7_IO3 +G7_IO3 analog switch enable +26 +1 + + +G7_IO4 +G7_IO4 analog switch enable +27 +1 + + +G8_IO1 +G8_IO1 analog switch enable +28 +1 + + +G8_IO2 +G8_IO2 analog switch enable +29 +1 + + +G8_IO3 +G8_IO3 analog switch enable +30 +1 + + +G8_IO4 +G8_IO4 analog switch enable +31 +1 + + + + +IOSCR +IOSCR +I/O sampling control register +0x20 +0x20 +read-write +0x00000000 + + +G1_IO1 +G1_IO1 sampling mode +0 +1 + + +G1_IO2 +G1_IO2 sampling mode +1 +1 + + +G1_IO3 +G1_IO3 sampling mode +2 +1 + + +G1_IO4 +G1_IO4 sampling mode +3 +1 + + +G2_IO1 +G2_IO1 sampling mode +4 +1 + + +G2_IO2 +G2_IO2 sampling mode +5 +1 + + +G2_IO3 +G2_IO3 sampling mode +6 +1 + + +G2_IO4 +G2_IO4 sampling mode +7 +1 + + +G3_IO1 +G3_IO1 sampling mode +8 +1 + + +G3_IO2 +G3_IO2 sampling mode +9 +1 + + +G3_IO3 +G3_IO3 sampling mode +10 +1 + + +G3_IO4 +G3_IO4 sampling mode +11 +1 + + +G4_IO1 +G4_IO1 sampling mode +12 +1 + + +G4_IO2 +G4_IO2 sampling mode +13 +1 + + +G4_IO3 +G4_IO3 sampling mode +14 +1 + + +G4_IO4 +G4_IO4 sampling mode +15 +1 + + +G5_IO1 +G5_IO1 sampling mode +16 +1 + + +G5_IO2 +G5_IO2 sampling mode +17 +1 + + +G5_IO3 +G5_IO3 sampling mode +18 +1 + + +G5_IO4 +G5_IO4 sampling mode +19 +1 + + +G6_IO1 +G6_IO1 sampling mode +20 +1 + + +G6_IO2 +G6_IO2 sampling mode +21 +1 + + +G6_IO3 +G6_IO3 sampling mode +22 +1 + + +G6_IO4 +G6_IO4 sampling mode +23 +1 + + +G7_IO1 +G7_IO1 sampling mode +24 +1 + + +G7_IO2 +G7_IO2 sampling mode +25 +1 + + +G7_IO3 +G7_IO3 sampling mode +26 +1 + + +G7_IO4 +G7_IO4 sampling mode +27 +1 + + +G8_IO1 +G8_IO1 sampling mode +28 +1 + + +G8_IO2 +G8_IO2 sampling mode +29 +1 + + +G8_IO3 +G8_IO3 sampling mode +30 +1 + + +G8_IO4 +G8_IO4 sampling mode +31 +1 + + + + +IOCCR +IOCCR +I/O channel control register +0x28 +0x20 +read-write +0x00000000 + + +G1_IO1 +G1_IO1 channel mode +0 +1 + + +G1_IO2 +G1_IO2 channel mode +1 +1 + + +G1_IO3 +G1_IO3 channel mode +2 +1 + + +G1_IO4 +G1_IO4 channel mode +3 +1 + + +G2_IO1 +G2_IO1 channel mode +4 +1 + + +G2_IO2 +G2_IO2 channel mode +5 +1 + + +G2_IO3 +G2_IO3 channel mode +6 +1 + + +G2_IO4 +G2_IO4 channel mode +7 +1 + + +G3_IO1 +G3_IO1 channel mode +8 +1 + + +G3_IO2 +G3_IO2 channel mode +9 +1 + + +G3_IO3 +G3_IO3 channel mode +10 +1 + + +G3_IO4 +G3_IO4 channel mode +11 +1 + + +G4_IO1 +G4_IO1 channel mode +12 +1 + + +G4_IO2 +G4_IO2 channel mode +13 +1 + + +G4_IO3 +G4_IO3 channel mode +14 +1 + + +G4_IO4 +G4_IO4 channel mode +15 +1 + + +G5_IO1 +G5_IO1 channel mode +16 +1 + + +G5_IO2 +G5_IO2 channel mode +17 +1 + + +G5_IO3 +G5_IO3 channel mode +18 +1 + + +G5_IO4 +G5_IO4 channel mode +19 +1 + + +G6_IO1 +G6_IO1 channel mode +20 +1 + + +G6_IO2 +G6_IO2 channel mode +21 +1 + + +G6_IO3 +G6_IO3 channel mode +22 +1 + + +G6_IO4 +G6_IO4 channel mode +23 +1 + + +G7_IO1 +G7_IO1 channel mode +24 +1 + + +G7_IO2 +G7_IO2 channel mode +25 +1 + + +G7_IO3 +G7_IO3 channel mode +26 +1 + + +G7_IO4 +G7_IO4 channel mode +27 +1 + + +G8_IO1 +G8_IO1 channel mode +28 +1 + + +G8_IO2 +G8_IO2 channel mode +29 +1 + + +G8_IO3 +G8_IO3 channel mode +30 +1 + + +G8_IO4 +G8_IO4 channel mode +31 +1 + + + + +IOGCSR +IOGCSR +I/O group control status register +0x30 +0x20 +0x00000000 + + +G8S +Analog I/O group x status +23 +1 +read-write + + +G7S +Analog I/O group x status +22 +1 +read-write + + +G6S +Analog I/O group x status +21 +1 +read-only + + +G5S +Analog I/O group x status +20 +1 +read-only + + +G4S +Analog I/O group x status +19 +1 +read-only + + +G3S +Analog I/O group x status +18 +1 +read-only + + +G2S +Analog I/O group x status +17 +1 +read-only + + +G1S +Analog I/O group x status +16 +1 +read-only + + +G8E +Analog I/O group x enable +7 +1 +read-write + + +G7E +Analog I/O group x enable +6 +1 +read-write + + +G6E +Analog I/O group x enable +5 +1 +read-write + + +G5E +Analog I/O group x enable +4 +1 +read-write + + +G4E +Analog I/O group x enable +3 +1 +read-write + + +G3E +Analog I/O group x enable +2 +1 +read-write + + +G2E +Analog I/O group x enable +1 +1 +read-write + + +G1E +Analog I/O group x enable +0 +1 +read-write + + + + +IOG1CR +IOG1CR +I/O group x counter register +0x34 +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + +IOG2CR +IOG2CR +I/O group x counter register +0x38 +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + +IOG3CR +IOG3CR +I/O group x counter register +0x3C +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + +IOG4CR +IOG4CR +I/O group x counter register +0x40 +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + +IOG5CR +IOG5CR +I/O group x counter register +0x44 +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + +IOG6CR +IOG6CR +I/O group x counter register +0x48 +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + +IOG7CR +IOG7CR +I/O group x counter register +0x4C +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + +IOG8CR +IOG8CR +I/O group x counter register +0x50 +0x20 +read-only +0x00000000 + + +CNT +Counter value +0 +14 + + + + + + +CRC +cyclic redundancy check calculation unit +CRC +0x40023000 + +0x0 +0x400 +registers + + + +DR +DR +Data register +0x0 +0x20 +read-write +0xFFFFFFFF + + +DR +Data register bits +0 +32 + + + + +IDR +IDR +Independent data register +0x4 +0x20 +read-write +0x00000000 + + +IDR +General-purpose 8-bit data register bits +0 +8 + + + + +CR +CR +Control register +0x8 +0x20 +read-write +0x00000000 + + +RESET +reset bit +0 +1 + + +POLYSIZE +Polynomial size +3 +2 + + +REV_IN +Reverse input data +5 +2 + + +REV_OUT +Reverse output data +7 +1 + + + + +INIT +INIT +Initial CRC value +0x10 +0x20 +read-write +0xFFFFFFFF + + +INIT +Programmable initial CRC value +0 +32 + + + + +POL +POL +CRC polynomial +0x14 +0x20 +read-write +0x04C11DB7 + + +POL +Programmable polynomial +0 +32 + + + + + + +Flash +Flash +Flash +0x40022000 + +0x0 +0x400 +registers + + +FLASH +Flash global interrupt +4 + + + +ACR +ACR +Flash access control register +0x0 +0x20 +0x00000030 + + +LATENCY +LATENCY +0 +3 +read-write + + +PRFTBE +PRFTBE +4 +1 +read-write + + +PRFTBS +PRFTBS +5 +1 +read-only + + + + +KEYR +KEYR +Flash key register +0x4 +0x20 +write-only +0x00000000 + + +FKEYR +Flash Key +0 +32 + + + + +OPTKEYR +OPTKEYR +Flash option key register +0x8 +0x20 +write-only +0x00000000 + + +OPTKEYR +Option byte key +0 +32 + + + + +SR +SR +Flash status register +0xC +0x20 +0x00000000 + + +EOP +End of operation +5 +1 +read-write + + +WRPRT +Write protection error +4 +1 +read-write + + +PGERR +Programming error +2 +1 +read-write + + +BSY +Busy +0 +1 +read-only + + + + +CR +CR +Flash control register +0x10 +0x20 +read-write +0x00000080 + + +FORCE_OPTLOAD +Force option byte loading +13 +1 + + +EOPIE +End of operation interrupt enable +12 +1 + + +ERRIE +Error interrupt enable +10 +1 + + +OPTWRE +Option bytes write enable +9 +1 + + +LOCK +Lock +7 +1 + + +STRT +Start +6 +1 + + +OPTER +Option byte erase +5 +1 + + +OPTPG +Option byte programming +4 +1 + + +MER +Mass erase +2 +1 + + +PER +Page erase +1 +1 + + +PG +Programming +0 +1 + + + + +AR +AR +Flash address register +0x14 +0x20 +write-only +0x00000000 + + +FAR +Flash address +0 +32 + + + + +OBR +OBR +Option byte register +0x1C +0x20 +read-only +0xFFFFFF02 + + +OPTERR +Option byte error +0 +1 + + +LEVEL1_PROT +Level 1 protection status +1 +1 + + +LEVEL2_PROT +Level 2 protection status +2 +1 + + +WDG_SW +WDG_SW +8 +1 + + +nRST_STOP +nRST_STOP +9 +1 + + +nRST_STDBY +nRST_STDBY +10 +1 + + +BOOT1 +BOOT1 +12 +1 + + +VDDA_MONITOR +VDDA_MONITOR +13 +1 + + +SRAM_PARITY_CHECK +SRAM_PARITY_CHECK +14 +1 + + +Data0 +Data0 +16 +8 + + +Data1 +Data1 +24 +8 + + + + +WRPR +WRPR +Write protection register +0x20 +0x20 +read-only +0xFFFFFFFF + + +WRP +Write protect +0 +32 + + + + + + +RCC +Reset and clock control +RCC +0x40021000 + +0x0 +0x400 +registers + + +RCC +RCC global interrupt +5 + + + +CR +CR +Clock control register +0x0 +0x20 +0x00000083 + + +HSION +Internal High Speed clock enable +0 +1 +read-write + + +HSIRDY +Internal High Speed clock ready flag +1 +1 +read-only + + +HSITRIM +Internal High Speed clock trimming +3 +5 +read-write + + +HSICAL +Internal High Speed clock Calibration +8 +8 +read-only + + +HSEON +External High Speed clock enable +16 +1 +read-write + + +HSERDY +External High Speed clock ready flag +17 +1 +read-only + + +HSEBYP +External High Speed clock Bypass +18 +1 +read-write + + +CSSON +Clock Security System enable +19 +1 +read-write + + +PLLON +PLL enable +24 +1 +read-write + + +PLLRDY +PLL clock ready flag +25 +1 +read-only + + + + +CFGR +CFGR +Clock configuration register (RCC_CFGR) +0x4 +0x20 +0x00000000 + + +SW +System clock Switch +0 +2 +read-write + + +SWS +System Clock Switch Status +2 +2 +read-only + + +HPRE +AHB prescaler +4 +4 +read-write + + +PPRE1 +APB Low speed prescaler (APB1) +8 +3 +read-write + + +PPRE2 +APB high speed prescaler (APB2) +11 +3 +read-write + + +PLLSRC +PLL entry clock source +15 +2 +read-write + + +PLLXTPRE +HSE divider for PLL entry +17 +1 +read-write + + +PLLMUL +PLL Multiplication Factor +18 +4 +read-write + + +USBPRES +USB prescaler +22 +1 +read-write + + +MCO +Microcontroller clock output +24 +3 +read-write + + +MCOF +Microcontroller Clock Output Flag +28 +1 +read-only + + +I2SSRC +I2S external clock source selection +23 +1 +read-write + + + + +CIR +CIR +Clock interrupt register (RCC_CIR) +0x8 +0x20 +0x00000000 + + +LSIRDYF +LSI Ready Interrupt flag +0 +1 +read-only + + +LSERDYF +LSE Ready Interrupt flag +1 +1 +read-only + + +HSIRDYF +HSI Ready Interrupt flag +2 +1 +read-only + + +HSERDYF +HSE Ready Interrupt flag +3 +1 +read-only + + +PLLRDYF +PLL Ready Interrupt flag +4 +1 +read-only + + +CSSF +Clock Security System Interrupt flag +7 +1 +read-only + + +LSIRDYIE +LSI Ready Interrupt Enable +8 +1 +read-write + + +LSERDYIE +LSE Ready Interrupt Enable +9 +1 +read-write + + +HSIRDYIE +HSI Ready Interrupt Enable +10 +1 +read-write + + +HSERDYIE +HSE Ready Interrupt Enable +11 +1 +read-write + + +PLLRDYIE +PLL Ready Interrupt Enable +12 +1 +read-write + + +LSIRDYC +LSI Ready Interrupt Clear +16 +1 +write-only + + +LSERDYC +LSE Ready Interrupt Clear +17 +1 +write-only + + +HSIRDYC +HSI Ready Interrupt Clear +18 +1 +write-only + + +HSERDYC +HSE Ready Interrupt Clear +19 +1 +write-only + + +PLLRDYC +PLL Ready Interrupt Clear +20 +1 +write-only + + +CSSC +Clock security system interrupt clear +23 +1 +write-only + + + + +APB2RSTR +APB2RSTR +APB2 peripheral reset register (RCC_APB2RSTR) +0xC +0x20 +read-write +0x00000000 + + +SYSCFGRST +SYSCFG and COMP reset +0 +1 + + +TIM1RST +TIM1 timer reset +11 +1 + + +SPI1RST +SPI 1 reset +12 +1 + + +TIM8RST +TIM8 timer reset +13 +1 + + +USART1RST +USART1 reset +14 +1 + + +TIM15RST +TIM15 timer reset +16 +1 + + +TIM16RST +TIM16 timer reset +17 +1 + + +TIM17RST +TIM17 timer reset +18 +1 + + + + +APB1RSTR +APB1RSTR +APB1 peripheral reset register (RCC_APB1RSTR) +0x10 +0x20 +read-write +0x00000000 + + +TIM2RST +Timer 2 reset +0 +1 + + +TIM3RST +Timer 3 reset +1 +1 + + +TIM4RST +Timer 14 reset +2 +1 + + +TIM6RST +Timer 6 reset +4 +1 + + +TIM7RST +Timer 7 reset +5 +1 + + +WWDGRST +Window watchdog reset +11 +1 + + +SPI2RST +SPI2 reset +14 +1 + + +SPI3RST +SPI3 reset +15 +1 + + +USART2RST +USART 2 reset +17 +1 + + +USART3RST +USART3 reset +18 +1 + + +UART4RST +UART 4 reset +19 +1 + + +UART5RST +UART 5 reset +20 +1 + + +I2C1RST +I2C1 reset +21 +1 + + +I2C2RST +I2C2 reset +22 +1 + + +USBRST +USB reset +23 +1 + + +CANRST +CAN reset +25 +1 + + +PWRRST +Power interface reset +28 +1 + + +DACRST +DAC interface reset +29 +1 + + +I2C3RST +I2C3 reset +30 +1 + + + + +AHBENR +AHBENR +AHB Peripheral Clock enable register (RCC_AHBENR) +0x14 +0x20 +read-write +0x00000014 + + +DMAEN +DMA1 clock enable +0 +1 + + +DMA2EN +DMA2 clock enable +1 +1 + + +SRAMEN +SRAM interface clock enable +2 +1 + + +FLITFEN +FLITF clock enable +4 +1 + + +CRCEN +CRC clock enable +6 +1 + + +IOPHEN +I/O port H clock enable +16 +1 + + +IOPAEN +I/O port A clock enable +17 +1 + + +IOPBEN +I/O port B clock enable +18 +1 + + +IOPCEN +I/O port C clock enable +19 +1 + + +IOPDEN +I/O port D clock enable +20 +1 + + +IOPEEN +I/O port E clock enable +21 +1 + + +IOPFEN +I/O port F clock enable +22 +1 + + +IOPGEN +I/O port G clock enable +23 +1 + + +TSCEN +Touch sensing controller clock enable +24 +1 + + +ADC12EN +ADC1 and ADC2 clock enable +28 +1 + + +ADC34EN +ADC3 and ADC4 clock enable +29 +1 + + + + +APB2ENR +APB2ENR +APB2 peripheral clock enable register (RCC_APB2ENR) +0x18 +0x20 +read-write +0x00000000 + + +SYSCFGEN +SYSCFG clock enable +0 +1 + + +TIM1EN +TIM1 Timer clock enable +11 +1 + + +SPI1EN +SPI 1 clock enable +12 +1 + + +TIM8EN +TIM8 Timer clock enable +13 +1 + + +USART1EN +USART1 clock enable +14 +1 + + +TIM15EN +TIM15 timer clock enable +16 +1 + + +TIM16EN +TIM16 timer clock enable +17 +1 + + +TIM17EN +TIM17 timer clock enable +18 +1 + + + + +APB1ENR +APB1ENR +APB1 peripheral clock enable register (RCC_APB1ENR) +0x1C +0x20 +read-write +0x00000000 + + +TIM2EN +Timer 2 clock enable +0 +1 + + +TIM3EN +Timer 3 clock enable +1 +1 + + +TIM4EN +Timer 4 clock enable +2 +1 + + +TIM6EN +Timer 6 clock enable +4 +1 + + +TIM7EN +Timer 7 clock enable +5 +1 + + +WWDGEN +Window watchdog clock enable +11 +1 + + +SPI2EN +SPI 2 clock enable +14 +1 + + +SPI3EN +SPI 3 clock enable +15 +1 + + +USART2EN +USART 2 clock enable +17 +1 + + +USART3EN +USART 3 clock enable +18 +1 + + +UART4EN +UART 4 clock enable +19 +1 + + +UART5EN +UART 5 clock enable +20 +1 + + +I2C1EN +I2C 1 clock enable +21 +1 + + +I2C2EN +I2C 2 clock enable +22 +1 + + +USBEN +USB clock enable +23 +1 + + +CANEN +CAN clock enable +25 +1 + + +PWREN +Power interface clock enable +28 +1 + + +DACEN +DAC interface clock enable +29 +1 + + +I2C3EN +I2C 3 clock enable +30 +1 + + + + +BDCR +BDCR +Backup domain control register (RCC_BDCR) +0x20 +0x20 +0x00000000 + + +LSEON +External Low Speed oscillator enable +0 +1 +read-write + + +LSERDY +External Low Speed oscillator ready +1 +1 +read-only + + +LSEBYP +External Low Speed oscillator bypass +2 +1 +read-write + + +LSEDRV +LSE oscillator drive capability +3 +2 +read-write + + +RTCSEL +RTC clock source selection +8 +2 +read-write + + +RTCEN +RTC clock enable +15 +1 +read-write + + +BDRST +Backup domain software reset +16 +1 +read-write + + + + +CSR +CSR +Control/status register (RCC_CSR) +0x24 +0x20 +0x0C000000 + + +LSION +Internal low speed oscillator enable +0 +1 +read-write + + +LSIRDY +Internal low speed oscillator ready +1 +1 +read-only + + +RMVF +Remove reset flag +24 +1 +read-write + + +OBLRSTF +Option byte loader reset flag +25 +1 +read-write + + +PINRSTF +PIN reset flag +26 +1 +read-write + + +PORRSTF +POR/PDR reset flag +27 +1 +read-write + + +SFTRSTF +Software reset flag +28 +1 +read-write + + +IWDGRSTF +Independent watchdog reset flag +29 +1 +read-write + + +WWDGRSTF +Window watchdog reset flag +30 +1 +read-write + + +LPWRRSTF +Low-power reset flag +31 +1 +read-write + + + + +AHBRSTR +AHBRSTR +AHB peripheral reset register +0x28 +0x20 +read-write +0x00000000 + + +IOPHRST +I/O port H reset +16 +1 + + +IOPARST +I/O port A reset +17 +1 + + +IOPBRST +I/O port B reset +18 +1 + + +IOPCRST +I/O port C reset +19 +1 + + +IOPDRST +I/O port D reset +20 +1 + + +IOPERST +I/O port E reset +21 +1 + + +IOPFRST +I/O port F reset +22 +1 + + +IOPGRST +I/O port G reset +23 +1 + + +TSCRST +Touch sensing controller reset +24 +1 + + +ADC12RST +ADC1 and ADC2 reset +28 +1 + + +ADC34RST +ADC3 and ADC4 reset +29 +1 + + + + +CFGR2 +CFGR2 +Clock configuration register 2 +0x2C +0x20 +read-write +0x00000000 + + +PREDIV +PREDIV division factor +0 +4 + + +ADC12PRES +ADC1 and ADC2 prescaler +4 +5 + + +ADC34PRES +ADC3 and ADC4 prescaler +9 +5 + + + + +CFGR3 +CFGR3 +Clock configuration register 3 +0x30 +0x20 +read-write +0x00000000 + + +USART1SW +USART1 clock source selection +0 +2 + + +I2C1SW +I2C1 clock source selection +4 +1 + + +I2C2SW +I2C2 clock source selection +5 +1 + + +I2C3SW +I2C3 clock source selection +6 +1 + + +USART2SW +USART2 clock source selection +16 +2 + + +USART3SW +USART3 clock source selection +18 +2 + + +TIM1SW +Timer1 clock source selection +8 +1 + + +TIM8SW +Timer8 clock source selection +9 +1 + + +UART4SW +UART4 clock source selection +20 +2 + + +UART5SW +UART5 clock source selection +22 +2 + + + + + + +DMA1 +DMA controller 1 +DMA +0x40020000 + +0x0 +0x400 +registers + + +DMA1_CH1 +DMA1 channel 1 interrupt +11 + + +DMA1_CH2 +DMA1 channel 2 interrupt +12 + + +DMA1_CH3 +DMA1 channel 3 interrupt +13 + + +DMA1_CH4 +DMA1 channel 4 interrupt +14 + + +DMA1_CH5 +DMA1 channel 5 interrupt +15 + + +DMA1_CH6 +DMA1 channel 6 interrupt +16 + + +DMA1_CH7 +DMA1 channel 7interrupt +17 + + + +ISR +ISR +DMA interrupt status register (DMA_ISR) +0x0 +0x20 +read-only +0x00000000 + + +GIF1 +Channel 1 Global interrupt flag +0 +1 + + +TCIF1 +Channel 1 Transfer Complete flag +1 +1 + + +HTIF1 +Channel 1 Half Transfer Complete flag +2 +1 + + +TEIF1 +Channel 1 Transfer Error flag +3 +1 + + +GIF2 +Channel 2 Global interrupt flag +4 +1 + + +TCIF2 +Channel 2 Transfer Complete flag +5 +1 + + +HTIF2 +Channel 2 Half Transfer Complete flag +6 +1 + + +TEIF2 +Channel 2 Transfer Error flag +7 +1 + + +GIF3 +Channel 3 Global interrupt flag +8 +1 + + +TCIF3 +Channel 3 Transfer Complete flag +9 +1 + + +HTIF3 +Channel 3 Half Transfer Complete flag +10 +1 + + +TEIF3 +Channel 3 Transfer Error flag +11 +1 + + +GIF4 +Channel 4 Global interrupt flag +12 +1 + + +TCIF4 +Channel 4 Transfer Complete flag +13 +1 + + +HTIF4 +Channel 4 Half Transfer Complete flag +14 +1 + + +TEIF4 +Channel 4 Transfer Error flag +15 +1 + + +GIF5 +Channel 5 Global interrupt flag +16 +1 + + +TCIF5 +Channel 5 Transfer Complete flag +17 +1 + + +HTIF5 +Channel 5 Half Transfer Complete flag +18 +1 + + +TEIF5 +Channel 5 Transfer Error flag +19 +1 + + +GIF6 +Channel 6 Global interrupt flag +20 +1 + + +TCIF6 +Channel 6 Transfer Complete flag +21 +1 + + +HTIF6 +Channel 6 Half Transfer Complete flag +22 +1 + + +TEIF6 +Channel 6 Transfer Error flag +23 +1 + + +GIF7 +Channel 7 Global interrupt flag +24 +1 + + +TCIF7 +Channel 7 Transfer Complete flag +25 +1 + + +HTIF7 +Channel 7 Half Transfer Complete flag +26 +1 + + +TEIF7 +Channel 7 Transfer Error flag +27 +1 + + + + +IFCR +IFCR +DMA interrupt flag clear register (DMA_IFCR) +0x4 +0x20 +write-only +0x00000000 + + +CGIF1 +Channel 1 Global interrupt clear +0 +1 + + +CTCIF1 +Channel 1 Transfer Complete clear +1 +1 + + +CHTIF1 +Channel 1 Half Transfer clear +2 +1 + + +CTEIF1 +Channel 1 Transfer Error clear +3 +1 + + +CGIF2 +Channel 2 Global interrupt clear +4 +1 + + +CTCIF2 +Channel 2 Transfer Complete clear +5 +1 + + +CHTIF2 +Channel 2 Half Transfer clear +6 +1 + + +CTEIF2 +Channel 2 Transfer Error clear +7 +1 + + +CGIF3 +Channel 3 Global interrupt clear +8 +1 + + +CTCIF3 +Channel 3 Transfer Complete clear +9 +1 + + +CHTIF3 +Channel 3 Half Transfer clear +10 +1 + + +CTEIF3 +Channel 3 Transfer Error clear +11 +1 + + +CGIF4 +Channel 4 Global interrupt clear +12 +1 + + +CTCIF4 +Channel 4 Transfer Complete clear +13 +1 + + +CHTIF4 +Channel 4 Half Transfer clear +14 +1 + + +CTEIF4 +Channel 4 Transfer Error clear +15 +1 + + +CGIF5 +Channel 5 Global interrupt clear +16 +1 + + +CTCIF5 +Channel 5 Transfer Complete clear +17 +1 + + +CHTIF5 +Channel 5 Half Transfer clear +18 +1 + + +CTEIF5 +Channel 5 Transfer Error clear +19 +1 + + +CGIF6 +Channel 6 Global interrupt clear +20 +1 + + +CTCIF6 +Channel 6 Transfer Complete clear +21 +1 + + +CHTIF6 +Channel 6 Half Transfer clear +22 +1 + + +CTEIF6 +Channel 6 Transfer Error clear +23 +1 + + +CGIF7 +Channel 7 Global interrupt clear +24 +1 + + +CTCIF7 +Channel 7 Transfer Complete clear +25 +1 + + +CHTIF7 +Channel 7 Half Transfer clear +26 +1 + + +CTEIF7 +Channel 7 Transfer Error clear +27 +1 + + + + +CCR1 +CCR1 +DMA channel configuration register (DMA_CCR) +0x8 +0x20 +read-write +0x00000000 + + +EN +Channel enable +0 +1 + + +TCIE +Transfer complete interrupt enable +1 +1 + + +HTIE +Half Transfer interrupt enable +2 +1 + + +TEIE +Transfer error interrupt enable +3 +1 + + +DIR +Data transfer direction +4 +1 + + +CIRC +Circular mode +5 +1 + + +PINC +Peripheral increment mode +6 +1 + + +MINC +Memory increment mode +7 +1 + + +PSIZE +Peripheral size +8 +2 + + +MSIZE +Memory size +10 +2 + + +PL +Channel Priority level +12 +2 + + +MEM2MEM +Memory to memory mode +14 +1 + + + + +CNDTR1 +CNDTR1 +DMA channel 1 number of data register +0xC +0x20 +read-write +0x00000000 + + +NDT +Number of data to transfer +0 +16 + + + + +CPAR1 +CPAR1 +DMA channel 1 peripheral address register +0x10 +0x20 +read-write +0x00000000 + + +PA +Peripheral address +0 +32 + + + + +CMAR1 +CMAR1 +DMA channel 1 memory address register +0x14 +0x20 +read-write +0x00000000 + + +MA +Memory address +0 +32 + + + + +CCR2 +CCR2 +DMA channel configuration register (DMA_CCR) +0x1C +0x20 +read-write +0x00000000 + + +EN +Channel enable +0 +1 + + +TCIE +Transfer complete interrupt enable +1 +1 + + +HTIE +Half Transfer interrupt enable +2 +1 + + +TEIE +Transfer error interrupt enable +3 +1 + + +DIR +Data transfer direction +4 +1 + + +CIRC +Circular mode +5 +1 + + +PINC +Peripheral increment mode +6 +1 + + +MINC +Memory increment mode +7 +1 + + +PSIZE +Peripheral size +8 +2 + + +MSIZE +Memory size +10 +2 + + +PL +Channel Priority level +12 +2 + + +MEM2MEM +Memory to memory mode +14 +1 + + + + +CNDTR2 +CNDTR2 +DMA channel 2 number of data register +0x20 +0x20 +read-write +0x00000000 + + +NDT +Number of data to transfer +0 +16 + + + + +CPAR2 +CPAR2 +DMA channel 2 peripheral address register +0x24 +0x20 +read-write +0x00000000 + + +PA +Peripheral address +0 +32 + + + + +CMAR2 +CMAR2 +DMA channel 2 memory address register +0x28 +0x20 +read-write +0x00000000 + + +MA +Memory address +0 +32 + + + + +CCR3 +CCR3 +DMA channel configuration register (DMA_CCR) +0x30 +0x20 +read-write +0x00000000 + + +EN +Channel enable +0 +1 + + +TCIE +Transfer complete interrupt enable +1 +1 + + +HTIE +Half Transfer interrupt enable +2 +1 + + +TEIE +Transfer error interrupt enable +3 +1 + + +DIR +Data transfer direction +4 +1 + + +CIRC +Circular mode +5 +1 + + +PINC +Peripheral increment mode +6 +1 + + +MINC +Memory increment mode +7 +1 + + +PSIZE +Peripheral size +8 +2 + + +MSIZE +Memory size +10 +2 + + +PL +Channel Priority level +12 +2 + + +MEM2MEM +Memory to memory mode +14 +1 + + + + +CNDTR3 +CNDTR3 +DMA channel 3 number of data register +0x34 +0x20 +read-write +0x00000000 + + +NDT +Number of data to transfer +0 +16 + + + + +CPAR3 +CPAR3 +DMA channel 3 peripheral address register +0x38 +0x20 +read-write +0x00000000 + + +PA +Peripheral address +0 +32 + + + + +CMAR3 +CMAR3 +DMA channel 3 memory address register +0x3C +0x20 +read-write +0x00000000 + + +MA +Memory address +0 +32 + + + + +CCR4 +CCR4 +DMA channel configuration register (DMA_CCR) +0x44 +0x20 +read-write +0x00000000 + + +EN +Channel enable +0 +1 + + +TCIE +Transfer complete interrupt enable +1 +1 + + +HTIE +Half Transfer interrupt enable +2 +1 + + +TEIE +Transfer error interrupt enable +3 +1 + + +DIR +Data transfer direction +4 +1 + + +CIRC +Circular mode +5 +1 + + +PINC +Peripheral increment mode +6 +1 + + +MINC +Memory increment mode +7 +1 + + +PSIZE +Peripheral size +8 +2 + + +MSIZE +Memory size +10 +2 + + +PL +Channel Priority level +12 +2 + + +MEM2MEM +Memory to memory mode +14 +1 + + + + +CNDTR4 +CNDTR4 +DMA channel 4 number of data register +0x48 +0x20 +read-write +0x00000000 + + +NDT +Number of data to transfer +0 +16 + + + + +CPAR4 +CPAR4 +DMA channel 4 peripheral address register +0x4C +0x20 +read-write +0x00000000 + + +PA +Peripheral address +0 +32 + + + + +CMAR4 +CMAR4 +DMA channel 4 memory address register +0x50 +0x20 +read-write +0x00000000 + + +MA +Memory address +0 +32 + + + + +CCR5 +CCR5 +DMA channel configuration register (DMA_CCR) +0x58 +0x20 +read-write +0x00000000 + + +EN +Channel enable +0 +1 + + +TCIE +Transfer complete interrupt enable +1 +1 + + +HTIE +Half Transfer interrupt enable +2 +1 + + +TEIE +Transfer error interrupt enable +3 +1 + + +DIR +Data transfer direction +4 +1 + + +CIRC +Circular mode +5 +1 + + +PINC +Peripheral increment mode +6 +1 + + +MINC +Memory increment mode +7 +1 + + +PSIZE +Peripheral size +8 +2 + + +MSIZE +Memory size +10 +2 + + +PL +Channel Priority level +12 +2 + + +MEM2MEM +Memory to memory mode +14 +1 + + + + +CNDTR5 +CNDTR5 +DMA channel 5 number of data register +0x5C +0x20 +read-write +0x00000000 + + +NDT +Number of data to transfer +0 +16 + + + + +CPAR5 +CPAR5 +DMA channel 5 peripheral address register +0x60 +0x20 +read-write +0x00000000 + + +PA +Peripheral address +0 +32 + + + + +CMAR5 +CMAR5 +DMA channel 5 memory address register +0x64 +0x20 +read-write +0x00000000 + + +MA +Memory address +0 +32 + + + + +CCR6 +CCR6 +DMA channel configuration register (DMA_CCR) +0x6C +0x20 +read-write +0x00000000 + + +EN +Channel enable +0 +1 + + +TCIE +Transfer complete interrupt enable +1 +1 + + +HTIE +Half Transfer interrupt enable +2 +1 + + +TEIE +Transfer error interrupt enable +3 +1 + + +DIR +Data transfer direction +4 +1 + + +CIRC +Circular mode +5 +1 + + +PINC +Peripheral increment mode +6 +1 + + +MINC +Memory increment mode +7 +1 + + +PSIZE +Peripheral size +8 +2 + + +MSIZE +Memory size +10 +2 + + +PL +Channel Priority level +12 +2 + + +MEM2MEM +Memory to memory mode +14 +1 + + + + +CNDTR6 +CNDTR6 +DMA channel 6 number of data register +0x70 +0x20 +read-write +0x00000000 + + +NDT +Number of data to transfer +0 +16 + + + + +CPAR6 +CPAR6 +DMA channel 6 peripheral address register +0x74 +0x20 +read-write +0x00000000 + + +PA +Peripheral address +0 +32 + + + + +CMAR6 +CMAR6 +DMA channel 6 memory address register +0x78 +0x20 +read-write +0x00000000 + + +MA +Memory address +0 +32 + + + + +CCR7 +CCR7 +DMA channel configuration register (DMA_CCR) +0x80 +0x20 +read-write +0x00000000 + + +EN +Channel enable +0 +1 + + +TCIE +Transfer complete interrupt enable +1 +1 + + +HTIE +Half Transfer interrupt enable +2 +1 + + +TEIE +Transfer error interrupt enable +3 +1 + + +DIR +Data transfer direction +4 +1 + + +CIRC +Circular mode +5 +1 + + +PINC +Peripheral increment mode +6 +1 + + +MINC +Memory increment mode +7 +1 + + +PSIZE +Peripheral size +8 +2 + + +MSIZE +Memory size +10 +2 + + +PL +Channel Priority level +12 +2 + + +MEM2MEM +Memory to memory mode +14 +1 + + + + +CNDTR7 +CNDTR7 +DMA channel 7 number of data register +0x84 +0x20 +read-write +0x00000000 + + +NDT +Number of data to transfer +0 +16 + + + + +CPAR7 +CPAR7 +DMA channel 7 peripheral address register +0x88 +0x20 +read-write +0x00000000 + + +PA +Peripheral address +0 +32 + + + + +CMAR7 +CMAR7 +DMA channel 7 memory address register +0x8C +0x20 +read-write +0x00000000 + + +MA +Memory address +0 +32 + + + + + + +DMA2 +0x40020400 + +DMA2_CH1 +DMA2 channel1 global interrupt +56 + + +DMA2_CH2 +DMA2 channel2 global interrupt +57 + + +DMA2_CH3 +DMA2 channel3 global interrupt +58 + + +DMA2_CH4 +DMA2 channel4 global interrupt +59 + + +DMA2_CH5 +DMA2 channel5 global interrupt +60 + + + +TIM2 +General purpose timer +TIMs +0x40000000 + +0x0 +0x400 +registers + + +TIM2 +TIM2 global interrupt +28 + + + +CR1 +CR1 +control register 1 +0x0 +0x20 +read-write +0x0000 + + +CEN +Counter enable +0 +1 + + +UDIS +Update disable +1 +1 + + +URS +Update request source +2 +1 + + +OPM +One-pulse mode +3 +1 + + +DIR +Direction +4 +1 + + +CMS +Center-aligned mode selection +5 +2 + + +ARPE +Auto-reload preload enable +7 +1 + + +CKD +Clock division +8 +2 + + +UIFREMAP +UIF status bit remapping +11 +1 + + + + +CR2 +CR2 +control register 2 +0x4 +0x20 +read-write +0x0000 + + +TI1S +TI1 selection +7 +1 + + +MMS +Master mode selection +4 +3 + + +CCDS +Capture/compare DMA selection +3 +1 + + + + +SMCR +SMCR +slave mode control register +0x8 +0x20 +read-write +0x0000 + + +SMS +Slave mode selection +0 +3 + + +OCCS +OCREF clear selection +3 +1 + + +TS +Trigger selection +4 +3 + + +MSM +Master/Slave mode +7 +1 + + +ETF +External trigger filter +8 +4 + + +ETPS +External trigger prescaler +12 +2 + + +ECE +External clock enable +14 +1 + + +ETP +External trigger polarity +15 +1 + + +SMS_3 +Slave mode selection bit3 +16 +1 + + + + +DIER +DIER +DMA/Interrupt enable register +0xC +0x20 +read-write +0x0000 + + +TDE +Trigger DMA request enable +14 +1 + + +CC4DE +Capture/Compare 4 DMA request enable +12 +1 + + +CC3DE +Capture/Compare 3 DMA request enable +11 +1 + + +CC2DE +Capture/Compare 2 DMA request enable +10 +1 + + +CC1DE +Capture/Compare 1 DMA request enable +9 +1 + + +UDE +Update DMA request enable +8 +1 + + +TIE +Trigger interrupt enable +6 +1 + + +CC4IE +Capture/Compare 4 interrupt enable +4 +1 + + +CC3IE +Capture/Compare 3 interrupt enable +3 +1 + + +CC2IE +Capture/Compare 2 interrupt enable +2 +1 + + +CC1IE +Capture/Compare 1 interrupt enable +1 +1 + + +UIE +Update interrupt enable +0 +1 + + + + +SR +SR +status register +0x10 +0x20 +read-write +0x0000 + + +CC4OF +Capture/Compare 4 overcapture flag +12 +1 + + +CC3OF +Capture/Compare 3 overcapture flag +11 +1 + + +CC2OF +Capture/compare 2 overcapture flag +10 +1 + + +CC1OF +Capture/Compare 1 overcapture flag +9 +1 + + +TIF +Trigger interrupt flag +6 +1 + + +CC4IF +Capture/Compare 4 interrupt flag +4 +1 + + +CC3IF +Capture/Compare 3 interrupt flag +3 +1 + + +CC2IF +Capture/Compare 2 interrupt flag +2 +1 + + +CC1IF +Capture/compare 1 interrupt flag +1 +1 + + +UIF +Update interrupt flag +0 +1 + + + + +EGR +EGR +event generation register +0x14 +0x20 +write-only +0x0000 + + +TG +Trigger generation +6 +1 + + +CC4G +Capture/compare 4 generation +4 +1 + + +CC3G +Capture/compare 3 generation +3 +1 + + +CC2G +Capture/compare 2 generation +2 +1 + + +CC1G +Capture/compare 1 generation +1 +1 + + +UG +Update generation +0 +1 + + + + +CCMR1_Output +CCMR1_Output +capture/compare mode register 1 (output mode) +0x18 +0x20 +read-write +0x00000000 + + +CC1S +Capture/Compare 1 selection +0 +2 + + +OC1FE +Output compare 1 fast enable +2 +1 + + +OC1PE +Output compare 1 preload enable +3 +1 + + +OC1M +Output compare 1 mode +4 +3 + + +OC1CE +Output compare 1 clear enable +7 +1 + + +CC2S +Capture/Compare 2 selection +8 +2 + + +OC2FE +Output compare 2 fast enable +10 +1 + + +OC2PE +Output compare 2 preload enable +11 +1 + + +OC2M +Output compare 2 mode +12 +3 + + +OC2CE +Output compare 2 clear enable +15 +1 + + +OC1M_3 +Output compare 1 mode bit 3 +16 +1 + + +OC2M_3 +Output compare 2 mode bit 3 +24 +1 + + + + +CCMR1_Input +CCMR1_Input +capture/compare mode register 1 (input mode) +CCMR1_Output +0x18 +0x20 +read-write +0x00000000 + + +IC2F +Input capture 2 filter +12 +4 + + +IC2PSC +Input capture 2 prescaler +10 +2 + + +CC2S +Capture/compare 2 selection +8 +2 + + +IC1F +Input capture 1 filter +4 +4 + + +IC1PSC +Input capture 1 prescaler +2 +2 + + +CC1S +Capture/Compare 1 selection +0 +2 + + + + +CCMR2_Output +CCMR2_Output +capture/compare mode register 2 (output mode) +0x1C +0x20 +read-write +0x00000000 + + +CC3S +Capture/Compare 3 selection +0 +2 + + +OC3FE +Output compare 3 fast enable +2 +1 + + +OC3PE +Output compare 3 preload enable +3 +1 + + +OC3M +Output compare 3 mode +4 +3 + + +OC3CE +Output compare 3 clear enable +7 +1 + + +CC4S +Capture/Compare 4 selection +8 +2 + + +OC4FE +Output compare 4 fast enable +10 +1 + + +OC4PE +Output compare 4 preload enable +11 +1 + + +OC4M +Output compare 4 mode +12 +3 + + +O24CE +Output compare 4 clear enable +15 +1 + + +OC3M_3 +Output compare 3 mode bit3 +16 +1 + + +OC4M_3 +Output compare 4 mode bit3 +24 +1 + + + + +CCMR2_Input +CCMR2_Input +capture/compare mode register 2 (input mode) +CCMR2_Output +0x1C +0x20 +read-write +0x00000000 + + +IC4F +Input capture 4 filter +12 +4 + + +IC4PSC +Input capture 4 prescaler +10 +2 + + +CC4S +Capture/Compare 4 selection +8 +2 + + +IC3F +Input capture 3 filter +4 +4 + + +IC3PSC +Input capture 3 prescaler +2 +2 + + +CC3S +Capture/Compare 3 selection +0 +2 + + + + +CCER +CCER +capture/compare enable register +0x20 +0x20 +read-write +0x0000 + + +CC1E +Capture/Compare 1 output enable +0 +1 + + +CC1P +Capture/Compare 1 output Polarity +1 +1 + + +CC1NP +Capture/Compare 1 output Polarity +3 +1 + + +CC2E +Capture/Compare 2 output enable +4 +1 + + +CC2P +Capture/Compare 2 output Polarity +5 +1 + + +CC2NP +Capture/Compare 2 output Polarity +7 +1 + + +CC3E +Capture/Compare 3 output enable +8 +1 + + +CC3P +Capture/Compare 3 output Polarity +9 +1 + + +CC3NP +Capture/Compare 3 output Polarity +11 +1 + + +CC4E +Capture/Compare 4 output enable +12 +1 + + +CC4P +Capture/Compare 3 output Polarity +13 +1 + + +CC4NP +Capture/Compare 3 output Polarity +15 +1 + + + + +CNT +CNT +counter +0x24 +0x20 +read-write +0x00000000 + + +CNTL +Low counter value +0 +16 + + +CNTH +High counter value +16 +15 + + +CNT_or_UIFCPY +if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access +31 +1 + + + + +PSC +PSC +prescaler +0x28 +0x20 +read-write +0x0000 + + +PSC +Prescaler value +0 +16 + + + + +ARR +ARR +auto-reload register +0x2C +0x20 +read-write +0x00000000 + + +ARRL +Low Auto-reload value +0 +16 + + +ARRH +High Auto-reload value +16 +16 + + + + +CCR1 +CCR1 +capture/compare register 1 +0x34 +0x20 +read-write +0x00000000 + + +CCR1L +Low Capture/Compare 1 value +0 +16 + + +CCR1H +High Capture/Compare 1 value (on TIM2) +16 +16 + + + + +CCR2 +CCR2 +capture/compare register 2 +0x38 +0x20 +read-write +0x00000000 + + +CCR2L +Low Capture/Compare 2 value +0 +16 + + +CCR2H +High Capture/Compare 2 value (on TIM2) +16 +16 + + + + +CCR3 +CCR3 +capture/compare register 3 +0x3C +0x20 +read-write +0x00000000 + + +CCR3L +Low Capture/Compare value +0 +16 + + +CCR3H +High Capture/Compare value (on TIM2) +16 +16 + + + + +CCR4 +CCR4 +capture/compare register 4 +0x40 +0x20 +read-write +0x00000000 + + +CCR4L +Low Capture/Compare value +0 +16 + + +CCR4H +High Capture/Compare value (on TIM2) +16 +16 + + + + +DCR +DCR +DMA control register +0x48 +0x20 +read-write +0x0000 + + +DBL +DMA burst length +8 +5 + + +DBA +DMA base address +0 +5 + + + + +DMAR +DMAR +DMA address for full transfer +0x4C +0x20 +read-write +0x0000 + + +DMAB +DMA register for burst accesses +0 +16 + + + + + + +TIM3 +0x40000400 + +TIM3 +TIM3 global interrupt +29 + + + +TIM4 +0x40000800 + +TIM4 +TIM4 global interrupt +30 + + + +TIM15 +General purpose timers +TIMs +0x40014000 + +0x0 +0x400 +registers + + +TIM1_BRK_TIM15 +TIM1 Break/TIM15 global + interruts +24 + + + +CR1 +CR1 +control register 1 +0x0 +0x20 +read-write +0x0000 + + +CEN +Counter enable +0 +1 + + +UDIS +Update disable +1 +1 + + +URS +Update request source +2 +1 + + +OPM +One-pulse mode +3 +1 + + +ARPE +Auto-reload preload enable +7 +1 + + +CKD +Clock division +8 +2 + + +UIFREMAP +UIF status bit remapping +11 +1 + + + + +CR2 +CR2 +control register 2 +0x4 +0x20 +read-write +0x0000 + + +CCPC +Capture/compare preloaded control +0 +1 + + +CCUS +Capture/compare control update selection +2 +1 + + +CCDS +Capture/compare DMA selection +3 +1 + + +MMS +Master mode selection +4 +3 + + +TI1S +TI1 selection +7 +1 + + +OIS1 +Output Idle state 1 +8 +1 + + +OIS1N +Output Idle state 1 +9 +1 + + +OIS2 +Output Idle state 2 +10 +1 + + + + +SMCR +SMCR +slave mode control register +0x8 +0x20 +read-write +0x0000 + + +SMS +Slave mode selection +0 +3 + + +TS +Trigger selection +4 +3 + + +MSM +Master/Slave mode +7 +1 + + +SMS_3 +Slave mode selection bit 3 +16 +1 + + + + +DIER +DIER +DMA/Interrupt enable register +0xC +0x20 +read-write +0x0000 + + +UIE +Update interrupt enable +0 +1 + + +CC1IE +Capture/Compare 1 interrupt enable +1 +1 + + +CC2IE +Capture/Compare 2 interrupt enable +2 +1 + + +COMIE +COM interrupt enable +5 +1 + + +TIE +Trigger interrupt enable +6 +1 + + +BIE +Break interrupt enable +7 +1 + + +UDE +Update DMA request enable +8 +1 + + +CC1DE +Capture/Compare 1 DMA request enable +9 +1 + + +CC2DE +Capture/Compare 2 DMA request enable +10 +1 + + +COMDE +COM DMA request enable +13 +1 + + +TDE +Trigger DMA request enable +14 +1 + + + + +SR +SR +status register +0x10 +0x20 +read-write +0x0000 + + +CC2OF +Capture/compare 2 overcapture flag +10 +1 + + +CC1OF +Capture/Compare 1 overcapture flag +9 +1 + + +BIF +Break interrupt flag +7 +1 + + +TIF +Trigger interrupt flag +6 +1 + + +COMIF +COM interrupt flag +5 +1 + + +CC2IF +Capture/Compare 2 interrupt flag +2 +1 + + +CC1IF +Capture/compare 1 interrupt flag +1 +1 + + +UIF +Update interrupt flag +0 +1 + + + + +EGR +EGR +event generation register +0x14 +0x20 +write-only +0x0000 + + +BG +Break generation +7 +1 + + +TG +Trigger generation +6 +1 + + +COMG +Capture/Compare control update generation +5 +1 + + +CC2G +Capture/compare 2 generation +2 +1 + + +CC1G +Capture/compare 1 generation +1 +1 + + +UG +Update generation +0 +1 + + + + +CCMR1_Output +CCMR1_Output +capture/compare mode register (output mode) +0x18 +0x20 +read-write +0x00000000 + + +CC1S +Capture/Compare 1 selection +0 +2 + + +OC1FE +Output Compare 1 fast enable +2 +1 + + +OC1PE +Output Compare 1 preload enable +3 +1 + + +OC1M +Output Compare 1 mode +4 +3 + + +CC2S +Capture/Compare 2 selection +8 +2 + + +OC2FE +Output Compare 2 fast enable +10 +1 + + +OC2PE +Output Compare 2 preload enable +11 +1 + + +OC2M +Output Compare 2 mode +12 +3 + + +OC1M_3 +Output Compare 1 mode bit 3 +16 +1 + + +OC2M_3 +Output Compare 2 mode bit 3 +24 +1 + + + + +CCMR1_Input +CCMR1_Input +capture/compare mode register 1 (input mode) +CCMR1_Output +0x18 +0x20 +read-write +0x00000000 + + +IC2F +Input capture 2 filter +12 +4 + + +IC2PSC +Input capture 2 prescaler +10 +2 + + +CC2S +Capture/Compare 2 selection +8 +2 + + +IC1F +Input capture 1 filter +4 +4 + + +IC1PSC +Input capture 1 prescaler +2 +2 + + +CC1S +Capture/Compare 1 selection +0 +2 + + + + +CCER +CCER +capture/compare enable register +0x20 +0x20 +read-write +0x0000 + + +CC2NP +Capture/Compare 2 output Polarity +7 +1 + + +CC2P +Capture/Compare 2 output Polarity +5 +1 + + +CC2E +Capture/Compare 2 output enable +4 +1 + + +CC1NP +Capture/Compare 1 output Polarity +3 +1 + + +CC1NE +Capture/Compare 1 complementary output enable +2 +1 + + +CC1P +Capture/Compare 1 output Polarity +1 +1 + + +CC1E +Capture/Compare 1 output enable +0 +1 + + + + +CNT +CNT +counter +0x24 +0x20 +0x00000000 + + +CNT +counter value +0 +16 +read-write + + +UIFCPY +UIF copy +31 +1 +read-only + + + + +PSC +PSC +prescaler +0x28 +0x20 +read-write +0x0000 + + +PSC +Prescaler value +0 +16 + + + + +ARR +ARR +auto-reload register +0x2C +0x20 +read-write +0x00000000 + + +ARR +Auto-reload value +0 +16 + + + + +RCR +RCR +repetition counter register +0x30 +0x20 +read-write +0x0000 + + +REP +Repetition counter value +0 +8 + + + + +CCR1 +CCR1 +capture/compare register 1 +0x34 +0x20 +read-write +0x00000000 + + +CCR1 +Capture/Compare 1 value +0 +16 + + + + +CCR2 +CCR2 +capture/compare register 2 +0x38 +0x20 +read-write +0x00000000 + + +CCR2 +Capture/Compare 2 value +0 +16 + + + + +BDTR +BDTR +break and dead-time register +0x44 +0x20 +read-write +0x0000 + + +MOE +Main output enable +15 +1 + + +AOE +Automatic output enable +14 +1 + + +BKP +Break polarity +13 +1 + + +BKE +Break enable +12 +1 + + +OSSR +Off-state selection for Run mode +11 +1 + + +OSSI +Off-state selection for Idle mode +10 +1 + + +LOCK +Lock configuration +8 +2 + + +DTG +Dead-time generator setup +0 +8 + + +BKF +Break filter +16 +4 + + + + +DCR +DCR +DMA control register +0x48 +0x20 +read-write +0x0000 + + +DBL +DMA burst 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value +0 +16 +read-write + + +UIFCPY +UIF Copy +31 +1 +read-only + + + + +PSC +PSC +prescaler +0x28 +0x20 +read-write +0x0000 + + +PSC +Prescaler value +0 +16 + + + + +ARR +ARR +auto-reload register +0x2C +0x20 +read-write +0x00000000 + + +ARR +Auto-reload value +0 +16 + + + + +RCR +RCR +repetition counter register +0x30 +0x20 +read-write +0x0000 + + +REP +Repetition counter value +0 +8 + + + + +CCR1 +CCR1 +capture/compare register 1 +0x34 +0x20 +read-write +0x00000000 + + +CCR1 +Capture/Compare 1 value +0 +16 + + + + +BDTR +BDTR +break and dead-time register +0x44 +0x20 +read-write +0x0000 + + +DTG +Dead-time generator setup +0 +8 + + +LOCK +Lock configuration +8 +2 + + +OSSI +Off-state selection for Idle mode +10 +1 + + +OSSR +Off-state selection for Run mode +11 +1 + + +BKE +Break enable +12 +1 + + +BKP +Break polarity +13 +1 + + +AOE +Automatic output enable +14 +1 + + +MOE +Main output enable +15 +1 + + +BKF +Break filter +16 +4 + + + + +DCR +DCR +DMA control register +0x48 +0x20 +read-write +0x0000 + + +DBL +DMA burst length +8 +5 + + +DBA +DMA base address +0 +5 + + + + +DMAR +DMAR +DMA address for full transfer +0x4C +0x20 +read-write +0x0000 + + +DMAB +DMA register for burst accesses +0 +16 + + + + +OR +OR +option register +0x50 +0x20 +read-write +0x0000 + + + + +TIM17 +General purpose timer +TIMs +0x40014800 + +0x0 +0x400 +registers + + +TIM1_TRG_COM_TIM17 +TIM1 trigger and commutation/TIM17 + interrupts +26 + + + +CR1 +CR1 +control register 1 +0x0 +0x20 +read-write +0x0000 + + +CEN +Counter enable +0 +1 + + +UDIS +Update disable +1 +1 + + +URS +Update request source +2 +1 + + +OPM +One-pulse mode +3 +1 + + +ARPE +Auto-reload preload enable +7 +1 + + +CKD +Clock division +8 +2 + + +UIFREMAP +UIF status bit remapping +11 +1 + + + + +CR2 +CR2 +control register 2 +0x4 +0x20 +read-write +0x0000 + + +OIS1N +Output Idle state 1 +9 +1 + + +OIS1 +Output Idle state 1 +8 +1 + + +CCDS +Capture/compare DMA selection +3 +1 + + +CCUS +Capture/compare control update selection +2 +1 + + +CCPC +Capture/compare preloaded control +0 +1 + + + + +DIER +DIER +DMA/Interrupt enable register +0xC +0x20 +read-write +0x0000 + + +UIE +Update interrupt enable +0 +1 + + +CC1IE +Capture/Compare 1 interrupt enable +1 +1 + + +COMIE +COM interrupt enable +5 +1 + + +TIE +Trigger interrupt enable +6 +1 + + +BIE +Break interrupt enable +7 +1 + + +UDE +Update DMA request enable +8 +1 + + +CC1DE +Capture/Compare 1 DMA request enable +9 +1 + + +COMDE +COM DMA request enable +13 +1 + + +TDE +Trigger DMA request enable +14 +1 + + + + +SR +SR +status register +0x10 +0x20 +read-write +0x0000 + + +CC1OF +Capture/Compare 1 overcapture flag +9 +1 + + +BIF +Break interrupt flag +7 +1 + + +TIF +Trigger interrupt flag +6 +1 + + +COMIF +COM interrupt flag +5 +1 + + +CC1IF +Capture/compare 1 interrupt flag +1 +1 + + +UIF +Update interrupt flag +0 +1 + + + + +EGR +EGR +event generation register +0x14 +0x20 +write-only +0x0000 + + +BG +Break generation +7 +1 + + +TG +Trigger generation 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+MOE +Main output enable +15 +1 + + +BKF +Break filter +16 +4 + + + + +DCR +DCR +DMA control register +0x48 +0x20 +read-write +0x0000 + + +DBL +DMA burst length +8 +5 + + +DBA +DMA base address +0 +5 + + + + +DMAR +DMAR +DMA address for full transfer +0x4C +0x20 +read-write +0x0000 + + +DMAB +DMA register for burst accesses +0 +16 + + + + + + +USART1 +Universal synchronous asynchronous receiver transmitter +USART +0x40013800 + +0x0 +0x400 +registers + + +USART1_EXTI25 +USART1 global interrupt and EXTI Line 25 + interrupt +37 + + + +CR1 +CR1 +Control register 1 +0x0 +0x20 +read-write +0x0000 + + +EOBIE +End of Block interrupt enable +27 +1 + + +RTOIE +Receiver timeout interrupt enable +26 +1 + + +DEAT +Driver Enable assertion time +21 +5 + + +DEDT +Driver Enable deassertion time +16 +5 + + +OVER8 +Oversampling mode +15 +1 + + +CMIE +Character match interrupt enable +14 +1 + + +MME +Mute mode enable +13 +1 + + +M +Word length +12 +1 + + +WAKE +Receiver wakeup method +11 +1 + + +PCE +Parity control enable +10 +1 + + +PS +Parity selection +9 +1 + + +PEIE +PE interrupt enable +8 +1 + + +TXEIE +interrupt enable +7 +1 + + +TCIE +Transmission complete interrupt enable +6 +1 + + +RXNEIE +RXNE interrupt enable +5 +1 + + +IDLEIE +IDLE interrupt enable +4 +1 + + +TE +Transmitter enable +3 +1 + + +RE +Receiver enable +2 +1 + + +UESM +USART enable in Stop mode +1 +1 + + +UE +USART enable +0 +1 + + + + +CR2 +CR2 +Control register 2 +0x4 +0x20 +read-write +0x0000 + + +ADD4 +Address of the USART node +28 +4 + + +ADD0 +Address of the USART node +24 +4 + + +RTOEN +Receiver timeout enable +23 +1 + + +ABRMOD +Auto baud rate mode +21 +2 + + +ABREN +Auto baud rate enable +20 +1 + + +MSBFIRST +Most significant bit first +19 +1 + + +DATAINV +Binary data inversion +18 +1 + + +TXINV +TX pin active level inversion +17 +1 + + +RXINV +RX pin active level inversion +16 +1 + + +SWAP +Swap TX/RX pins +15 +1 + + +LINEN +LIN mode enable +14 +1 + + +STOP +STOP bits +12 +2 + + +CLKEN +Clock enable +11 +1 + + +CPOL +Clock polarity +10 +1 + + +CPHA +Clock phase +9 +1 + + +LBCL +Last bit clock pulse +8 +1 + + +LBDIE +LIN break detection interrupt enable +6 +1 + + +LBDL +LIN break detection length +5 +1 + + +ADDM7 +7-bit Address Detection/4-bit Address Detection +4 +1 + + + + +CR3 +CR3 +Control register 3 +0x8 +0x20 +read-write +0x0000 + + +WUFIE +Wakeup from Stop mode interrupt enable +22 +1 + + +WUS +Wakeup from Stop mode interrupt flag selection +20 +2 + + +SCARCNT +Smartcard auto-retry count +17 +3 + + +DEP +Driver enable polarity selection +15 +1 + + +DEM +Driver enable mode +14 +1 + + +DDRE +DMA Disable on Reception Error +13 +1 + + +OVRDIS +Overrun Disable +12 +1 + + +ONEBIT +One sample bit method enable +11 +1 + + +CTSIE +CTS interrupt enable +10 +1 + + +CTSE +CTS enable +9 +1 + + +RTSE +RTS enable +8 +1 + + +DMAT +DMA enable transmitter +7 +1 + + +DMAR +DMA enable receiver +6 +1 + + +SCEN +Smartcard mode enable +5 +1 + + +NACK +Smartcard NACK enable +4 +1 + + +HDSEL +Half-duplex selection +3 +1 + + +IRLP +IrDA low-power +2 +1 + + +IREN +IrDA mode enable +1 +1 + + +EIE +Error interrupt enable +0 +1 + + + + +BRR +BRR +Baud rate register +0xC +0x20 +read-write +0x0000 + + +DIV_Mantissa +mantissa of USARTDIV +4 +12 + + +DIV_Fraction +fraction of USARTDIV +0 +4 + + + + +GTPR +GTPR +Guard time and prescaler register +0x10 +0x20 +read-write +0x0000 + + +GT +Guard time value +8 +8 + + +PSC +Prescaler value +0 +8 + + + + +RTOR +RTOR +Receiver timeout register +0x14 +0x20 +read-write +0x0000 + + +BLEN +Block Length +24 +8 + + +RTO +Receiver timeout value +0 +24 + + + + +RQR +RQR +Request register +0x18 +0x20 +read-write +0x0000 + + +TXFRQ +Transmit data flush request +4 +1 + + +RXFRQ +Receive data flush request +3 +1 + + +MMRQ +Mute mode request +2 +1 + + +SBKRQ +Send break request +1 +1 + + +ABRRQ +Auto baud rate request +0 +1 + + + + +ISR +ISR +Interrupt & status register +0x1C +0x20 +read-only +0x00C0 + + +REACK +Receive enable acknowledge flag +22 +1 + + +TEACK +Transmit enable acknowledge flag +21 +1 + + +WUF +Wakeup from Stop mode flag +20 +1 + + +RWU +Receiver wakeup from Mute mode +19 +1 + + +SBKF +Send break flag +18 +1 + + +CMF +character match flag +17 +1 + + +BUSY +Busy flag +16 +1 + + +ABRF +Auto baud rate flag +15 +1 + + +ABRE +Auto baud rate error +14 +1 + + +EOBF +End of block flag +12 +1 + + +RTOF +Receiver timeout +11 +1 + + +CTS +CTS flag +10 +1 + + +CTSIF +CTS interrupt flag +9 +1 + + +LBDF +LIN break detection flag +8 +1 + + +TXE +Transmit data register empty +7 +1 + + +TC +Transmission complete +6 +1 + + +RXNE +Read data register not empty +5 +1 + + +IDLE +Idle line detected +4 +1 + + +ORE +Overrun error +3 +1 + + +NF +Noise detected flag +2 +1 + + +FE +Framing error +1 +1 + + +PE +Parity error +0 +1 + + + + +ICR +ICR +Interrupt flag clear register +0x20 +0x20 +read-write +0x0000 + + +WUCF +Wakeup from Stop mode clear flag +20 +1 + + +CMCF +Character match clear flag +17 +1 + + +EOBCF +End of timeout clear flag +12 +1 + + +RTOCF +Receiver timeout clear flag +11 +1 + + +CTSCF +CTS clear flag +9 +1 + + +LBDCF +LIN break detection clear flag +8 +1 + + +TCCF +Transmission complete clear flag +6 +1 + + +IDLECF +Idle line detected clear flag +4 +1 + + +ORECF +Overrun error clear flag +3 +1 + + +NCF +Noise detected clear flag +2 +1 + + +FECF +Framing error clear flag +1 +1 + + +PECF +Parity error clear flag +0 +1 + + + + +RDR +RDR +Receive data register +0x24 +0x20 +read-only +0x0000 + + +RDR +Receive data value +0 +9 + + + + +TDR +TDR +Transmit data register +0x28 +0x20 +read-write +0x0000 + + +TDR +Transmit data value +0 +9 + + + + + + +USART2 +0x40004400 + +USART2_EXTI26 +USART2 global interrupt and EXTI Line 26 + interrupt +38 + + + +USART3 +0x40004800 + +USART3_EXTI28 +USART3 global interrupt and EXTI Line 28 + interrupt +39 + + + +UART4 +0x40004C00 + +UART4_EXTI34 +UART4 global and EXTI Line 34 + interrupts +52 + + + +UART5 +0x40005000 + +UART5_EXTI35 +UART5 global and EXTI Line 35 + interrupts +53 + + + +SPI1 +Serial peripheral interface/Inter-IC sound +SPI +0x40013000 + +0x0 +0x400 +registers + + +SPI1 +SPI1 global interrupt +35 + + + +CR1 +CR1 +control register 1 +0x0 +0x20 +read-write +0x0000 + + +BIDIMODE +Bidirectional data mode enable +15 +1 + + +BIDIOE +Output enable in bidirectional mode +14 +1 + + +CRCEN +Hardware CRC calculation enable +13 +1 + + +CRCNEXT +CRC transfer next +12 +1 + + +DFF +Data frame format +11 +1 + + +RXONLY +Receive only +10 +1 + + +SSM +Software slave management +9 +1 + + +SSI +Internal slave select +8 +1 + + +LSBFIRST +Frame format +7 +1 + + +SPE +SPI enable +6 +1 + + +BR +Baud rate control +3 +3 + + +MSTR +Master selection +2 +1 + + +CPOL +Clock polarity +1 +1 + + +CPHA +Clock phase +0 +1 + + + + +CR2 +CR2 +control register 2 +0x4 +0x20 +read-write +0x0000 + + +RXDMAEN +Rx buffer DMA enable +0 +1 + + +TXDMAEN +Tx buffer DMA enable +1 +1 + + +SSOE +SS output enable +2 +1 + + +NSSP +NSS pulse management +3 +1 + + +FRF +Frame format +4 +1 + + +ERRIE +Error interrupt enable +5 +1 + + +RXNEIE +RX buffer not empty interrupt enable +6 +1 + + +TXEIE +Tx buffer empty interrupt enable +7 +1 + + +DS +Data size +8 +4 + + +FRXTH +FIFO reception threshold +12 +1 + + +LDMA_RX +Last DMA transfer for reception +13 +1 + + +LDMA_TX +Last DMA transfer for transmission +14 +1 + + + + +SR +SR +status register +0x8 +0x20 +0x0002 + + +RXNE +Receive buffer not empty +0 +1 +read-only + + +TXE +Transmit buffer empty +1 +1 +read-only + + +CHSIDE +Channel side +2 +1 +read-only + + +UDR +Underrun flag +3 +1 +read-only + + +CRCERR +CRC error flag +4 +1 +read-write + + +MODF +Mode fault +5 +1 +read-only + + +OVR +Overrun flag +6 +1 +read-only + + +BSY +Busy flag +7 +1 +read-only + + +TIFRFE +TI frame format error +8 +1 +read-only + + +FRLVL +FIFO reception level +9 +2 +read-only + + +FTLVL +FIFO transmission level +11 +2 +read-only + + + + +DR +DR +data register +0xC +0x20 +read-write +0x0000 + + +DR +Data register +0 +16 + + + + +CRCPR +CRCPR +CRC polynomial register +0x10 +0x20 +read-write +0x0007 + + +CRCPOLY +CRC polynomial register +0 +16 + + + + +RXCRCR +RXCRCR +RX CRC register +0x14 +0x20 +read-only +0x0000 + + +RxCRC +Rx CRC register +0 +16 + + + + +TXCRCR +TXCRCR +TX CRC register +0x18 +0x20 +read-only +0x0000 + + +TxCRC +Tx CRC register +0 +16 + + + + +I2SCFGR +I2SCFGR +I2S configuration register +0x1C +0x20 +read-write +0x0000 + + +I2SMOD +I2S mode selection +11 +1 + + +I2SE +I2S Enable +10 +1 + + +I2SCFG +I2S configuration mode +8 +2 + + +PCMSYNC +PCM frame synchronization +7 +1 + + +I2SSTD +I2S standard selection +4 +2 + + +CKPOL +Steady state clock polarity +3 +1 + + +DATLEN +Data length to be transferred +1 +2 + + +CHLEN +Channel length (number of bits per audio channel) +0 +1 + + + + +I2SPR +I2SPR +I2S prescaler register +0x20 +0x20 +read-write +0x00000010 + + +MCKOE +Master clock output enable +9 +1 + + +ODD +Odd factor for the prescaler +8 +1 + + +I2SDIV +I2S Linear prescaler +0 +8 + + + + + + +SPI2 +0x40003800 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Line 34 + interrupts +52 + + +UART5_EXTI35 +UART5 global and EXTI Line 35 + interrupts +53 + + +USB_WKUP_EXTI +USB wakeup from Suspend and EXTI Line + 18 +76 + + + +IMR1 +IMR1 +Interrupt mask register +0x0 +0x20 +read-write +0x1F800000 + + +MR0 +Interrupt Mask on line 0 +0 +1 + + +MR1 +Interrupt Mask on line 1 +1 +1 + + +MR2 +Interrupt Mask on line 2 +2 +1 + + +MR3 +Interrupt Mask on line 3 +3 +1 + + +MR4 +Interrupt Mask on line 4 +4 +1 + + +MR5 +Interrupt Mask on line 5 +5 +1 + + +MR6 +Interrupt Mask on line 6 +6 +1 + + +MR7 +Interrupt Mask on line 7 +7 +1 + + +MR8 +Interrupt Mask on line 8 +8 +1 + + +MR9 +Interrupt Mask on line 9 +9 +1 + + +MR10 +Interrupt Mask on line 10 +10 +1 + + +MR11 +Interrupt Mask on line 11 +11 +1 + + +MR12 +Interrupt Mask on line 12 +12 +1 + + +MR13 +Interrupt Mask on line 13 +13 +1 + + +MR14 +Interrupt Mask on line 14 +14 +1 + + +MR15 +Interrupt Mask on line 15 +15 +1 + + +MR16 +Interrupt Mask on line 16 +16 +1 + + +MR17 +Interrupt Mask on line 17 +17 +1 + + +MR18 +Interrupt Mask on line 18 +18 +1 + + +MR19 +Interrupt Mask on line 19 +19 +1 + + +MR20 +Interrupt Mask on line 20 +20 +1 + + +MR21 +Interrupt Mask on line 21 +21 +1 + + +MR22 +Interrupt Mask on line 22 +22 +1 + + +MR23 +Interrupt Mask on line 23 +23 +1 + + +MR24 +Interrupt Mask on line 24 +24 +1 + + +MR25 +Interrupt Mask on line 25 +25 +1 + + +MR26 +Interrupt Mask on line 26 +26 +1 + + +MR27 +Interrupt Mask on line 27 +27 +1 + + +MR28 +Interrupt Mask on line 28 +28 +1 + + +MR29 +Interrupt Mask on line 29 +29 +1 + + +MR30 +Interrupt Mask on line 30 +30 +1 + + +MR31 +Interrupt Mask on line 31 +31 +1 + + + + +EMR1 +EMR1 +Event mask register +0x4 +0x20 +read-write +0x00000000 + + +MR0 +Event Mask on line 0 +0 +1 + + +MR1 +Event Mask on line 1 +1 +1 + + +MR2 +Event Mask on line 2 +2 +1 + + +MR3 +Event Mask on line 3 +3 +1 + + +MR4 +Event Mask on line 4 +4 +1 + + +MR5 +Event Mask on line 5 +5 +1 + + +MR6 +Event Mask on line 6 +6 +1 + + +MR7 +Event Mask on line 7 +7 +1 + + +MR8 +Event Mask on line 8 +8 +1 + + +MR9 +Event Mask on line 9 +9 +1 + + +MR10 +Event Mask on line 10 +10 +1 + + +MR11 +Event Mask on line 11 +11 +1 + + +MR12 +Event Mask on line 12 +12 +1 + + +MR13 +Event Mask on line 13 +13 +1 + + +MR14 +Event Mask on line 14 +14 +1 + + +MR15 +Event Mask on line 15 +15 +1 + + +MR16 +Event Mask on line 16 +16 +1 + + +MR17 +Event Mask on line 17 +17 +1 + + +MR18 +Event Mask on line 18 +18 +1 + + +MR19 +Event Mask on line 19 +19 +1 + + +MR20 +Event Mask on line 20 +20 +1 + + +MR21 +Event Mask on line 21 +21 +1 + + +MR22 +Event Mask on line 22 +22 +1 + + +MR23 +Event Mask on line 23 +23 +1 + + +MR24 +Event Mask on line 24 +24 +1 + + +MR25 +Event Mask on line 25 +25 +1 + + +MR26 +Event Mask on line 26 +26 +1 + + +MR27 +Event Mask on line 27 +27 +1 + + +MR28 +Event Mask on line 28 +28 +1 + + +MR29 +Event Mask on line 29 +29 +1 + + +MR30 +Event Mask on line 30 +30 +1 + + +MR31 +Event Mask on line 31 +31 +1 + + + + +RTSR1 +RTSR1 +Rising Trigger selection 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event configuration of line 15 +15 +1 + + +TR16 +Rising trigger event configuration of line 16 +16 +1 + + +TR17 +Rising trigger event configuration of line 17 +17 +1 + + +TR18 +Rising trigger event configuration of line 18 +18 +1 + + +TR19 +Rising trigger event configuration of line 19 +19 +1 + + +TR20 +Rising trigger event configuration of line 20 +20 +1 + + +TR21 +Rising trigger event configuration of line 21 +21 +1 + + +TR22 +Rising trigger event configuration of line 22 +22 +1 + + +TR29 +Rising trigger event configuration of line 29 +29 +1 + + +TR30 +Rising trigger event configuration of line 30 +30 +1 + + +TR31 +Rising trigger event configuration of line 31 +31 +1 + + + + +FTSR1 +FTSR1 +Falling Trigger selection register +0xC +0x20 +read-write +0x00000000 + + +TR0 +Falling trigger event configuration of line 0 +0 +1 + + +TR1 +Falling trigger event configuration of line 1 +1 +1 + + +TR2 +Falling trigger event configuration of line 2 +2 +1 + + +TR3 +Falling trigger event configuration of line 3 +3 +1 + + +TR4 +Falling trigger event configuration of line 4 +4 +1 + + +TR5 +Falling trigger event configuration of line 5 +5 +1 + + +TR6 +Falling trigger event configuration of line 6 +6 +1 + + +TR7 +Falling trigger event configuration of line 7 +7 +1 + + +TR8 +Falling trigger event configuration of line 8 +8 +1 + + +TR9 +Falling trigger event configuration of line 9 +9 +1 + + +TR10 +Falling trigger event configuration of line 10 +10 +1 + + +TR11 +Falling trigger event configuration of line 11 +11 +1 + + +TR12 +Falling trigger event configuration of line 12 +12 +1 + + +TR13 +Falling trigger event configuration of line 13 +13 +1 + + +TR14 +Falling trigger event configuration of line 14 +14 +1 + + +TR15 +Falling trigger event configuration of line 15 +15 +1 + + +TR16 +Falling trigger event configuration of line 16 +16 +1 + + +TR17 +Falling trigger event configuration of line 17 +17 +1 + + +TR18 +Falling trigger event configuration of line 18 +18 +1 + + +TR19 +Falling trigger event configuration of line 19 +19 +1 + + +TR20 +Falling trigger event configuration of line 20 +20 +1 + + +TR21 +Falling trigger event configuration of line 21 +21 +1 + + +TR22 +Falling trigger event configuration of line 22 +22 +1 + + +TR29 +Falling trigger event configuration of line 29 +29 +1 + + +TR30 +Falling trigger event configuration of line 30. +30 +1 + + +TR31 +Falling trigger event configuration of line 31 +31 +1 + + + + +SWIER1 +SWIER1 +Software interrupt event register +0x10 +0x20 +read-write +0x00000000 + + +SWIER0 +Software Interrupt on line 0 +0 +1 + + +SWIER1 +Software Interrupt on line 1 +1 +1 + + +SWIER2 +Software Interrupt on line 2 +2 +1 + + +SWIER3 +Software Interrupt on line 3 +3 +1 + + +SWIER4 +Software Interrupt on line 4 +4 +1 + + +SWIER5 +Software Interrupt on line 5 +5 +1 + + +SWIER6 +Software Interrupt on line 6 +6 +1 + + +SWIER7 +Software Interrupt on line 7 +7 +1 + + +SWIER8 +Software Interrupt on line 8 +8 +1 + + +SWIER9 +Software Interrupt on line 9 +9 +1 + + +SWIER10 +Software Interrupt on line 10 +10 +1 + + +SWIER11 +Software Interrupt on line 11 +11 +1 + + +SWIER12 +Software Interrupt on line 12 +12 +1 + + +SWIER13 +Software Interrupt on line 13 +13 +1 + + +SWIER14 +Software Interrupt on line 14 +14 +1 + + +SWIER15 +Software Interrupt on line 15 +15 +1 + + +SWIER16 +Software Interrupt on line 16 +16 +1 + + +SWIER17 +Software Interrupt on line 17 +17 +1 + + +SWIER18 +Software Interrupt on line 18 +18 +1 + + +SWIER19 +Software Interrupt on line 19 +19 +1 + + +SWIER20 +Software Interrupt on line 20 +20 +1 + + +SWIER21 +Software Interrupt on line 21 +21 +1 + + +SWIER22 +Software Interrupt on line 22 +22 +1 + + +SWIER29 +Software Interrupt on line 29 +29 +1 + + +SWIER30 +Software Interrupt on line 309 +30 +1 + + +SWIER31 +Software Interrupt on line 319 +31 +1 + + + + +PR1 +PR1 +Pending register +0x14 +0x20 +read-write +0x00000000 + + +PR0 +Pending bit 0 +0 +1 + + +PR1 +Pending bit 1 +1 +1 + + +PR2 +Pending bit 2 +2 +1 + + +PR3 +Pending bit 3 +3 +1 + + +PR4 +Pending bit 4 +4 +1 + + +PR5 +Pending bit 5 +5 +1 + + +PR6 +Pending bit 6 +6 +1 + + +PR7 +Pending bit 7 +7 +1 + + +PR8 +Pending bit 8 +8 +1 + + +PR9 +Pending bit 9 +9 +1 + + +PR10 +Pending bit 10 +10 +1 + + +PR11 +Pending bit 11 +11 +1 + + +PR12 +Pending bit 12 +12 +1 + + +PR13 +Pending bit 13 +13 +1 + + +PR14 +Pending bit 14 +14 +1 + + +PR15 +Pending bit 15 +15 +1 + + +PR16 +Pending bit 16 +16 +1 + + +PR17 +Pending bit 17 +17 +1 + + +PR18 +Pending bit 18 +18 +1 + + +PR19 +Pending bit 19 +19 +1 + + +PR20 +Pending bit 20 +20 +1 + + +PR21 +Pending bit 21 +21 +1 + + +PR22 +Pending bit 22 +22 +1 + + +PR29 +Pending bit 29 +29 +1 + + +PR30 +Pending bit 30 +30 +1 + + +PR31 +Pending bit 31 +31 +1 + + + + +IMR2 +IMR2 +Interrupt mask register +0x18 +0x20 +read-write +0xFFFFFFFC + + +MR32 +Interrupt Mask on external/internal line 32 +0 +1 + + +MR33 +Interrupt Mask on external/internal line 33 +1 +1 + + +MR34 +Interrupt Mask on external/internal line 34 +2 +1 + + +MR35 +Interrupt Mask on external/internal line 35 +3 +1 + + + + +EMR2 +EMR2 +Event mask register +0x1C +0x20 +read-write +0x00000000 + + +MR32 +Event mask on external/internal line 32 +0 +1 + + +MR33 +Event mask on external/internal line 33 +1 +1 + + +MR34 +Event mask on external/internal line 34 +2 +1 + + +MR35 +Event mask on external/internal line 35 +3 +1 + + + + +RTSR2 +RTSR2 +Rising Trigger selection register +0x20 +0x20 +read-write +0x00000000 + + +TR32 +Rising trigger event configuration bit of line 32 +0 +1 + + +TR33 +Rising trigger event configuration bit of line 33 +1 +1 + + + + +FTSR2 +FTSR2 +Falling Trigger selection register +0x24 +0x20 +read-write +0x00000000 + + +TR32 +Falling trigger event configuration bit of line 32 +0 +1 + + +TR33 +Falling trigger event configuration bit of line 33 +1 +1 + + + + +SWIER2 +SWIER2 +Software interrupt event register +0x28 +0x20 +read-write +0x00000000 + + +SWIER32 +Software interrupt on line 32 +0 +1 + + +SWIER33 +Software interrupt on line 33 +1 +1 + + + + +PR2 +PR2 +Pending register +0x2C +0x20 +read-write +0x00000000 + + +PR32 +Pending bit on line 32 +0 +1 + + +PR33 +Pending bit on line 33 +1 +1 + + + + + + +COMP +Comparator +COMP +0x4001001C + +0x0 +0x19 +registers + + +COMP123 +COMP1 & COMP2 & COMP3 interrupts + combined with EXTI Lines 21, 22 and 29 + interrupts +64 + + +COMP456 +COMP4 & COMP5 & COMP6 interrupts + combined with EXTI Lines 30, 31 and 32 + interrupts +65 + + +COMP7 +COMP7 interrupt combined with EXTI Line 33 + interrupt +66 + + + +COMP1_CSR +COMP1_CSR +control and status register +0x0 +0x20 +0x00000000 + + +COMP1EN +Comparator 1 enable +0 +1 +read-write + + +COMP1_INP_DAC +COMP1_INP_DAC +1 +1 +read-write + + +COMP1MODE +Comparator 1 mode +2 +2 +read-write + + +COMP1INSEL +Comparator 1 inverting input selection +4 +3 +read-write + + +COMP1_OUT_SEL +Comparator 1 output selection +10 +4 +read-write + + +COMP1POL +Comparator 1 output polarity +15 +1 +read-write + + +COMP1HYST +Comparator 1 hysteresis +16 +2 +read-write + + +COMP1_BLANKING +Comparator 1 blanking source +18 +3 +read-write + + +COMP1OUT +Comparator 1 output +30 +1 +read-only + + +COMP1LOCK +Comparator 1 lock +31 +1 +read-write + + + + +COMP2_CSR +COMP2_CSR +control and status register +0x4 +0x20 +read-write +0x00000000 + + +COMP2EN +Comparator 2 enable +0 +1 + + +COMP2MODE +Comparator 2 mode +2 +2 + + +COMP2INSEL +Comparator 2 inverting input selection +4 +3 + + +COMP2INPSEL +Comparator 2 non inverted input selection +7 +1 + + +COMP2INMSEL +Comparator 1inverting input selection +9 +1 + + +COMP2_OUT_SEL +Comparator 2 output selection +10 +4 + + +COMP2POL +Comparator 2 output polarity +15 +1 + + +COMP2HYST +Comparator 2 hysteresis +16 +2 + + +COMP2_BLANKING +Comparator 2 blanking source +18 +3 + + +COMP2LOCK +Comparator 2 lock +31 +1 + + + + +COMP3_CSR +COMP3_CSR +control and status register +0x8 +0x20 +0x00000000 + + +COMP3EN +Comparator 3 enable +0 +1 +read-write + + +COMP3MODE +Comparator 3 mode +2 +2 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+ +COMP4POL +Comparator 4 output polarity +15 +1 +read-write + + +COMP4HYST +Comparator 4 hysteresis +16 +2 +read-write + + +COMP4_BLANKING +Comparator 4 blanking source +18 +3 +read-write + + +COMP4OUT +Comparator 4 output +30 +1 +read-only + + +COMP4LOCK +Comparator 4 lock +31 +1 +read-write + + + + +COMP5_CSR +COMP5_CSR +control and status register +0x10 +0x20 +0x00000000 + + +COMP5EN +Comparator 5 enable +0 +1 +read-write + + +COMP5MODE +Comparator 5 mode +2 +2 +read-write + + +COMP5INSEL +Comparator 5 inverting input selection +4 +3 +read-write + + +COMP5INPSEL +Comparator 5 non inverted input selection +7 +1 +read-write + + +COMP5_OUT_SEL +Comparator 5 output selection +10 +4 +read-write + + +COMP5POL +Comparator 5 output polarity +15 +1 +read-write + + +COMP5HYST +Comparator 5 hysteresis +16 +2 +read-write + + +COMP5_BLANKING +Comparator 5 blanking source +18 +3 +read-write + + +COMP5OUT +Comparator51 output +30 +1 +read-only + + +COMP5LOCK +Comparator 5 lock +31 +1 +read-write + + + + +COMP6_CSR +COMP6_CSR +control and status register +0x14 +0x20 +0x00000000 + + +COMP6EN +Comparator 6 enable +0 +1 +read-write + + +COMP6MODE +Comparator 6 mode +2 +2 +read-write + + +COMP6INSEL +Comparator 6 inverting input selection +4 +3 +read-write + + +COMP6INPSEL +Comparator 6 non inverted input selection +7 +1 +read-write + + +COM6WINMODE +Comparator 6 window mode +9 +1 +read-write + + +COMP6_OUT_SEL +Comparator 6 output selection +10 +4 +read-write + + +COMP6POL +Comparator 6 output polarity +15 +1 +read-write + + +COMP6HYST +Comparator 6 hysteresis +16 +2 +read-write + + +COMP6_BLANKING +Comparator 6 blanking source +18 +3 +read-write + + +COMP6OUT +Comparator 6 output +30 +1 +read-only + + +COMP6LOCK +Comparator 6 lock +31 +1 +read-write + + + + +COMP7_CSR +COMP7_CSR +control and status register +0x18 +0x20 +0x00000000 + + +COMP7EN +Comparator 7 enable +0 +1 +read-write + + +COMP7MODE +Comparator 7 mode +2 +2 +read-write + + +COMP7INSEL +Comparator 7 inverting input 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+8 +1 +read-only + + +SLAKI +SLAKI +4 +1 +read-write + + +WKUI +WKUI +3 +1 +read-write + + +ERRI +ERRI +2 +1 +read-write + + +SLAK +SLAK +1 +1 +read-only + + +INAK +INAK +0 +1 +read-only + + + + +TSR +TSR +transmit status register +0x8 +0x20 +0x1C000000 + + +LOW2 +Lowest priority flag for mailbox 2 +31 +1 +read-only + + +LOW1 +Lowest priority flag for mailbox 1 +30 +1 +read-only + + +LOW0 +Lowest priority flag for mailbox 0 +29 +1 +read-only + + +TME2 +Lowest priority flag for mailbox 2 +28 +1 +read-only + + +TME1 +Lowest priority flag for mailbox 1 +27 +1 +read-only + + +TME0 +Lowest priority flag for mailbox 0 +26 +1 +read-only + + +CODE +CODE +24 +2 +read-only + + +ABRQ2 +ABRQ2 +23 +1 +read-write + + +TERR2 +TERR2 +19 +1 +read-write + + +ALST2 +ALST2 +18 +1 +read-write + + +TXOK2 +TXOK2 +17 +1 +read-write + + +RQCP2 +RQCP2 +16 +1 +read-write + + +ABRQ1 +ABRQ1 +15 +1 +read-write + + +TERR1 +TERR1 +11 +1 +read-write + + +ALST1 +ALST1 +10 +1 +read-write + + +TXOK1 +TXOK1 +9 +1 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register +0x10 +0x20 +0x00000000 + + +EA +Endpoint address +0 +4 +read-write + + +STAT_TX +Status bits, for transmission transfers +4 +2 +read-write + + +DTOG_TX +Data Toggle, for transmission transfers +6 +1 +read-write + + +CTR_TX +Correct Transfer for transmission +7 +1 +read-write + + +EP_KIND +Endpoint kind +8 +1 +read-write + + +EP_TYPE +Endpoint type +9 +2 +read-write + + +SETUP +Setup transaction completed +11 +1 +read-only + + +STAT_RX +Status bits, for reception transfers +12 +2 +read-write + + +DTOG_RX +Data Toggle, for reception transfers +14 +1 +read-write + + +CTR_RX +Correct transfer for reception +15 +1 +read-write + + + + +USB_EP5R +USB_EP5R +endpoint 5 register +0x14 +0x20 +0x00000000 + + +EA +Endpoint address +0 +4 +read-write + + +STAT_TX +Status bits, for transmission transfers +4 +2 +read-write + + +DTOG_TX +Data Toggle, for transmission transfers +6 +1 +read-write + + +CTR_TX +Correct Transfer for transmission +7 +1 +read-write + + +EP_KIND +Endpoint kind +8 +1 +read-write + + +EP_TYPE +Endpoint type +9 +2 +read-write + + +SETUP +Setup transaction completed +11 +1 +read-only + + +STAT_RX +Status bits, for reception transfers +12 +2 +read-write + + +DTOG_RX +Data Toggle, for reception transfers +14 +1 +read-write + + +CTR_RX +Correct transfer for reception +15 +1 +read-write + + + + +USB_EP6R +USB_EP6R +endpoint 6 register +0x18 +0x20 +0x00000000 + + +EA +Endpoint address +0 +4 +read-write + + +STAT_TX +Status bits, for transmission transfers +4 +2 +read-write + + +DTOG_TX +Data Toggle, for transmission transfers +6 +1 +read-write + + +CTR_TX +Correct Transfer for transmission +7 +1 +read-write + + +EP_KIND +Endpoint kind +8 +1 +read-write + + +EP_TYPE +Endpoint type +9 +2 +read-write + + +SETUP +Setup transaction completed +11 +1 +read-only + + +STAT_RX +Status bits, for reception transfers +12 +2 +read-write + + +DTOG_RX +Data Toggle, for reception transfers +14 +1 +read-write + + +CTR_RX +Correct transfer for reception +15 +1 +read-write + + + + +USB_EP7R +USB_EP7R +endpoint 7 register +0x1C +0x20 +0x00000000 + + +EA +Endpoint address +0 +4 +read-write + + +STAT_TX +Status bits, for transmission transfers +4 +2 +read-write + + +DTOG_TX +Data Toggle, for transmission transfers +6 +1 +read-write + + +CTR_TX +Correct Transfer for transmission +7 +1 +read-write + + +EP_KIND +Endpoint kind +8 +1 +read-write + + +EP_TYPE +Endpoint type +9 +2 +read-write + + +SETUP +Setup transaction completed +11 +1 +read-only + + +STAT_RX +Status bits, for reception transfers +12 +2 +read-write + + +DTOG_RX +Data Toggle, for reception transfers +14 +1 +read-write + + +CTR_RX +Correct transfer for reception +15 +1 +read-write + + + + +USB_CNTR +USB_CNTR +control register +0x40 +0x20 +read-write +0x00000003 + + +FRES +Force USB Reset +0 +1 + + +PDWN +Power down +1 +1 + + +LPMODE +Low-power mode +2 +1 + + +FSUSP +Force suspend +3 +1 + + +RESUME +Resume request +4 +1 + + +ESOFM +Expected start of frame interrupt mask +8 +1 + + +SOFM +Start of frame interrupt mask +9 +1 + + +RESETM +USB reset interrupt mask +10 +1 + + +SUSPM +Suspend mode interrupt mask +11 +1 + + +WKUPM +Wakeup interrupt mask +12 +1 + + +ERRM +Error interrupt mask +13 +1 + + +PMAOVRM +Packet memory area over / underrun interrupt mask +14 +1 + + +CTRM +Correct transfer interrupt mask +15 +1 + + + + +ISTR +ISTR +interrupt status register +0x44 +0x20 +0x00000000 + + +EP_ID +Endpoint Identifier +0 +4 +read-only + + +DIR +Direction of transaction +4 +1 +read-only + + +ESOF +Expected start frame +8 +1 +read-write + + +SOF +start of frame +9 +1 +read-write + + +RESET +reset request +10 +1 +read-write + + +SUSP +Suspend mode request +11 +1 +read-write + + +WKUP +Wakeup +12 +1 +read-write + + +ERR +Error +13 +1 +read-write + + +PMAOVR +Packet memory area over / underrun +14 +1 +read-write + + +CTR +Correct transfer +15 +1 +read-only + + + + +FNR +FNR +frame number register +0x48 +0x20 +read-only +0x0000 + + +FN +Frame number +0 +11 + + +LSOF +Lost SOF +11 +2 + + +LCK +Locked +13 +1 + + +RXDM +Receive data - line status +14 +1 + + +RXDP +Receive data + line status +15 +1 + + + + +DADDR +DADDR +device address +0x4C +0x20 +read-write +0x0000 + + +ADD +Device address +0 +1 + + +ADD1 +Device address +1 +1 + + +ADD2 +Device address +2 +1 + + +ADD3 +Device address +3 +1 + + +ADD4 +Device address +4 +1 + + +ADD5 +Device address +5 +1 + + +ADD6 +Device address +6 +1 + + +EF +Enable function +7 +1 + + + + +BTABLE +BTABLE +Buffer table address +0x50 +0x20 +read-write +0x0000 + + +BTABLE +Buffer table +3 +13 + + + + + + +I2C1 +Inter-integrated circuit +I2C +0x40005400 + +0x0 +0x400 +registers + + +I2C1_EV_EXTI23 +I2C1 event interrupt and EXTI Line23 + interrupt +31 + + +I2C1_ER +I2C1 error interrupt +32 + + + +CR1 +CR1 +Control register 1 +0x0 +0x20 +0x00000000 + + +PE +Peripheral enable +0 +1 +read-write + + +TXIE +TX Interrupt enable +1 +1 +read-write + + +RXIE +RX Interrupt enable +2 +1 +read-write + + +ADDRIE +Address match interrupt enable (slave only) +3 +1 +read-write + + +NACKIE +Not acknowledge received interrupt enable +4 +1 +read-write + + +STOPIE +STOP detection Interrupt enable +5 +1 +read-write + + +TCIE +Transfer Complete interrupt enable +6 +1 +read-write + + +ERRIE +Error interrupts enable +7 +1 +read-write + + +DNF +Digital noise filter +8 +4 +read-write + + +ANFOFF +Analog noise filter OFF +12 +1 +read-write + + +SWRST +Software reset +13 +1 +write-only + + +TXDMAEN +DMA transmission requests enable +14 +1 +read-write + + +RXDMAEN +DMA reception requests enable +15 +1 +read-write + + +SBC +Slave byte control +16 +1 +read-write + + +NOSTRETCH +Clock stretching disable +17 +1 +read-write + + +WUPEN +Wakeup from STOP enable +18 +1 +read-write + + +GCEN +General call enable +19 +1 +read-write + + +SMBHEN +SMBus Host address enable +20 +1 +read-write + + +SMBDEN +SMBus Device Default address enable +21 +1 +read-write + + +ALERTEN +SMBUS alert enable +22 +1 +read-write + + +PECEN +PEC enable +23 +1 +read-write + + + + +CR2 +CR2 +Control register 2 +0x4 +0x20 +read-write +0x00000000 + + +PECBYTE +Packet error checking byte +26 +1 + + +AUTOEND +Automatic end mode (master mode) +25 +1 + + +RELOAD +NBYTES reload mode +24 +1 + + +NBYTES +Number of bytes +16 +8 + + +NACK +NACK generation (slave mode) +15 +1 + + +STOP +Stop generation (master mode) +14 +1 + + +START +Start generation +13 +1 + + +HEAD10R +10-bit address header only read direction (master receiver mode) +12 +1 + + +ADD10 +10-bit addressing mode (master mode) +11 +1 + + +RD_WRN +Transfer direction (master mode) +10 +1 + + +SADD8 +Slave address bit 9:8 (master mode) +8 +2 + + +SADD1 +Slave address bit 7:1 (master mode) +1 +7 + + +SADD0 +Slave address bit 0 (master mode) +0 +1 + + + + +OAR1 +OAR1 +Own address register 1 +0x8 +0x20 +read-write +0x00000000 + + +OA1_0 +Interface address +0 +1 + + +OA1_1 +Interface address +1 +7 + + +OA1_8 +Interface address +8 +2 + + +OA1MODE +Own Address 1 10-bit mode +10 +1 + + +OA1EN +Own Address 1 enable +15 +1 + + + + +OAR2 +OAR2 +Own address register 2 +0xC +0x20 +read-write +0x00000000 + + +OA2 +Interface address +1 +7 + + +OA2MSK +Own Address 2 masks +8 +3 + + +OA2EN +Own Address 2 enable +15 +1 + + + + +TIMINGR +TIMINGR +Timing register +0x10 +0x20 +read-write +0x00000000 + + +SCLL +SCL low period (master mode) +0 +8 + + +SCLH +SCL high period (master mode) +8 +8 + + +SDADEL +Data hold time +16 +4 + + +SCLDEL +Data setup time +20 +4 + + +PRESC +Timing prescaler +28 +4 + + + + +TIMEOUTR +TIMEOUTR +Status register 1 +0x14 +0x20 +read-write +0x00000000 + + +TIMEOUTA +Bus timeout A +0 +12 + + +TIDLE +Idle clock timeout detection +12 +1 + + +TIMOUTEN +Clock timeout enable +15 +1 + + +TIMEOUTB +Bus timeout B +16 +12 + + +TEXTEN +Extended clock timeout enable +31 +1 + + + + +ISR +ISR +Interrupt and Status register +0x18 +0x20 +0x00000001 + + +ADDCODE +Address match code (Slave mode) +17 +7 +read-only + + +DIR +Transfer direction (Slave mode) +16 +1 +read-only + + +BUSY +Bus busy +15 +1 +read-only + + +ALERT +SMBus alert +13 +1 +read-only + + +TIMEOUT +Timeout or t_low detection flag +12 +1 +read-only + + +PECERR +PEC Error in reception +11 +1 +read-only + + +OVR +Overrun/Underrun (slave mode) +10 +1 +read-only + + +ARLO +Arbitration lost +9 +1 +read-only + + +BERR +Bus error +8 +1 +read-only + + +TCR +Transfer Complete Reload +7 +1 +read-only + + +TC +Transfer Complete (master mode) +6 +1 +read-only + + +STOPF +Stop detection flag +5 +1 +read-only + + +NACKF +Not acknowledge received flag +4 +1 +read-only + + +ADDR +Address matched (slave mode) +3 +1 +read-only + + +RXNE +Receive data register not empty (receivers) +2 +1 +read-only + + +TXIS +Transmit interrupt status (transmitters) +1 +1 +read-write + + +TXE +Transmit data register empty (transmitters) +0 +1 +read-write + + + + +ICR +ICR +Interrupt clear register +0x1C +0x20 +write-only +0x00000000 + + +ALERTCF +Alert flag clear +13 +1 + + +TIMOUTCF +Timeout detection flag clear +12 +1 + + +PECCF +PEC Error flag clear +11 +1 + + +OVRCF +Overrun/Underrun flag clear +10 +1 + + +ARLOCF +Arbitration lost flag clear +9 +1 + + +BERRCF +Bus error flag clear +8 +1 + + +STOPCF +Stop detection flag clear +5 +1 + + +NACKCF +Not Acknowledge flag clear +4 +1 + + +ADDRCF +Address Matched flag clear +3 +1 + + + + +PECR +PECR +PEC register +0x20 +0x20 +read-only +0x00000000 + + +PEC +Packet error checking register +0 +8 + + + + +RXDR +RXDR +Receive data register +0x24 +0x20 +read-only +0x00000000 + + +RXDATA +8-bit receive data +0 +8 + + + + +TXDR +TXDR +Transmit data register +0x28 +0x20 +read-write +0x00000000 + + +TXDATA +8-bit transmit data +0 +8 + + + + + + +I2C2 +0x40005800 + +I2C2_EV_EXTI24 +I2C2 event interrupt & EXTI Line24 + interrupt +33 + + +I2C2_ER +I2C2 error interrupt +34 + + + +I2C3 +0x40007800 + +I2C2_EV_EXTI24 +I2C2 event interrupt & EXTI Line24 + interrupt +33 + + +I2C2_ER +I2C2 error interrupt +34 + + + +IWDG +Independent watchdog +IWDG +0x40003000 + +0x0 +0x400 +registers + + + +KR +KR +Key register +0x0 +0x20 +write-only +0x00000000 + + +KEY +Key value +0 +16 + + + + +PR +PR +Prescaler register +0x4 +0x20 +read-write +0x00000000 + + +PR +Prescaler divider +0 +3 + + + + +RLR +RLR +Reload register +0x8 +0x20 +read-write +0x00000FFF + + +RL +Watchdog counter reload value +0 +12 + + + + +SR +SR +Status register +0xC +0x20 +read-only +0x00000000 + + +PVU +Watchdog prescaler value update +0 +1 + + +RVU +Watchdog counter reload value update +1 +1 + + +WVU +Watchdog counter window value update +2 +1 + + + + +WINR +WINR +Window register +0x10 +0x20 +read-write +0x00000FFF + + +WIN +Watchdog counter window value +0 +12 + + + + + + +WWDG +Window watchdog +WWDG +0x40002C00 + +0x0 +0x400 +registers + + +WWDG +Window Watchdog interrupt +0 + + + +CR +CR +Control register +0x0 +0x20 +read-write +0x0000007F + + +T +7-bit counter +0 +7 + + +WDGA +Activation bit +7 +1 + + + + +CFR +CFR +Configuration register +0x4 +0x20 +read-write +0x0000007F + + +EWI +Early wakeup interrupt +9 +1 + + +WDGTB +Timer base +7 +2 + + +W +7-bit window value +0 +7 + + + + +SR +SR +Status register +0x8 +0x20 +read-write +0x00000000 + + +EWIF +Early wakeup interrupt flag +0 +1 + + + + + + +RTC +Real-time clock +RTC +0x40002800 + +0x0 +0x400 +registers + + +RTC_WKUP +RTC Wakeup interrupt through the EXTI + line +3 + + +RTCAlarm +RTC alarm interrupt +41 + + + +TR +TR +time register +0x0 +0x20 +read-write +0x00000000 + + +PM +AM/PM notation +22 +1 + + +HT +Hour tens in BCD format +20 +2 + + +HU +Hour units in BCD format +16 +4 + + +MNT +Minute tens in BCD format +12 +3 + + +MNU +Minute units in BCD format +8 +4 + + +ST +Second tens in BCD format +4 +3 + + +SU +Second units in BCD format +0 +4 + + + + +DR +DR +date register +0x4 +0x20 +read-write +0x00002101 + + +YT +Year tens in BCD format +20 +4 + + +YU +Year units in BCD format +16 +4 + + +WDU +Week day units +13 +3 + + +MT +Month tens in BCD format +12 +1 + + +MU +Month units in BCD format +8 +4 + + +DT +Date tens in BCD format +4 +2 + + +DU +Date units in BCD format +0 +4 + + + + +CR +CR +control register +0x8 +0x20 +read-write +0x00000000 + + +WCKSEL +Wakeup clock selection +0 +3 + + +TSEDGE +Time-stamp event active edge +3 +1 + + +REFCKON +Reference clock detection enable (50 or 60 Hz) +4 +1 + + +BYPSHAD +Bypass the shadow registers +5 +1 + + +FMT +Hour format +6 +1 + + +ALRAE +Alarm A enable +8 +1 + + +ALRBE +Alarm B enable +9 +1 + + +WUTE +Wakeup timer enable +10 +1 + + +TSE +Time stamp enable +11 +1 + + +ALRAIE +Alarm A interrupt enable +12 +1 + + +ALRBIE +Alarm B interrupt enable +13 +1 + + +WUTIE +Wakeup timer interrupt enable +14 +1 + + +TSIE +Time-stamp interrupt enable +15 +1 + + +ADD1H +Add 1 hour (summer time change) +16 +1 + + +SUB1H +Subtract 1 hour (winter time change) +17 +1 + + +BKP +Backup +18 +1 + + +COSEL +Calibration output selection +19 +1 + + +POL +Output polarity +20 +1 + + +OSEL +Output selection +21 +2 + + +COE +Calibration output enable +23 +1 + + + + +ISR +ISR +initialization and status register +0xC +0x20 +0x00000007 + + +ALRAWF +Alarm A write flag +0 +1 +read-only + + +ALRBWF +Alarm B write flag +1 +1 +read-only + + +WUTWF +Wakeup timer write flag +2 +1 +read-only + + +SHPF +Shift operation pending +3 +1 +read-write + + +INITS +Initialization status flag +4 +1 +read-only + + +RSF +Registers synchronization flag +5 +1 +read-write + + +INITF +Initialization flag +6 +1 +read-only + + +INIT +Initialization mode +7 +1 +read-write + + +ALRAF +Alarm A flag +8 +1 +read-write + + +ALRBF +Alarm B flag +9 +1 +read-write + + +WUTF +Wakeup timer flag +10 +1 +read-write + + +TSF +Time-stamp flag +11 +1 +read-write + + +TSOVF +Time-stamp overflow flag +12 +1 +read-write + + +TAMP1F +Tamper detection flag +13 +1 +read-write + + +TAMP2F +RTC_TAMP2 detection flag +14 +1 +read-write + + +TAMP3F +RTC_TAMP3 detection flag +15 +1 +read-write + + +RECALPF +Recalibration pending Flag +16 +1 +read-only + + + + +PRER +PRER +prescaler register +0x10 +0x20 +read-write +0x007F00FF + + +PREDIV_A +Asynchronous prescaler factor +16 +7 + + +PREDIV_S +Synchronous prescaler factor +0 +15 + + + + +WUTR +WUTR +wakeup timer register +0x14 +0x20 +read-write +0x0000FFFF + + +WUT +Wakeup auto-reload value bits +0 +16 + + + + +ALRMAR +ALRMAR +alarm A register +0x1C +0x20 +read-write +0x00000000 + + +MSK4 +Alarm A date mask +31 +1 + + +WDSEL +Week day selection +30 +1 + + +DT +Date tens in BCD format +28 +2 + + +DU +Date units or day in BCD format +24 +4 + + +MSK3 +Alarm A hours mask +23 +1 + + +PM +AM/PM notation +22 +1 + + +HT +Hour tens in BCD format +20 +2 + + +HU +Hour units in BCD format +16 +4 + + +MSK2 +Alarm A minutes mask +15 +1 + + +MNT +Minute tens in BCD format +12 +3 + + +MNU +Minute units in BCD format +8 +4 + + +MSK1 +Alarm A seconds mask +7 +1 + + +ST +Second tens in BCD format +4 +3 + + +SU +Second units in BCD format +0 +4 + + + + +ALRMBR +ALRMBR +alarm B register +0x20 +0x20 +read-write +0x00000000 + + +MSK4 +Alarm B date mask +31 +1 + + +WDSEL +Week day selection +30 +1 + + +DT +Date tens in BCD format +28 +2 + + +DU +Date units or day in BCD format +24 +4 + + +MSK3 +Alarm B hours mask +23 +1 + + +PM +AM/PM notation +22 +1 + + +HT +Hour tens in BCD format +20 +2 + + +HU +Hour units in BCD format +16 +4 + + +MSK2 +Alarm B minutes mask +15 +1 + + +MNT +Minute tens in BCD format +12 +3 + + +MNU +Minute units in BCD format +8 +4 + + +MSK1 +Alarm B seconds mask +7 +1 + + +ST +Second tens in BCD format +4 +3 + + +SU +Second units in BCD format +0 +4 + + + + +WPR +WPR +write protection register +0x24 +0x20 +write-only +0x00000000 + + +KEY +Write protection key +0 +8 + + + + +SSR +SSR +sub second register +0x28 +0x20 +read-only +0x00000000 + + +SS +Sub second value +0 +16 + + + + +SHIFTR +SHIFTR +shift control register +0x2C +0x20 +write-only +0x00000000 + + +ADD1S +Add one second +31 +1 + + +SUBFS +Subtract a fraction of a second +0 +15 + + + + +TSTR +TSTR +time stamp time register +0x30 +0x20 +read-only +0x00000000 + + +SU +Second units in BCD format +0 +4 + + +ST +Second tens in BCD format +4 +3 + + +MNU +Minute units in BCD format +8 +4 + + +MNT +Minute tens in BCD format +12 +3 + + +HU +Hour units in BCD format +16 +4 + + +HT +Hour tens in BCD format +20 +2 + + +PM +AM/PM notation +22 +1 + + + + +TSDR +TSDR +time stamp date register +0x34 +0x20 +read-only +0x00000000 + + +WDU +Week day units +13 +3 + + +MT +Month tens in BCD format +12 +1 + + +MU +Month units in BCD format +8 +4 + + +DT +Date tens in BCD format +4 +2 + + +DU +Date units in BCD format +0 +4 + + + + +TSSSR +TSSSR +timestamp sub second register +0x38 +0x20 +read-only +0x00000000 + + +SS +Sub second value +0 +16 + + + + +CALR +CALR +calibration register +0x3C +0x20 +read-write +0x00000000 + + +CALP +Increase frequency of RTC by 488.5 ppm +15 +1 + + +CALW8 +Use an 8-second calibration cycle period +14 +1 + + +CALW16 +Use a 16-second calibration cycle period +13 +1 + + +CALM +Calibration minus +0 +9 + + + + +TAFCR +TAFCR +tamper and alternate function configuration register +0x40 +0x20 +read-write +0x00000000 + + +TAMP1E +Tamper 1 detection enable +0 +1 + + +TAMP1TRG +Active level for tamper 1 +1 +1 + + +TAMPIE +Tamper interrupt enable +2 +1 + + +TAMP2E +Tamper 2 detection enable +3 +1 + + +TAMP2TRG +Active level for tamper 2 +4 +1 + + +TAMP3E +Tamper 3 detection enable +5 +1 + + +TAMP3TRG +Active level for tamper 3 +6 +1 + + +TAMPTS +Activate timestamp on tamper detection event +7 +1 + + +TAMPFREQ +Tamper sampling frequency +8 +3 + + +TAMPFLT +Tamper filter count +11 +2 + + +TAMPPRCH +Tamper precharge duration +13 +2 + + +TAMPPUDIS +TAMPER pull-up disable +15 +1 + + +PC13VALUE +PC13 value +18 +1 + + +PC13MODE +PC13 mode +19 +1 + + +PC14VALUE +PC14 value +20 +1 + + +PC14MODE +PC 14 mode +21 +1 + + +PC15VALUE +PC15 value +22 +1 + + +PC15MODE +PC15 mode +23 +1 + + + + +ALRMASSR +ALRMASSR +alarm A sub second register +0x44 +0x20 +read-write +0x00000000 + + +MASKSS +Mask the most-significant bits starting at this bit +24 +4 + + +SS +Sub seconds value +0 +15 + + + + +ALRMBSSR +ALRMBSSR +alarm B sub second register +0x48 +0x20 +read-write +0x00000000 + + +MASKSS +Mask the most-significant bits starting at this bit +24 +4 + + +SS +Sub seconds value +0 +15 + + + + +BKP0R +BKP0R +backup register +0x50 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP1R +BKP1R +backup register +0x54 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP2R +BKP2R +backup register +0x58 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP3R +BKP3R +backup register +0x5C +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP4R +BKP4R +backup register +0x60 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP5R +BKP5R +backup register +0x64 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP6R +BKP6R +backup register +0x68 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP7R +BKP7R +backup register +0x6C +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP8R +BKP8R +backup register +0x70 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP9R +BKP9R +backup register +0x74 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP10R +BKP10R +backup register +0x78 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP11R +BKP11R +backup register +0x7C +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP12R +BKP12R +backup register +0x80 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP13R +BKP13R +backup register +0x84 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP14R +BKP14R +backup register +0x88 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP15R +BKP15R +backup register +0x8C +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP16R +BKP16R +backup register +0x90 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP17R +BKP17R +backup register +0x94 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP18R +BKP18R +backup register +0x98 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP19R +BKP19R +backup register +0x9C +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP20R +BKP20R +backup register +0xA0 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP21R +BKP21R +backup register +0xA4 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP22R +BKP22R +backup register +0xA8 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP23R +BKP23R +backup register +0xAC +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP24R +BKP24R +backup register +0xB0 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP25R +BKP25R +backup register +0xB4 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP26R +BKP26R +backup register +0xB8 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP27R +BKP27R +backup register +0xBC +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP28R +BKP28R +backup register +0xC0 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP29R +BKP29R +backup register +0xC4 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP30R +BKP30R +backup register +0xC8 +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + +BKP31R +BKP31R +backup register +0xCC +0x20 +read-write +0x00000000 + + +BKP +BKP +0 +32 + + + + + + +TIM6 +Basic timers +TIMs +0x40001000 + +0x0 +0x400 +registers + + +TIM6_DACUNDER +TIM6 global and DAC12 underrun + interrupts +54 + + + +CR1 +CR1 +control register 1 +0x0 +0x20 +read-write +0x0000 + + +CEN +Counter enable +0 +1 + + +UDIS +Update disable +1 +1 + + +URS +Update request source +2 +1 + + +OPM +One-pulse mode +3 +1 + + +ARPE +Auto-reload preload enable +7 +1 + + +UIFREMAP +UIF status bit remapping +11 +1 + + + + +CR2 +CR2 +control register 2 +0x4 +0x20 +read-write +0x0000 + + +MMS +Master mode selection +4 +3 + + + + +DIER +DIER +DMA/Interrupt enable register +0xC +0x20 +read-write +0x0000 + + +UDE +Update DMA request enable +8 +1 + + +UIE +Update interrupt enable +0 +1 + + + + +SR +SR +status register +0x10 +0x20 +read-write +0x0000 + + +UIF +Update interrupt flag +0 +1 + + + + +EGR +EGR +event generation register +0x14 +0x20 +write-only +0x0000 + + +UG +Update generation +0 +1 + + + + +CNT +CNT +counter +0x24 +0x20 +0x00000000 + + +CNT +Low counter value +0 +16 +read-write + + +UIFCPY +UIF Copy +31 +1 +read-only + + + + +PSC +PSC +prescaler +0x28 +0x20 +read-write +0x0000 + + +PSC +Prescaler value +0 +16 + + + + +ARR +ARR +auto-reload register +0x2C +0x20 +read-write +0x00000000 + + +ARR +Low Auto-reload value +0 +16 + + + + + + +TIM7 +0x40001400 + +TIM7 +TIM7 global interrupt +55 + + + +DAC +Digital-to-analog converter +DAC +0x40007400 + +0x0 +0x400 +registers + + +TIM6_DACUNDER +TIM6 global and DAC12 underrun + interrupts +54 + + + +CR +CR +control register +0x0 +0x20 +read-write +0x00000000 + + +DMAUDRIE2 +DAC channel2 DMA underrun interrupt enable +29 +1 + + +DMAEN2 +DAC channel2 DMA enable +28 +1 + + +MAMP2 +DAC channel2 mask/amplitude selector +24 +4 + + +WAVE2 +DAC channel2 noise/triangle wave generation enable +22 +2 + + +TSEL2 +DAC channel2 trigger selection +19 +3 + + +TEN2 +DAC channel2 trigger enable +18 +1 + + +BOFF2 +DAC channel2 output buffer disable +17 +1 + + +EN2 +DAC channel2 enable +16 +1 + + +DMAUDRIE1 +DAC channel1 DMA Underrun Interrupt enable +13 +1 + + +DMAEN1 +DAC channel1 DMA enable +12 +1 + + +MAMP1 +DAC channel1 mask/amplitude selector +8 +4 + + +WAVE1 +DAC channel1 noise/triangle wave generation enable +6 +2 + + +TSEL1 +DAC channel1 trigger selection +3 +3 + + +TEN1 +DAC channel1 trigger enable +2 +1 + + +BOFF1 +DAC channel1 output buffer disable +1 +1 + + +EN1 +DAC channel1 enable +0 +1 + + + + +SWTRIGR +SWTRIGR +software trigger register +0x4 +0x20 +write-only +0x00000000 + + +SWTRIG2 +DAC channel2 software trigger +1 +1 + + +SWTRIG1 +DAC channel1 software trigger +0 +1 + + + + +DHR12R1 +DHR12R1 +channel1 12-bit right-aligned data holding register +0x8 +0x20 +read-write +0x00000000 + + +DACC1DHR +DAC channel1 12-bit right-aligned data +0 +12 + + + + +DHR12L1 +DHR12L1 +channel1 12-bit left aligned data holding register +0xC +0x20 +read-write +0x00000000 + + +DACC1DHR +DAC channel1 12-bit left-aligned data +4 +12 + + + + +DHR8R1 +DHR8R1 +channel1 8-bit right aligned data holding register +0x10 +0x20 +read-write +0x00000000 + + +DACC1DHR +DAC channel1 8-bit right-aligned data +0 +8 + + + + +DHR12R2 +DHR12R2 +channel2 12-bit right aligned data holding register +0x14 +0x20 +read-write +0x00000000 + + +DACC2DHR +DAC channel2 12-bit right-aligned data +0 +12 + + + + +DHR12L2 +DHR12L2 +channel2 12-bit left aligned data holding register +0x18 +0x20 +read-write +0x00000000 + + +DACC2DHR +DAC channel2 12-bit left-aligned data +4 +12 + + + + +DHR8R2 +DHR8R2 +channel2 8-bit right-aligned data holding register +0x1C +0x20 +read-write +0x00000000 + + +DACC2DHR +DAC channel2 8-bit right-aligned data +0 +8 + + + + +DHR12RD +DHR12RD +Dual DAC 12-bit right-aligned data holding register +0x20 +0x20 +read-write +0x00000000 + + +DACC2DHR +DAC channel2 12-bit right-aligned data +16 +12 + + +DACC1DHR +DAC channel1 12-bit right-aligned data +0 +12 + + + + +DHR12LD +DHR12LD +DUAL DAC 12-bit left aligned data holding register +0x24 +0x20 +read-write +0x00000000 + + +DACC2DHR +DAC channel2 12-bit left-aligned data +20 +12 + + +DACC1DHR +DAC channel1 12-bit left-aligned data +4 +12 + + + + +DHR8RD +DHR8RD +DUAL DAC 8-bit right aligned data holding register +0x28 +0x20 +read-write +0x00000000 + + +DACC2DHR +DAC channel2 8-bit right-aligned data +8 +8 + + +DACC1DHR +DAC channel1 8-bit right-aligned data +0 +8 + + + + +DOR1 +DOR1 +channel1 data output register +0x2C +0x20 +read-only +0x00000000 + + +DACC1DOR +DAC channel1 data output +0 +12 + + + + +DOR2 +DOR2 +channel2 data output register +0x30 +0x20 +read-only +0x00000000 + + +DACC2DOR +DAC channel2 data output +0 +12 + + + + +SR +SR +status register +0x34 +0x20 +read-write +0x00000000 + + +DMAUDR2 +DAC channel2 DMA underrun flag +29 +1 + + +DMAUDR1 +DAC channel1 DMA underrun flag +13 +1 + + + + + + +NVIC +Nested Vectored Interrupt Controller +NVIC +0xE000E000 + +0x0 +0x1001 +registers + + + +ICTR +ICTR +Interrupt Controller Type Register +0x4 +0x20 +read-only +0x00000000 + + +INTLINESNUM +Total number of interrupt lines in groups +0 +4 + + + + +STIR +STIR +Software Triggered Interrupt Register +0xF00 +0x20 +write-only +0x00000000 + + +INTID +interrupt to be triggered +0 +9 + + + + +ISER0 +ISER0 +Interrupt Set-Enable Register +0x100 +0x20 +read-write +0x00000000 + + +SETENA +SETENA +0 +32 + + + + +ISER1 +ISER1 +Interrupt Set-Enable Register +0x104 +0x20 +read-write +0x00000000 + + +SETENA +SETENA +0 +32 + + + + +ISER2 +ISER2 +Interrupt Set-Enable Register +0x108 +0x20 +read-write +0x00000000 + + +SETENA +SETENA +0 +32 + + + + +ICER0 +ICER0 +Interrupt Clear-Enable Register +0x180 +0x20 +read-write +0x00000000 + + +CLRENA +CLRENA +0 +32 + + + + +ICER1 +ICER1 +Interrupt Clear-Enable Register +0x184 +0x20 +read-write +0x00000000 + + +CLRENA +CLRENA +0 +32 + + + + +ICER2 +ICER2 +Interrupt Clear-Enable Register +0x188 +0x20 +read-write +0x00000000 + + +CLRENA +CLRENA +0 +32 + + + + +ISPR0 +ISPR0 +Interrupt Set-Pending Register +0x200 +0x20 +read-write +0x00000000 + + +SETPEND +SETPEND +0 +32 + + + + +ISPR1 +ISPR1 +Interrupt Set-Pending Register +0x204 +0x20 +read-write +0x00000000 + + +SETPEND +SETPEND +0 +32 + + + + +ISPR2 +ISPR2 +Interrupt Set-Pending Register +0x208 +0x20 +read-write +0x00000000 + + +SETPEND +SETPEND +0 +32 + + + + +ICPR0 +ICPR0 +Interrupt Clear-Pending Register +0x280 +0x20 +read-write +0x00000000 + + +CLRPEND +CLRPEND +0 +32 + + + + +ICPR1 +ICPR1 +Interrupt Clear-Pending Register +0x284 +0x20 +read-write +0x00000000 + + +CLRPEND +CLRPEND +0 +32 + + + + +ICPR2 +ICPR2 +Interrupt Clear-Pending Register +0x288 +0x20 +read-write +0x00000000 + + +CLRPEND +CLRPEND +0 +32 + + + + +IABR0 +IABR0 +Interrupt Active Bit Register +0x300 +0x20 +read-only +0x00000000 + + +ACTIVE +ACTIVE +0 +32 + + + + +IABR1 +IABR1 +Interrupt Active Bit Register +0x304 +0x20 +read-only +0x00000000 + + +ACTIVE +ACTIVE +0 +32 + + + + +IABR2 +IABR2 +Interrupt Active Bit Register +0x308 +0x20 +read-only +0x00000000 + + +ACTIVE +ACTIVE +0 +32 + + + + +IPR0 +IPR0 +Interrupt Priority Register +0x400 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR1 +IPR1 +Interrupt Priority Register +0x404 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR2 +IPR2 +Interrupt Priority Register +0x408 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR3 +IPR3 +Interrupt Priority Register +0x40C +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR4 +IPR4 +Interrupt Priority Register +0x410 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR5 +IPR5 +Interrupt Priority Register +0x414 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR6 +IPR6 +Interrupt Priority Register +0x418 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR7 +IPR7 +Interrupt Priority Register +0x41C +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR8 +IPR8 +Interrupt Priority Register +0x420 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR9 +IPR9 +Interrupt Priority Register +0x424 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR10 +IPR10 +Interrupt Priority Register +0x428 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR11 +IPR11 +Interrupt Priority Register +0x42C +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR12 +IPR12 +Interrupt Priority Register +0x430 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR13 +IPR13 +Interrupt Priority Register +0x434 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR14 +IPR14 +Interrupt Priority Register +0x438 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR15 +IPR15 +Interrupt Priority Register +0x43C +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR16 +IPR16 +Interrupt Priority Register +0x440 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR17 +IPR17 +Interrupt Priority Register +0x444 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR18 +IPR18 +Interrupt Priority Register +0x448 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR19 +IPR19 +Interrupt Priority Register +0x44C +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + +IPR20 +IPR20 +Interrupt Priority Register +0x450 +0x20 +read-write +0x00000000 + + +IPR_N0 +IPR_N0 +0 +8 + + +IPR_N1 +IPR_N1 +8 +8 + + +IPR_N2 +IPR_N2 +16 +8 + + +IPR_N3 +IPR_N3 +24 +8 + + + + + + +FPU +Floting point unit +FPU +0xE000ED88 + +0x0 +0x200 +registers + + +FPU +Floating point interrupt +81 + + + +CPACR +CPACR +Coprocessor Access Control Register +0x0 +0x20 +read-write +0x00000000 + + +CP0 +Access privileges for coprocessor 0 +0 +1 + + +CP1 +Access privileges for coprocessor 1 +2 +1 + + +CP2 +Access privileges for coprocessor 2 +4 +1 + + +CP3 +Access privileges for coprocessor 3 +6 +1 + + +CP4 +Access privileges for coprocessor 4 +8 +1 + + +CP5 +Access privileges for coprocessor 5 +10 +1 + + +CP6 +Access privileges for coprocessor 6 +12 +2 + + +CP7 +Access privileges for coprocessor 7 +14 +1 + + +CP10 +Access privileges for coprocessor 10 +20 +1 + + +CP11 +Access privileges for coprocessor 11 +22 +1 + + + + +FPCCR +FPCCR +FP Context Control Register +0x1AC +0x20 +read-write +0xC0000000 + + +LSPACT +LSPACT +0 +1 + + +USER +USER +1 +1 + + +THREAD +THREAD +3 +1 + + +HFRDY +HFRDY +4 +1 + + +MMRDY +MMRDY +5 +1 + + +BFRDY +BFRDY +6 +1 + + +MONRDY +MONRDY +8 +1 + + +LSPEN +LSPEN +30 +1 + + +ASPEN +ASPEN +31 +1 + + + + +FPCAR +FPCAR +FP Context Address Register +0x1B0 +0x20 +read-write +0x00000000 + + +ADDRESS +ADDRESS +3 +29 + + + + +FPDSCR +FPDSCR +FP Default Status Control Register +0x1B4 +0x20 +read-write +0x00000000 + + +RMode +RMode +22 +2 + + +FZ +FZ +24 +1 + + +DN +DN +25 +1 + + +AHP +AHP +26 +1 + + + + +MVFR0 +MVFR0 +Media and VFP Feature Register 0 +0x1B8 +0x20 +read-only +0x10110021 + + +A_SIMD +A_SIMD registers +0 +4 + + +Single_precision +Single_precision +4 +4 + + +Double_precision +Double_precision +8 +4 + + +FP_exception_trapping +FP exception trapping +12 +4 + + +Divide +Divide +16 +4 + + +Square_root +Square root +20 +4 + + +Short_vectors +Short vectors +24 +4 + + +FP_rounding_modes +FP rounding modes +28 +4 + + + + +MVFR1 +MVFR1 +Media and VFP Feature Register 1 +0x1BC +0x20 +read-only +0x11000011 + + +FtZ_mode +FtZ mode +0 +4 + + +D_NaN_mode +D_NaN mode +4 +4 + + +FP_HPFP +FP HPFP +24 +4 + + +FP_fused_MAC +FP fused MAC +28 +4 + + + + + + +DBGMCU +Debug support +DBGMCU +0xE0042000 + +0x0 +0x400 +registers + + + +IDCODE +IDCODE +MCU Device ID Code Register +0x0 +0x20 +read-only +0x0 + + +DEV_ID +Device Identifier +0 +12 + + +REV_ID +Revision Identifier +16 +16 + + + + +CR +CR +Debug MCU Configuration Register +0x4 +0x20 +read-write +0x0 + + +DBG_SLEEP +Debug Sleep mode +0 +1 + + +DBG_STOP +Debug Stop Mode +1 +1 + + +DBG_STANDBY +Debug Standby Mode +2 +1 + + +TRACE_IOEN +Trace pin assignment control +5 +1 + + +TRACE_MODE +Trace pin assignment control +6 +2 + + + + +APB1FZ +APB1FZ +APB Low Freeze Register +0x8 +0x20 +read-write +0x0 + + +DBG_TIM2_STOP +Debug Timer 2 stopped when Core is halted +0 +1 + + +DBG_TIM3_STOP +Debug Timer 3 stopped when Core is halted +1 +1 + + +DBG_TIM4_STOP +Debug Timer 4 stopped when Core is halted +2 +1 + + +DBG_TIM5_STOP +Debug Timer 5 stopped when Core is halted +3 +1 + + +DBG_TIM6_STOP +Debug Timer 6 stopped when Core is halted +4 +1 + + +DBG_TIM7_STOP +Debug Timer 7 stopped when Core is halted +5 +1 + + +DBG_TIM12_STOP +Debug Timer 12 stopped when Core is halted +6 +1 + + +DBG_TIM13_STOP +Debug Timer 13 stopped when Core is halted +7 +1 + + +DBG_TIMER14_STOP +Debug Timer 14 stopped when Core is halted +8 +1 + + +DBG_TIM18_STOP +Debug Timer 18 stopped when Core is halted +9 +1 + + +DBG_RTC_STOP +Debug RTC stopped when Core is halted +10 +1 + + +DBG_WWDG_STOP +Debug Window Wachdog stopped when Core is halted +11 +1 + + +DBG_IWDG_STOP +Debug Independent Wachdog stopped when Core is halted +12 +1 + + +I2C1_SMBUS_TIMEOUT +SMBUS timeout mode stopped when Core is halted +21 +1 + + +I2C2_SMBUS_TIMEOUT +SMBUS timeout mode stopped when Core is halted +22 +1 + + +DBG_CAN_STOP +Debug CAN stopped when core is halted +25 +1 + + + + +APB2FZ +APB2FZ +APB High Freeze Register +0xC +0x20 +read-write +0x0 + + +DBG_TIM15_STOP +Debug Timer 15 stopped when Core is halted +2 +1 + + +DBG_TIM16_STOP +Debug Timer 16 stopped when Core is halted +3 +1 + + +DBG_TIM17_STO +Debug Timer 17 stopped when Core is halted +4 +1 + + +DBG_TIM19_STOP +Debug Timer 19 stopped when Core is halted +5 +1 + + + + + + +TIM1 +Advanced timer +TIMs +0x40012C00 + +0x0 +0x400 +registers + + +TIM1_CC +TIM1 capture compare interrupt +27 + + + +CR1 +CR1 +control register 1 +0x0 +0x20 +read-write +0x0000 + + +CEN +Counter enable +0 +1 + + +UDIS +Update disable +1 +1 + + +URS +Update request source +2 +1 + + +OPM +One-pulse mode +3 +1 + + +DIR +Direction +4 +1 + + +CMS +Center-aligned mode selection +5 +2 + + +ARPE +Auto-reload preload enable +7 +1 + + +CKD +Clock division +8 +2 + + +UIFREMAP +UIF status bit remapping +11 +1 + + + + +CR2 +CR2 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+14 +1 + + +ETP +External trigger polarity +15 +1 + + +SMS3 +Slave mode selection bit 3 +16 +1 + + + + +DIER +DIER +DMA/Interrupt enable register +0xC +0x20 +read-write +0x0000 + + +TDE +Trigger DMA request enable +14 +1 + + +COMDE +Reserved +13 +1 + + +CC4DE +Capture/Compare 4 DMA request enable +12 +1 + + +CC3DE +Capture/Compare 3 DMA request enable +11 +1 + + +CC2DE +Capture/Compare 2 DMA request enable +10 +1 + + +CC1DE +Capture/Compare 1 DMA request enable +9 +1 + + +UDE +Update DMA request enable +8 +1 + + +BIE +Break interrupt enable +7 +1 + + +TIE +Trigger interrupt enable +6 +1 + + +COMIE +COM interrupt enable +5 +1 + + +CC4IE +Capture/Compare 4 interrupt enable +4 +1 + + +CC3IE +Capture/Compare 3 interrupt enable +3 +1 + + +CC2IE +Capture/Compare 2 interrupt enable +2 +1 + + +CC1IE +Capture/Compare 1 interrupt enable +1 +1 + + +UIE +Update interrupt enable +0 +1 + + + + +SR +SR +status register +0x10 +0x20 +read-write +0x0000 + + +UIF +Update interrupt flag +0 +1 + + +CC1IF +Capture/compare 1 interrupt flag +1 +1 + + +CC2IF +Capture/Compare 2 interrupt flag +2 +1 + + +CC3IF +Capture/Compare 3 interrupt flag +3 +1 + + +CC4IF +Capture/Compare 4 interrupt flag +4 +1 + + +COMIF +COM interrupt flag +5 +1 + + +TIF +Trigger interrupt flag +6 +1 + + +BIF +Break interrupt flag +7 +1 + + +B2IF +Break 2 interrupt flag +8 +1 + + +CC1OF +Capture/Compare 1 overcapture flag +9 +1 + + +CC2OF +Capture/compare 2 overcapture flag +10 +1 + + +CC3OF +Capture/Compare 3 overcapture flag +11 +1 + + +CC4OF +Capture/Compare 4 overcapture flag +12 +1 + + +C5IF +Capture/Compare 5 interrupt flag +16 +1 + + +C6IF +Capture/Compare 6 interrupt flag +17 +1 + + + + +EGR +EGR +event generation register +0x14 +0x20 +write-only +0x0000 + + +UG +Update generation +0 +1 + + +CC1G +Capture/compare 1 generation +1 +1 + + +CC2G +Capture/compare 2 generation +2 +1 + + +CC3G +Capture/compare 3 generation +3 +1 + + +CC4G +Capture/compare 4 generation +4 +1 + + +COMG +Capture/Compare control update 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prescaler +10 +2 + + +CC2S +Capture/Compare 2 selection +8 +2 + + +IC1F +Input capture 1 filter +4 +4 + + +IC1PCS +Input capture 1 prescaler +2 +2 + + +CC1S +Capture/Compare 1 selection +0 +2 + + + + +CCMR2_Output +CCMR2_Output +capture/compare mode register (output mode) +0x1C +0x20 +read-write +0x00000000 + + +OC4CE +Output compare 4 clear enable +15 +1 + + +OC4M +Output compare 4 mode +12 +3 + + +OC4PE +Output compare 4 preload enable +11 +1 + + +OC4FE +Output compare 4 fast enable +10 +1 + + +CC4S +Capture/Compare 4 selection +8 +2 + + +OC3CE +Output compare 3 clear enable +7 +1 + + +OC3M +Output compare 3 mode +4 +3 + + +OC3PE +Output compare 3 preload enable +3 +1 + + +OC3FE +Output compare 3 fast enable +2 +1 + + +CC3S +Capture/Compare 3 selection +0 +2 + + +OC3M_3 +Output Compare 3 mode bit 3 +16 +1 + + +OC4M_3 +Output Compare 4 mode bit 3 +24 +1 + + + + +CCMR2_Input +CCMR2_Input +capture/compare mode register 2 (input mode) +CCMR2_Output +0x1C +0x20 +read-write +0x00000000 + + +IC4F +Input capture 4 filter +12 +4 + + +IC4PSC +Input capture 4 prescaler +10 +2 + + +CC4S +Capture/Compare 4 selection +8 +2 + + +IC3F +Input capture 3 filter +4 +4 + + +IC3PSC +Input capture 3 prescaler +2 +2 + + +CC3S +Capture/compare 3 selection +0 +2 + + + + +CCER +CCER +capture/compare enable register +0x20 +0x20 +read-write +0x0000 + + +CC1E +Capture/Compare 1 output enable +0 +1 + + +CC1P +Capture/Compare 1 output Polarity +1 +1 + + +CC1NE +Capture/Compare 1 complementary output enable +2 +1 + + +CC1NP +Capture/Compare 1 output Polarity +3 +1 + + +CC2E +Capture/Compare 2 output enable +4 +1 + + +CC2P +Capture/Compare 2 output Polarity +5 +1 + + +CC2NE +Capture/Compare 2 complementary output enable +6 +1 + + +CC2NP +Capture/Compare 2 output Polarity +7 +1 + + +CC3E +Capture/Compare 3 output enable +8 +1 + + +CC3P +Capture/Compare 3 output Polarity +9 +1 + + +CC3NE +Capture/Compare 3 complementary output enable +10 +1 + + +CC3NP +Capture/Compare 3 output Polarity +11 +1 + + +CC4E +Capture/Compare 4 output enable +12 +1 + + +CC4P +Capture/Compare 3 output Polarity +13 +1 + + +CC4NP +Capture/Compare 4 output Polarity +15 +1 + + +CC5E +Capture/Compare 5 output enable +16 +1 + + +CC5P +Capture/Compare 5 output Polarity +17 +1 + + +CC6E +Capture/Compare 6 output enable +20 +1 + + +CC6P +Capture/Compare 6 output Polarity +21 +1 + + + + +CNT +CNT +counter +0x24 +0x20 +0x00000000 + + +CNT +counter value +0 +16 +read-write + + +UIFCPY +UIF copy +31 +1 +read-only + + + + +PSC +PSC +prescaler +0x28 +0x20 +read-write +0x0000 + + +PSC +Prescaler value +0 +16 + + + + +ARR +ARR +auto-reload register +0x2C +0x20 +read-write +0x00000000 + + +ARR +Auto-reload value +0 +16 + + + + +RCR +RCR +repetition counter register +0x30 +0x20 +read-write +0x0000 + + +REP +Repetition counter value +0 +16 + + + + +CCR1 +CCR1 +capture/compare register 1 +0x34 +0x20 +read-write +0x00000000 + + +CCR1 +Capture/Compare 1 value +0 +16 + + + + +CCR2 +CCR2 +capture/compare register 2 +0x38 +0x20 +read-write +0x00000000 + + +CCR2 +Capture/Compare 2 value +0 +16 + + + + +CCR3 +CCR3 +capture/compare register 3 +0x3C +0x20 +read-write +0x00000000 + + +CCR3 +Capture/Compare 3 value +0 +16 + + + + +CCR4 +CCR4 +capture/compare register 4 +0x40 +0x20 +read-write +0x00000000 + + +CCR4 +Capture/Compare 3 value +0 +16 + + + + +BDTR +BDTR +break and dead-time register +0x44 +0x20 +read-write +0x00000000 + + +DTG +Dead-time generator setup +0 +8 + + +LOCK +Lock configuration +8 +2 + + +OSSI +Off-state selection for Idle mode +10 +1 + + +OSSR +Off-state selection for Run mode +11 +1 + + +BKE +Break enable +12 +1 + + +BKP +Break polarity +13 +1 + + +AOE +Automatic output enable +14 +1 + + +MOE +Main output enable +15 +1 + + +BKF +Break filter +16 +4 + + +BK2F +Break 2 filter +20 +4 + + +BK2E +Break 2 enable +24 +1 + + +BK2P +Break 2 polarity +25 +1 + + + + +DCR +DCR +DMA control register +0x48 +0x20 +read-write +0x00000000 + + +DBL +DMA burst length +8 +5 + + +DBA +DMA base address +0 +5 + + + + +DMAR +DMAR +DMA address for full transfer +0x4C +0x20 +read-write +0x00000000 + + +DMAB +DMA register for burst accesses +0 +16 + + + + +CCMR3_Output +CCMR3_Output +capture/compare mode register 3 (output mode) +0x54 +0x20 +read-write +0x00000000 + + +OC5FE +Output compare 5 fast enable +2 +1 + + +OC5PE +Output compare 5 preload enable +3 +1 + + +OC5M +Output compare 5 mode +4 +3 + + +OC5CE +Output compare 5 clear enable +7 +1 + + +OC6FE +Output compare 6 fast enable +10 +1 + + +OC6PE +Output compare 6 preload enable +11 +1 + + +OC6M +Output compare 6 mode +12 +3 + + +OC6CE +Output compare 6 clear enable +15 +1 + + +OC5M_3 +Outout Compare 5 mode bit 3 +16 +1 + + +OC6M_3 +Outout Compare 6 mode bit 3 +24 +1 + + + + +CCR5 +CCR5 +capture/compare register 5 +0x58 +0x20 +read-write +0x00000000 + + +CCR5 +Capture/Compare 5 value +0 +16 + + +GC5C1 +Group Channel 5 and Channel 1 +29 +1 + + +GC5C2 +Group Channel 5 and Channel 2 +30 +1 + + +GC5C3 +Group Channel 5 and Channel 3 +31 +1 + + + + +CCR6 +CCR6 +capture/compare register 6 +0x5C +0x20 +read-write +0x00000000 + + +CCR6 +Capture/Compare 6 value +0 +16 + + + + +OR +OR +option registers +0x60 +0x20 +read-write +0x00000000 + + +TIM1_ETR_ADC1_RMP +TIM1_ETR_ADC1 remapping capability +0 +2 + + +TIM1_ETR_ADC4_RMP +TIM1_ETR_ADC4 remapping capability +2 +2 + + + + + + +TIM20 +0x40015000 + +TIM1_CC +TIM1 capture compare interrupt +27 + + + +TIM8 +Advanced-timers +TIMs +0x40013400 + +0x0 +0x400 +registers + + +TIM8_BRK +TIM8 break interrupt +43 + + +TIM8_UP +TIM8 update interrupt +44 + + +TIM8_TRG_COM +TIM8 Trigger and commutation + interrupts +45 + + +TIM8_CC +TIM8 capture compare interrupt +46 + + + +CR1 +CR1 +control register 1 +0x0 +0x20 +read-write +0x0000 + + +CEN +Counter enable +0 +1 + + +UDIS +Update disable +1 +1 + + +URS +Update request source +2 +1 + + +OPM +One-pulse mode +3 +1 + + +DIR +Direction +4 +1 + + +CMS +Center-aligned mode selection +5 +2 + + +ARPE +Auto-reload preload enable +7 +1 + + +CKD +Clock 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+4 + + +ETPS +External trigger prescaler +12 +2 + + +ECE +External clock enable +14 +1 + + +ETP +External trigger polarity +15 +1 + + +SMS3 +Slave mode selection bit 3 +16 +1 + + + + +DIER +DIER +DMA/Interrupt enable register +0xC +0x20 +read-write +0x0000 + + +TDE +Trigger DMA request enable +14 +1 + + +COMDE +Reserved +13 +1 + + +CC4DE +Capture/Compare 4 DMA request enable +12 +1 + + +CC3DE +Capture/Compare 3 DMA request enable +11 +1 + + +CC2DE +Capture/Compare 2 DMA request enable +10 +1 + + +CC1DE +Capture/Compare 1 DMA request enable +9 +1 + + +UDE +Update DMA request enable +8 +1 + + +BIE +Break interrupt enable +7 +1 + + +TIE +Trigger interrupt enable +6 +1 + + +COMIE +COM interrupt enable +5 +1 + + +CC4IE +Capture/Compare 4 interrupt enable +4 +1 + + +CC3IE +Capture/Compare 3 interrupt enable +3 +1 + + +CC2IE +Capture/Compare 2 interrupt enable +2 +1 + + +CC1IE +Capture/Compare 1 interrupt enable +1 +1 + + +UIE +Update interrupt enable +0 +1 + + + + +SR +SR +status register +0x10 +0x20 +read-write +0x0000 + + +UIF +Update interrupt flag +0 +1 + + +CC1IF +Capture/compare 1 interrupt flag +1 +1 + + +CC2IF +Capture/Compare 2 interrupt flag +2 +1 + + +CC3IF +Capture/Compare 3 interrupt flag +3 +1 + + +CC4IF +Capture/Compare 4 interrupt flag +4 +1 + + +COMIF +COM interrupt flag +5 +1 + + +TIF +Trigger interrupt flag +6 +1 + + +BIF +Break interrupt flag +7 +1 + + +B2IF +Break 2 interrupt flag +8 +1 + + +CC1OF +Capture/Compare 1 overcapture flag +9 +1 + + +CC2OF +Capture/compare 2 overcapture flag +10 +1 + + +CC3OF +Capture/Compare 3 overcapture flag +11 +1 + + +CC4OF +Capture/Compare 4 overcapture flag +12 +1 + + +C5IF +Capture/Compare 5 interrupt flag +16 +1 + + +C6IF +Capture/Compare 6 interrupt flag +17 +1 + + + + +EGR +EGR +event generation register +0x14 +0x20 +write-only +0x0000 + + +UG +Update generation +0 +1 + + +CC1G +Capture/compare 1 generation +1 +1 + + +CC2G +Capture/compare 2 generation +2 +1 + + +CC3G +Capture/compare 3 generation +3 +1 + + +CC4G +Capture/compare 4 generation +4 +1 + + +COMG +Capture/Compare control update generation +5 +1 + + +TG +Trigger generation +6 +1 + + +BG +Break generation +7 +1 + + +B2G +Break 2 generation +8 +1 + + + + +CCMR1_Output +CCMR1_Output +capture/compare mode register (output mode) +0x18 +0x20 +read-write +0x00000000 + + +OC2CE +Output Compare 2 clear enable +15 +1 + + +OC2M +Output Compare 2 mode +12 +3 + + +OC2PE +Output Compare 2 preload enable +11 +1 + + +OC2FE +Output Compare 2 fast enable +10 +1 + + +CC2S +Capture/Compare 2 selection +8 +2 + + +OC1CE +Output Compare 1 clear enable +7 +1 + + +OC1M +Output Compare 1 mode +4 +3 + + +OC1PE +Output Compare 1 preload enable +3 +1 + + +OC1FE +Output Compare 1 fast enable +2 +1 + + +CC1S +Capture/Compare 1 selection +0 +2 + + +OC1M_3 +Output Compare 1 mode bit 3 +16 +1 + + +OC2M_3 +Output Compare 2 mode bit 3 +24 +1 + + + + +CCMR1_Input +CCMR1_Input +capture/compare mode register 1 (input mode) +CCMR1_Output +0x18 +0x20 +read-write +0x00000000 + + +IC2F +Input capture 2 filter +12 +4 + + +IC2PCS +Input capture 2 prescaler +10 +2 + + +CC2S +Capture/Compare 2 selection +8 +2 + + +IC1F +Input capture 1 filter +4 +4 + + +IC1PCS +Input capture 1 prescaler +2 +2 + + +CC1S +Capture/Compare 1 selection +0 +2 + + + + +CCMR2_Output +CCMR2_Output +capture/compare mode register (output mode) +0x1C +0x20 +read-write +0x00000000 + + +OC4CE +Output compare 4 clear enable +15 +1 + + +OC4M +Output compare 4 mode +12 +3 + + +OC4PE +Output compare 4 preload enable +11 +1 + + +OC4FE +Output compare 4 fast enable +10 +1 + + +CC4S +Capture/Compare 4 selection +8 +2 + + +OC3CE +Output compare 3 clear enable +7 +1 + + +OC3M +Output compare 3 mode +4 +3 + + +OC3PE +Output compare 3 preload enable +3 +1 + + +OC3FE +Output compare 3 fast enable +2 +1 + + +CC3S +Capture/Compare 3 selection +0 +2 + + +OC3M_3 +Output Compare 3 mode bit 3 +16 +1 + + +OC4M_3 +Output Compare 4 mode bit 3 +24 +1 + + + + +CCMR2_Input +CCMR2_Input +capture/compare mode register 2 (input mode) +CCMR2_Output +0x1C +0x20 +read-write +0x00000000 + + +IC4F +Input capture 4 filter +12 +4 + + +IC4PSC +Input capture 4 prescaler +10 +2 + + +CC4S +Capture/Compare 4 selection +8 +2 + + +IC3F +Input capture 3 filter +4 +4 + + +IC3PSC +Input capture 3 prescaler +2 +2 + + +CC3S +Capture/compare 3 selection +0 +2 + + + + +CCER +CCER +capture/compare enable register +0x20 +0x20 +read-write +0x0000 + + +CC1E +Capture/Compare 1 output enable +0 +1 + + +CC1P +Capture/Compare 1 output Polarity +1 +1 + + +CC1NE +Capture/Compare 1 complementary output enable +2 +1 + + +CC1NP +Capture/Compare 1 output Polarity +3 +1 + + +CC2E +Capture/Compare 2 output enable +4 +1 + + +CC2P +Capture/Compare 2 output Polarity +5 +1 + + +CC2NE +Capture/Compare 2 complementary output enable +6 +1 + + +CC2NP +Capture/Compare 2 output Polarity +7 +1 + + +CC3E +Capture/Compare 3 output enable +8 +1 + + +CC3P +Capture/Compare 3 output Polarity +9 +1 + + +CC3NE +Capture/Compare 3 complementary output enable +10 +1 + + +CC3NP +Capture/Compare 3 output Polarity +11 +1 + + +CC4E +Capture/Compare 4 output enable +12 +1 + + +CC4P +Capture/Compare 3 output Polarity +13 +1 + + +CC4NP +Capture/Compare 4 output Polarity +15 +1 + + +CC5E +Capture/Compare 5 output enable +16 +1 + + +CC5P +Capture/Compare 5 output Polarity +17 +1 + + +CC6E +Capture/Compare 6 output enable +20 +1 + + +CC6P +Capture/Compare 6 output Polarity +21 +1 + + + + +CNT +CNT +counter +0x24 +0x20 +0x00000000 + + +CNT +counter value +0 +16 +read-write + + +UIFCPY +UIF copy +31 +1 +read-only + + + + +PSC +PSC +prescaler +0x28 +0x20 +read-write +0x0000 + + +PSC +Prescaler value +0 +16 + + + + +ARR +ARR +auto-reload register +0x2C +0x20 +read-write +0x00000000 + + +ARR +Auto-reload value +0 +16 + + + + +RCR +RCR +repetition counter register +0x30 +0x20 +read-write +0x0000 + + +REP +Repetition counter value +0 +16 + + + + +CCR1 +CCR1 +capture/compare register 1 +0x34 +0x20 +read-write +0x00000000 + + +CCR1 +Capture/Compare 1 value +0 +16 + + + + +CCR2 +CCR2 +capture/compare register 2 +0x38 +0x20 +read-write +0x00000000 + + +CCR2 +Capture/Compare 2 value +0 +16 + + + + +CCR3 +CCR3 +capture/compare register 3 +0x3C +0x20 +read-write +0x00000000 + + +CCR3 +Capture/Compare 3 value +0 +16 + + + + +CCR4 +CCR4 +capture/compare register 4 +0x40 +0x20 +read-write +0x00000000 + + +CCR4 +Capture/Compare 3 value +0 +16 + + + + +BDTR +BDTR +break and dead-time register +0x44 +0x20 +read-write +0x00000000 + + +DTG +Dead-time generator setup +0 +8 + + +LOCK +Lock configuration +8 +2 + + +OSSI +Off-state selection for Idle mode +10 +1 + + +OSSR +Off-state selection for Run mode +11 +1 + + +BKE +Break enable +12 +1 + + +BKP +Break polarity +13 +1 + + +AOE +Automatic output enable +14 +1 + + +MOE +Main output enable +15 +1 + + +BKF +Break filter +16 +4 + + +BK2F +Break 2 filter +20 +4 + + +BK2E +Break 2 enable +24 +1 + + +BK2P +Break 2 polarity +25 +1 + + + + +DCR +DCR +DMA control register +0x48 +0x20 +read-write +0x00000000 + + +DBL +DMA burst length +8 +5 + + +DBA +DMA base address +0 +5 + + + + +DMAR +DMAR +DMA address for full transfer +0x4C +0x20 +read-write +0x00000000 + + +DMAB +DMA register for burst accesses +0 +16 + + + + +CCMR3_Output +CCMR3_Output +capture/compare mode register 3 (output mode) +0x54 +0x20 +read-write +0x00000000 + + +OC5FE +Output compare 5 fast enable +2 +1 + + +OC5PE +Output compare 5 preload enable +3 +1 + + +OC5M +Output compare 5 mode +4 +3 + + +OC5CE +Output compare 5 clear enable +7 +1 + + +OC6FE +Output compare 6 fast enable +10 +1 + + +OC6PE +Output compare 6 preload enable +11 +1 + + +OC6M +Output compare 6 mode +12 +3 + + +OC6CE +Output compare 6 clear enable +15 +1 + + +OC5M_3 +Outout Compare 5 mode bit 3 +16 +1 + + +OC6M_3 +Outout Compare 6 mode bit 3 +24 +1 + + + + +CCR5 +CCR5 +capture/compare register 5 +0x58 +0x20 +read-write +0x00000000 + + +CCR5 +Capture/Compare 5 value +0 +16 + + +GC5C1 +Group Channel 5 and Channel 1 +29 +1 + + +GC5C2 +Group Channel 5 and Channel 2 +30 +1 + + +GC5C3 +Group Channel 5 and Channel 3 +31 +1 + + + + +CCR6 +CCR6 +capture/compare register 6 +0x5C +0x20 +read-write +0x00000000 + + +CCR6 +Capture/Compare 6 value +0 +16 + + + + +OR +OR +option registers +0x60 +0x20 +read-write +0x00000000 + + +TIM8_ETR_ADC2_RMP +TIM8_ETR_ADC2 remapping capability +0 +2 + + +TIM8_ETR_ADC3_RMP +TIM8_ETR_ADC3 remapping capability +2 +2 + + + + + + +ADC1 +Analog-to-Digital Converter +ADC +0x50000000 + +0x0 +0x100 +registers + + +ADC1_2 +ADC1 and ADC2 global interrupt +18 + + + +ISR +ISR +interrupt and status register +0x0 +0x20 +read-write +0x00000000 + + +JQOVF +JQOVF +10 +1 + + +AWD3 +AWD3 +9 +1 + + +AWD2 +AWD2 +8 +1 + + +AWD1 +AWD1 +7 +1 + + +JEOS +JEOS +6 +1 + + +JEOC +JEOC +5 +1 + + +OVR +OVR +4 +1 + + +EOS +EOS +3 +1 + + +EOC +EOC +2 +1 + + +EOSMP +EOSMP +1 +1 + + +ADRDY +ADRDY +0 +1 + + + + +IER +IER +interrupt enable register +0x4 +0x20 +read-write +0x00000000 + + +JQOVFIE +JQOVFIE +10 +1 + + +AWD3IE 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+OVRMOD +12 +1 + + +EXTEN +EXTEN +10 +2 + + +EXTSEL +EXTSEL +6 +4 + + +ALIGN +ALIGN +5 +1 + + +RES +RES +3 +2 + + +DMACFG +DMACFG +1 +1 + + +DMAEN +DMAEN +0 +1 + + + + +SMPR1 +SMPR1 +sample time register 1 +0x14 +0x20 +read-write +0x00000000 + + +SMP9 +SMP9 +27 +3 + + +SMP8 +SMP8 +24 +3 + + +SMP7 +SMP7 +21 +3 + + +SMP6 +SMP6 +18 +3 + + +SMP5 +SMP5 +15 +3 + + +SMP4 +SMP4 +12 +3 + + +SMP3 +SMP3 +9 +3 + + +SMP2 +SMP2 +6 +3 + + +SMP1 +SMP1 +3 +3 + + + + +SMPR2 +SMPR2 +sample time register 2 +0x18 +0x20 +read-write +0x00000000 + + +SMP18 +SMP18 +24 +3 + + +SMP17 +SMP17 +21 +3 + + +SMP16 +SMP16 +18 +3 + + +SMP15 +SMP15 +15 +3 + + +SMP14 +SMP14 +12 +3 + + +SMP13 +SMP13 +9 +3 + + +SMP12 +SMP12 +6 +3 + + +SMP11 +SMP11 +3 +3 + + +SMP10 +SMP10 +0 +3 + + + + +TR1 +TR1 +watchdog threshold register 1 +0x20 +0x20 +read-write +0x0FFF0000 + + +HT1 +HT1 +16 +12 + + +LT1 +LT1 +0 +12 + + + + +TR2 +TR2 +watchdog threshold register +0x24 +0x20 +read-write +0x0FFF0000 + + +HT2 +HT2 +16 +8 + + +LT2 +LT2 +0 +8 + + + + +TR3 +TR3 +watchdog threshold register 3 +0x28 +0x20 +read-write +0x0FFF0000 + + +HT3 +HT3 +16 +8 + + +LT3 +LT3 +0 +8 + + + + +SQR1 +SQR1 +regular sequence register 1 +0x30 +0x20 +read-write +0x00000000 + + +SQ4 +SQ4 +24 +5 + + +SQ3 +SQ3 +18 +5 + + +SQ2 +SQ2 +12 +5 + + +SQ1 +SQ1 +6 +5 + + +L3 +L3 +0 +4 + + + + +SQR2 +SQR2 +regular sequence register 2 +0x34 +0x20 +read-write +0x00000000 + + +SQ9 +SQ9 +24 +5 + + +SQ8 +SQ8 +18 +5 + + +SQ7 +SQ7 +12 +5 + + +SQ6 +SQ6 +6 +5 + + +SQ5 +SQ5 +0 +5 + + + + +SQR3 +SQR3 +regular sequence register 3 +0x38 +0x20 +read-write +0x00000000 + + +SQ14 +SQ14 +24 +5 + + +SQ13 +SQ13 +18 +5 + + +SQ12 +SQ12 +12 +5 + + +SQ11 +SQ11 +6 +5 + + +SQ10 +SQ10 +0 +5 + + + + +SQR4 +SQR4 +regular sequence register 4 +0x3C +0x20 +read-write +0x00000000 + + +SQ16 +SQ16 +6 +5 + + +SQ15 +SQ15 +0 +5 + + + + +DR +DR +regular Data Register +0x40 +0x20 +read-only +0x00000000 + + +regularDATA +regularDATA +0 +16 + + + + +JSQR +JSQR +injected sequence register +0x4C +0x20 +read-write +0x00000000 + + +JSQ4 +JSQ4 +26 +5 + + +JSQ3 +JSQ3 +20 +5 + + +JSQ2 +JSQ2 +14 +5 + + +JSQ1 +JSQ1 +8 +5 + + +JEXTEN +JEXTEN +6 +2 + + +JEXTSEL +JEXTSEL +2 +4 + + +JL +JL +0 +2 + + + + +OFR1 +OFR1 +offset register 1 +0x60 +0x20 +read-write +0x00000000 + + +OFFSET1_EN +OFFSET1_EN +31 +1 + + +OFFSET1_CH +OFFSET1_CH +26 +5 + + +OFFSET1 +OFFSET1 +0 +12 + + + + +OFR2 +OFR2 +offset register 2 +0x64 +0x20 +read-write +0x00000000 + + +OFFSET2_EN +OFFSET2_EN +31 +1 + + +OFFSET2_CH +OFFSET2_CH +26 +5 + + +OFFSET2 +OFFSET2 +0 +12 + + + + +OFR3 +OFR3 +offset register 3 +0x68 +0x20 +read-write +0x00000000 + + +OFFSET3_EN +OFFSET3_EN +31 +1 + + +OFFSET3_CH +OFFSET3_CH +26 +5 + + +OFFSET3 +OFFSET3 +0 +12 + + + + +OFR4 +OFR4 +offset register 4 +0x6C +0x20 +read-write +0x00000000 + + +OFFSET4_EN +OFFSET4_EN +31 +1 + + +OFFSET4_CH +OFFSET4_CH +26 +5 + + +OFFSET4 +OFFSET4 +0 +12 + + + + +JDR1 +JDR1 +injected data register 1 +0x80 +0x20 +read-only +0x00000000 + + +JDATA1 +JDATA1 +0 +16 + + + + +JDR2 +JDR2 +injected data register 2 +0x84 +0x20 +read-only +0x00000000 + + +JDATA2 +JDATA2 +0 +16 + + + + +JDR3 +JDR3 +injected data register 3 +0x88 +0x20 +read-only +0x00000000 + + +JDATA3 +JDATA3 +0 +16 + + + + +JDR4 +JDR4 +injected data register 4 +0x8C +0x20 +read-only +0x00000000 + + +JDATA4 +JDATA4 +0 +16 + + + + +AWD2CR +AWD2CR +Analog Watchdog 2 Configuration Register +0xA0 +0x20 +read-write +0x00000000 + + +AWD2CH +AWD2CH +1 +18 + + + + +AWD3CR +AWD3CR +Analog Watchdog 3 Configuration Register +0xA4 +0x20 +read-write +0x00000000 + + +AWD3CH +AWD3CH +1 +18 + + + + +DIFSEL +DIFSEL +Differential Mode Selection Register 2 +0xB0 +0x20 +0x00000000 + + +DIFSEL_1_15 +Differential mode for channels 15 to 1 +1 +15 +read-write + + +DIFSEL_16_18 +Differential mode for channels 18 to 16 +16 +3 +read-only + + + + +CALFACT +CALFACT +Calibration Factors +0xB4 +0x20 +read-write +0x00000000 + + +CALFACT_D +CALFACT_D +16 +7 + + +CALFACT_S +CALFACT_S +0 +7 + + + + + + +ADC2 +0x50000100 + +ADC1_2 +ADC1 and ADC2 global interrupt +18 + + + +ADC3 +0x50000400 + +ADC3 +ADC3 global interrupt +47 + + + +ADC4 +0x50000500 + +ADC4 +ADC4 global interrupt +61 + + + +ADC1_2 +Analog-to-Digital Converter +ADC +0x50000300 + +0x0 +0xD +registers + + + +CSR +CSR +ADC Common status register +0x0 +0x20 +read-only +0x00000000 + + +ADDRDY_MST +ADDRDY_MST +0 +1 + + +EOSMP_MST +EOSMP_MST +1 +1 + + +EOC_MST +EOC_MST +2 +1 + + +EOS_MST +EOS_MST +3 +1 + + +OVR_MST +OVR_MST +4 +1 + + +JEOC_MST +JEOC_MST +5 +1 + + +JEOS_MST +JEOS_MST +6 +1 + + +AWD1_MST +AWD1_MST +7 +1 + + +AWD2_MST +AWD2_MST +8 +1 + + +AWD3_MST +AWD3_MST +9 +1 + + +JQOVF_MST +JQOVF_MST +10 +1 + + +ADRDY_SLV +ADRDY_SLV +16 +1 + + +EOSMP_SLV +EOSMP_SLV +17 +1 + + +EOC_SLV +End of regular conversion of the slave ADC +18 +1 + + +EOS_SLV +End of regular sequence flag of the slave ADC +19 +1 + + +OVR_SLV +Overrun flag of the slave ADC +20 +1 + + +JEOC_SLV +End of injected conversion flag of the slave ADC +21 +1 + + +JEOS_SLV +End of injected sequence flag of the slave ADC +22 +1 + + +AWD1_SLV +Analog watchdog 1 flag of the slave ADC +23 +1 + + +AWD2_SLV +Analog watchdog 2 flag of the slave ADC +24 +1 + + +AWD3_SLV +Analog watchdog 3 flag of the slave ADC +25 +1 + + +JQOVF_SLV +Injected Context Queue Overflow flag of the slave ADC +26 +1 + + + + +CCR +CCR +ADC common control register +0x8 +0x20 +read-write +0x00000000 + + +MULT +Multi ADC mode selection +0 +5 + + +DELAY +Delay between 2 sampling phases +8 +4 + + +DMACFG +DMA configuration (for multi-ADC mode) +13 +1 + + +MDMA +Direct memory access mode for multi ADC mode +14 +2 + + +CKMODE +ADC clock mode +16 +2 + + +VREFEN +VREFINT enable +22 +1 + + +TSEN +Temperature sensor enable +23 +1 + + +VBATEN +VBAT enable +24 +1 + + + + +CDR +CDR +ADC common regular data register for dual and triple modes +0xC +0x20 +read-only +0x00000000 + + +RDATA_SLV +Regular data of the slave ADC +16 +16 + + +RDATA_MST +Regular data of the master ADC +0 +16 + + + + + + +ADC3_4 +0x50000700 + + +SYSCFG +System configuration controller +SYSCFG +0x40010000 + +0x0 +0x19 +registers + + + +CFGR1 +CFGR1 +configuration register 1 +0x0 +0x20 +read-write +0x00000000 + + +MEM_MODE +Memory mapping selection bits +0 +2 + + +USB_IT_RMP +USB interrupt remap +5 +1 + + +TIM1_ITR_RMP +Timer 1 ITR3 selection +6 +1 + + +DAC_TRIG_RMP +DAC trigger remap (when TSEL = 001) +7 +1 + + +ADC24_DMA_RMP +ADC24 DMA remapping bit +8 +1 + + +TIM16_DMA_RMP +TIM16 DMA request remapping bit +11 +1 + + +TIM17_DMA_RMP +TIM17 DMA request remapping bit +12 +1 + + +TIM6_DAC1_DMA_RMP +TIM6 and DAC1 DMA request remapping bit +13 +1 + + +TIM7_DAC2_DMA_RMP +TIM7 and DAC2 DMA request remapping bit +14 +1 + + +I2C_PB6_FM +Fast Mode Plus (FM+) driving capability activation bits. +16 +1 + + +I2C_PB7_FM +Fast Mode Plus (FM+) driving capability activation bits. +17 +1 + + +I2C_PB8_FM +Fast Mode Plus (FM+) driving capability activation bits. +18 +1 + + +I2C_PB9_FM +Fast Mode Plus (FM+) driving capability activation bits. +19 +1 + + +I2C1_FM +I2C1 Fast Mode Plus +20 +1 + + +I2C2_FM +I2C2 Fast Mode Plus +21 +1 + + +ENCODER_MODE +Encoder mode +22 +2 + + +FPU_IT +Interrupt enable bits from FPU +26 +6 + + + + +EXTICR1 +EXTICR1 +external interrupt configuration register 1 +0x8 +0x20 +read-write +0x0000 + + +EXTI3 +EXTI 3 configuration bits +12 +4 + + +EXTI2 +EXTI 2 configuration bits +8 +4 + + +EXTI1 +EXTI 1 configuration bits +4 +4 + + +EXTI0 +EXTI 0 configuration bits +0 +4 + + + + +EXTICR2 +EXTICR2 +external interrupt configuration register 2 +0xC +0x20 +read-write +0x0000 + + +EXTI7 +EXTI 7 configuration bits +12 +4 + + +EXTI6 +EXTI 6 configuration bits +8 +4 + + +EXTI5 +EXTI 5 configuration bits +4 +4 + + +EXTI4 +EXTI 4 configuration bits +0 +4 + + + + +EXTICR3 +EXTICR3 +external interrupt configuration register 3 +0x10 +0x20 +read-write +0x0000 + + +EXTI11 +EXTI 11 configuration bits +12 +4 + + +EXTI10 +EXTI 10 configuration bits +8 +4 + + +EXTI9 +EXTI 9 configuration bits +4 +4 + + +EXTI8 +EXTI 8 configuration bits +0 +4 + + + + +EXTICR4 +EXTICR4 +external interrupt configuration register 4 +0x14 +0x20 +read-write +0x0000 + + +EXTI15 +EXTI 15 configuration bits +12 +4 + + +EXTI14 +EXTI 14 configuration bits +8 +4 + + +EXTI13 +EXTI 13 configuration bits +4 +4 + + +EXTI12 +EXTI 12 configuration bits +0 +4 + + + + +CFGR2 +CFGR2 +configuration register 2 +0x18 +0x20 +read-write +0x0000 + + +LOCUP_LOCK +Cortex-M0 LOCKUP bit enable bit +0 +1 + + +SRAM_PARITY_LOCK +SRAM parity lock bit +1 +1 + + +PVD_LOCK +PVD lock enable bit +2 +1 + + +BYP_ADD_PAR +Bypass address bit 29 in parity calculation +4 +1 + + +SRAM_PEF +SRAM parity flag +8 +1 + + + + +RCR +RCR +CCM SRAM protection register +0x4 +0x20 +read-write +0x0000 + + +PAGE0_WP +CCM SRAM page write protection bit +0 +1 + + +PAGE1_WP +CCM SRAM page write protection bit +1 +1 + + +PAGE2_WP +CCM SRAM page write protection bit +2 +1 + + +PAGE3_WP +CCM SRAM page write protection bit +3 +1 + + +PAGE4_WP +CCM SRAM page write protection bit +4 +1 + + +PAGE5_WP +CCM SRAM page write protection bit +5 +1 + + +PAGE6_WP +CCM SRAM page write protection bit +6 +1 + + +PAGE7_WP +CCM SRAM page write protection bit +7 +1 + + + PAGE8_WP + CCM SRAM page write protection + bit + 8 + 1 + + + PAGE9_WP + CCM SRAM page write protection + bit + 9 + 1 + + + PAGE10_WP + CCM SRAM page write protection + bit + 10 + 1 + + + PAGE11_WP + CCM SRAM page write protection + bit + 11 + 1 + + + PAGE12_WP + CCM SRAM page write protection + bit + 12 + 1 + + + PAGE13_WP + CCM SRAM page write protection + bit + 13 + 1 + + + PAGE14_WP + CCM SRAM page write protection + bit + 14 + 1 + + + PAGE15_WP + CCM SRAM page write protection + bit + 15 + 1 + + + + + + +OPAMP +Operational amplifier +OPAMP +0x40010038 + +0x0 +0x3C8 +registers + + + +OPAMP1_CR +OPAMP1_CR +OPAMP1 control register +0x0 +0x20 +0x00000000 + + +OPAMP1_EN +OPAMP1 enable +0 +1 +read-write + + +FORCE_VP +FORCE_VP +1 +1 +read-write + + +VP_SEL +OPAMP1 Non inverting input selection +2 +2 +read-write + + +VM_SEL +OPAMP1 inverting input selection +5 +2 +read-write + + +TCM_EN +Timer controlled Mux mode enable +7 +1 +read-write + + +VMS_SEL +OPAMP1 inverting input secondary selection +8 +1 +read-write + + +VPS_SEL +OPAMP1 Non inverting input secondary selection +9 +2 +read-write + + +CALON +Calibration mode enable +11 +1 +read-write + + +CALSEL +Calibration selection +12 +2 +read-write + + +PGA_GAIN +Gain in PGA mode +14 +4 +read-write + + +USER_TRIM +User trimming enable +18 +1 +read-write + + +TRIMOFFSETP +Offset trimming value (PMOS) +19 +5 +read-write + + +TRIMOFFSETN +Offset trimming value (NMOS) +24 +5 +read-write + + +TSTREF +TSTREF +29 +1 +read-write + + +OUTCAL +OPAMP 1 ouput status flag +30 +1 +read-only + + +LOCK +OPAMP 1 lock +31 +1 +read-write + + + + +OPAMP2_CR +OPAMP2_CR +OPAMP2 control register +0x4 +0x20 +0x00000000 + + +OPAMP2EN +OPAMP2 enable +0 +1 +read-write + + +FORCE_VP +FORCE_VP +1 +1 +read-write + + +VP_SEL +OPAMP2 Non inverting input selection +2 +2 +read-write + + +VM_SEL +OPAMP2 inverting input selection +5 +2 +read-write + + +TCM_EN +Timer controlled Mux mode enable +7 +1 +read-write + + +VMS_SEL +OPAMP2 inverting input secondary selection +8 +1 +read-write + + +VPS_SEL +OPAMP2 Non inverting input secondary selection +9 +2 +read-write + + +CALON +Calibration mode enable +11 +1 +read-write + + +CAL_SEL +Calibration selection +12 +2 +read-write + + +PGA_GAIN +Gain in PGA mode +14 +4 +read-write + + +USER_TRIM +User trimming enable +18 +1 +read-write + + +TRIMOFFSETP +Offset trimming value (PMOS) +19 +5 +read-write + + +TRIMOFFSETN +Offset trimming value (NMOS) +24 +5 +read-write + + +TSTREF +TSTREF +29 +1 +read-write + + +OUTCAL +OPAMP 2 ouput status flag +30 +1 +read-only + + +LOCK +OPAMP 2 lock +31 +1 +read-write + + + + +OPAMP3_CR +OPAMP3_CR +OPAMP3 control register +0x8 +0x20 +0x00000000 + + +OPAMP3EN +OPAMP3 enable +0 +1 +read-write + + +FORCE_VP +FORCE_VP +1 +1 +read-write + + +VP_SEL +OPAMP3 Non inverting input selection +2 +2 +read-write + + +VM_SEL +OPAMP3 inverting input selection +5 +2 +read-write + + +TCM_EN +Timer controlled Mux mode enable +7 +1 +read-write + + +VMS_SEL +OPAMP3 inverting input secondary selection +8 +1 +read-write + + +VPS_SEL +OPAMP3 Non inverting input secondary selection +9 +2 +read-write + + +CALON +Calibration mode enable +11 +1 +read-write + + +CALSEL +Calibration selection +12 +2 +read-write + + +PGA_GAIN +Gain in PGA mode +14 +4 +read-write + + +USER_TRIM +User trimming enable +18 +1 +read-write + + +TRIMOFFSETP +Offset trimming value (PMOS) +19 +5 +read-write + + +TRIMOFFSETN +Offset trimming value (NMOS) +24 +5 +read-write + + +TSTREF +TSTREF +29 +1 +read-write + + +OUTCAL +OPAMP 3 ouput status flag +30 +1 +read-only + + +LOCK +OPAMP 3 lock +31 +1 +read-write + + + + +OPAMP4_CR +OPAMP4_CR +OPAMP4 control register +0xC +0x20 +0x00000000 + + +OPAMP4EN +OPAMP4 enable +0 +1 +read-write + + +FORCE_VP +FORCE_VP +1 +1 +read-write + + +VP_SEL +OPAMP4 Non inverting input selection +2 +2 +read-write + + +VM_SEL +OPAMP4 inverting input selection +5 +2 +read-write + + +TCM_EN +Timer controlled Mux mode enable +7 +1 +read-write + + +VMS_SEL +OPAMP4 inverting input secondary selection +8 +1 +read-write + + +VPS_SEL +OPAMP4 Non inverting input secondary selection +9 +2 +read-write + + +CALON +Calibration mode enable +11 +1 +read-write + + +CALSEL +Calibration selection +12 +2 +read-write + + +PGA_GAIN +Gain in PGA mode +14 +4 +read-write + + +USER_TRIM +User trimming enable +18 +1 +read-write + + +TRIMOFFSETP +Offset trimming value (PMOS) +19 +5 +read-write + + +TRIMOFFSETN +Offset trimming value (NMOS) +24 +5 +read-write + + +TSTREF +TSTREF +29 +1 +read-write + + +OUTCAL +OPAMP 4 ouput status flag +30 +1 +read-only + + +LOCK +OPAMP 4 lock +31 +1 +read-write + + + + + + + \ No newline at end of file