[wip] generator controller
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277
firmware/shared_libs/controllers/ctrl_generator.c
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277
firmware/shared_libs/controllers/ctrl_generator.c
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#include "main.h"
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#include "spi.h"
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#include "i2c.h"
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#include "ctrl_app_types.h"
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#include "ctrl_app.h"
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#include "ad9833.h"
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#include "ltc2631.h"
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#include "mcp41x.h"
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#include "ctrl_generator.h"
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typedef struct FG_handle_s FG_handle_t;
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struct FG_handle_s
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{
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ad9833_handle_t hdds;
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ltc2631_handle_t hoffs;
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mcp41x_handle_t hampl;
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FG_handle_t *link[2];
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};
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typedef uint8_t timer_handle_t;
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typedef struct
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{
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timer_handle_t hpwm;
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ltc2631_handle_t hoffs;
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mcp41x_handle_t hampl;
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} PWM_handle_t;
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typedef enum
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{
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FG_CHAN1,
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FG_CHAN2,
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FG_CHAN3,
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FG_CHAN_MAX,
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} FG_channel_t;
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typedef enum
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{
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PWM_CHAN1,
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PWM_CHAN2,
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PWM_CHAN3,
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PWM_CHAN_MAX,
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} PWM_channel_t;
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FG_handle_t dds_gen[FG_CHAN_MAX];
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PWM_handle_t pwm_gen[PWM_CHAN_MAX];
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uint8_t ch_to_gen_ch[CHANNEL_MAX] = {FG_CHAN1, FG_CHAN2, FG_CHAN3, PWM_CHAN1, PWM_CHAN2, PWM_CHAN3};
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#define DDS1_CS_PORT GPIOC
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#define DDS2_CS_PORT GPIOC
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#define DDS3_CS_PORT GPIOC
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#define DDS1_CS_PIN GPIO_PIN_0
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#define DDS2_CS_PIN GPIO_PIN_0
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#define DDS3_CS_PIN GPIO_PIN_0
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#define AMP1_CS_PORT GPIOC
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#define AMP2_CS_PORT GPIOC
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#define AMP3_CS_PORT GPIOC
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#define AMP1_CS_PIN GPIO_PIN_0
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#define AMP2_CS_PIN GPIO_PIN_0
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#define AMP3_CS_PIN GPIO_PIN_0
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void gen_init()
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{
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ad9833_init(&dds_gen[FG_CHAN1].hdds, &hspi2, DDS1_CS_PORT, DDS1_CS_PIN);
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ad9833_init(&dds_gen[FG_CHAN2].hdds, &hspi2, DDS2_CS_PORT, DDS2_CS_PIN);
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ad9833_init(&dds_gen[FG_CHAN3].hdds, &hspi2, DDS3_CS_PORT, DDS3_CS_PIN);
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ltc2631_init(&dds_gen[FG_CHAN1].hoffs, &hi2c1, 0x00, LTC2631_8BIT, LTC_REF_2V5);
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ltc2631_init(&dds_gen[FG_CHAN2].hoffs, &hi2c1, 0x01, LTC2631_8BIT, LTC_REF_2V5);
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ltc2631_init(&dds_gen[FG_CHAN3].hoffs, &hi2c1, 0x02, LTC2631_8BIT, LTC_REF_2V5);
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mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP1_CS_PORT, AMP1_CS_PIN, MCP41X_10K);
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mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP2_CS_PORT, AMP2_CS_PIN, MCP41X_10K);
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mcp41x_init(&dds_gen[FG_CHAN1].hampl, &hspi2, AMP3_CS_PORT, AMP3_CS_PIN, MCP41X_10K);
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}
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static void _setAmpliude(mcp41x_handle_t *hampl, uint16_t ampl_x100)
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{
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uint8_t value = (ampl_x100 * UINT8_MAX) / MAX_VOLT_POS;
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ULOG_DEBUG("(%d:_setAmplitude) ampl_x100: %d, value: %d", __LINE__, ampl_x100, value);
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mcp41x_setValue(hampl, value);
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}
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static void _setOffset(ltc2631_handle_t *hoffs, int16_t offs_x100)
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{
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uint32_t value = (offs_x100 + MAX_VOLT_POS) * LTC_REF_2V5;
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ULOG_DEBUG("(%d:_setAmplitude) offs_x100: %d, value: %d", __LINE__, offs_x100, value);
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ltc2631_setOutputVoltage_u(hoffs, value);
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}
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static void _setFreqDdsGen(ad9833_handle_t *hdds, uint32_t freq)
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{
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ULOG_DEBUG("(%d:_setAmplitude) freq: %d", __LINE__, freq);
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ad9833_setFrequency(hdds, CHAN_0, freq);
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}
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static void _setPhaseDdsGen(ad9833_handle_t *hdds, uint32_t phas)
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{
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ULOG_DEBUG("(%d:_setAmplitude) phase: %d", __LINE__, phas);
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ad9833_setPhase(hdds, CHAN_0, phas);
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}
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static void _setWaveDdsGen(ad9833_handle_t *hdds, GEN_wave_t wave)
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{
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ULOG_DEBUG("(%d:_setAmplitude) wave: %d", __LINE__, wave);
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switch (wave)
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{
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case GEN_SIN:
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ad9833_setMode(hdds, MODE_SINE);
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break;
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case GEN_TRI:
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ad9833_setMode(hdds, MODE_TRIANGLE);
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break;
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case GEN_SQR:
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ad9833_setMode(hdds, MODE_SQUARE1);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown wave type: %d", __FILE__, __LINE__, wave);
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break;
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}
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}
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static void _setEnabledDdsGen(ad9833_handle_t *hdds, GEN_fg_t *gen)
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{
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ULOG_DEBUG("(%d:_setAmplitude) phase: %d", __LINE__, gen->enabled);
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switch (gen->enabled)
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{
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case FALSE:
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ad9833_setMode(hdds, MODE_OFF);
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break;
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case TRUE:
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_setWaveDdsGen(hdds, gen->wave);
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break;
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default:
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ULOG_ERROR("%s:%d: Value out of range: %d", __FILE__, __LINE__, gen->enabled);
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break;
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}
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}
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static void _setFreqPwmGen(timer_handle_t *hpwm, uint32_t freq)
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{
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}
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static void _setPhasePwmGen(timer_handle_t *hpwm, uint16_t phas)
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{
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}
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static void _setDutyPwmGen(timer_handle_t *hpwm, uint8_t duty)
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{
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}
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static void _setEnabledPwmGen(timer_handle_t *hpwm, bool_t en)
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{
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}
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void setFreq(GENERATOR_t *gen, GEN_channel_t channel)
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{
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switch (gen->gen_type)
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{
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case GEN_FG_TYPE:
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_setFreqDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->frequency);
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break;
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case GEN_PWM_TYPE:
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_setFreqPwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->frequency);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
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break;
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}
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}
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void setAmplitude(GENERATOR_t *gen, GEN_channel_t channel)
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{
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switch (gen->gen_type)
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{
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case GEN_FG_TYPE:
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_setAmpliude(&dds_gen[ch_to_gen_ch[channel]].hampl, ((GEN_fg_t *)gen->gen)->amplitude);
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break;
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case GEN_PWM_TYPE:
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_setAmpliude(&pwm_gen[ch_to_gen_ch[channel]].hampl, ((GEN_pwm_t *)gen->gen)->amplitude);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
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break;
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}
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}
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void setOfsset(GENERATOR_t *gen, GEN_channel_t channel)
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{
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switch (gen->gen_type)
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{
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case GEN_FG_TYPE:
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_setOffset(&dds_gen[ch_to_gen_ch[channel]].hoffs, ((GEN_fg_t *)gen->gen)->offset);
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break;
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case GEN_PWM_TYPE:
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_setOffset(&pwm_gen[ch_to_gen_ch[channel]].hoffs, ((GEN_pwm_t *)gen->gen)->offset);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
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break;
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}
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}
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void setPhase(GENERATOR_t *gen, GEN_channel_t channel)
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{
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switch (gen->gen_type)
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{
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case GEN_FG_TYPE:
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_setPhaseDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->phase);
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break;
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case GEN_PWM_TYPE:
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_setPhasePwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->phase);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
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break;
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}
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}
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void setWave(GENERATOR_t *gen, GEN_channel_t channel)
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{
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switch (gen->gen_type)
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{
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case GEN_FG_TYPE:
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_setWaveDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen)->wave);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
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break;
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}
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}
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void setDuty(GENERATOR_t *gen, GEN_channel_t channel)
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{
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switch (gen->gen_type)
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{
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case GEN_PWM_TYPE:
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_setDutyPwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->duty);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
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break;
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}
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}
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void setEnabled(GENERATOR_t *gen, GEN_channel_t channel)
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{
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switch (gen->gen_type)
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{
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case GEN_FG_TYPE:
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_setEnabledDdsGen(&dds_gen[ch_to_gen_ch[channel]].hdds, ((GEN_fg_t *)gen->gen));
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break;
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case GEN_PWM_TYPE:
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_setEnabledPwmGen(&pwm_gen[ch_to_gen_ch[channel]].hpwm, ((GEN_pwm_t *)gen->gen)->enabled);
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break;
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default:
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ULOG_ERROR("%s:%d: Unknown generator type: %d", __FILE__, __LINE__, gen->gen_type);
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break;
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}
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}
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void setLink(GENERATOR_t *source_gen, GEN_channel_t source_ch, GENERATOR_t *dest_gen, GEN_channel_t dest_ch)
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{
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}
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